X86ISelLowering.h revision 234353
1//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef X86ISELLOWERING_H 16#define X86ISELLOWERING_H 17 18#include "X86Subtarget.h" 19#include "X86RegisterInfo.h" 20#include "X86MachineFunctionInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetOptions.h" 23#include "llvm/CodeGen/FastISel.h" 24#include "llvm/CodeGen/SelectionDAG.h" 25#include "llvm/CodeGen/CallingConvLower.h" 26 27namespace llvm { 28 namespace X86ISD { 29 // X86 Specific DAG Nodes 30 enum NodeType { 31 // Start the numbering where the builtin ops leave off. 32 FIRST_NUMBER = ISD::BUILTIN_OP_END, 33 34 /// BSF - Bit scan forward. 35 /// BSR - Bit scan reverse. 36 BSF, 37 BSR, 38 39 /// SHLD, SHRD - Double shift instructions. These correspond to 40 /// X86::SHLDxx and X86::SHRDxx instructions. 41 SHLD, 42 SHRD, 43 44 /// FAND - Bitwise logical AND of floating point values. This corresponds 45 /// to X86::ANDPS or X86::ANDPD. 46 FAND, 47 48 /// FOR - Bitwise logical OR of floating point values. This corresponds 49 /// to X86::ORPS or X86::ORPD. 50 FOR, 51 52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds 53 /// to X86::XORPS or X86::XORPD. 54 FXOR, 55 56 /// FSRL - Bitwise logical right shift of floating point values. These 57 /// corresponds to X86::PSRLDQ. 58 FSRL, 59 60 /// CALL - These operations represent an abstract X86 call 61 /// instruction, which includes a bunch of information. In particular the 62 /// operands of these node are: 63 /// 64 /// #0 - The incoming token chain 65 /// #1 - The callee 66 /// #2 - The number of arg bytes the caller pushes on the stack. 67 /// #3 - The number of arg bytes the callee pops off the stack. 68 /// #4 - The value to pass in AL/AX/EAX (optional) 69 /// #5 - The value to pass in DL/DX/EDX (optional) 70 /// 71 /// The result values of these nodes are: 72 /// 73 /// #0 - The outgoing token chain 74 /// #1 - The first register result value (optional) 75 /// #2 - The second register result value (optional) 76 /// 77 CALL, 78 79 /// RDTSC_DAG - This operation implements the lowering for 80 /// readcyclecounter 81 RDTSC_DAG, 82 83 /// X86 compare and logical compare instructions. 84 CMP, COMI, UCOMI, 85 86 /// X86 bit-test instructions. 87 BT, 88 89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS 90 /// operand, usually produced by a CMP instruction. 91 SETCC, 92 93 // Same as SETCC except it's materialized with a sbb and the value is all 94 // one's or all zero's. 95 SETCC_CARRY, // R = carry_bit ? ~0 : 0 96 97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. 98 /// Operands are two FP values to compare; result is a mask of 99 /// 0s or 1s. Generally DTRT for C/C++ with NaNs. 100 FSETCCss, FSETCCsd, 101 102 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values, 103 /// result in an integer GPR. Needs masking for scalar result. 104 FGETSIGNx86, 105 106 /// X86 conditional moves. Operand 0 and operand 1 are the two values 107 /// to select from. Operand 2 is the condition code, and operand 3 is the 108 /// flag operand produced by a CMP or TEST instruction. It also writes a 109 /// flag result. 110 CMOV, 111 112 /// X86 conditional branches. Operand 0 is the chain operand, operand 1 113 /// is the block to branch if condition is true, operand 2 is the 114 /// condition code, and operand 3 is the flag operand produced by a CMP 115 /// or TEST instruction. 116 BRCOND, 117 118 /// Return with a flag operand. Operand 0 is the chain operand, operand 119 /// 1 is the number of bytes of stack to pop. 120 RET_FLAG, 121 122 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx. 123 REP_STOS, 124 125 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx. 126 REP_MOVS, 127 128 /// GlobalBaseReg - On Darwin, this node represents the result of the popl 129 /// at function entry, used for PIC code. 130 GlobalBaseReg, 131 132 /// Wrapper - A wrapper node for TargetConstantPool, 133 /// TargetExternalSymbol, and TargetGlobalAddress. 134 Wrapper, 135 136 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP 137 /// relative displacements. 138 WrapperRIP, 139 140 /// MOVQ2DQ - Copies a 64-bit value from an MMX vector to the low word 141 /// of an XMM vector, with the high word zero filled. 142 MOVQ2DQ, 143 144 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector 145 /// to an MMX vector. If you think this is too close to the previous 146 /// mnemonic, so do I; blame Intel. 147 MOVDQ2Q, 148 149 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to 150 /// i32, corresponds to X86::PEXTRB. 151 PEXTRB, 152 153 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to 154 /// i32, corresponds to X86::PEXTRW. 155 PEXTRW, 156 157 /// INSERTPS - Insert any element of a 4 x float vector into any element 158 /// of a destination 4 x floatvector. 159 INSERTPS, 160 161 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector, 162 /// corresponds to X86::PINSRB. 163 PINSRB, 164 165 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector, 166 /// corresponds to X86::PINSRW. 167 PINSRW, MMX_PINSRW, 168 169 /// PSHUFB - Shuffle 16 8-bit values within a vector. 170 PSHUFB, 171 172 /// ANDNP - Bitwise Logical AND NOT of Packed FP values. 173 ANDNP, 174 175 /// PSIGN - Copy integer sign. 176 PSIGN, 177 178 /// BLENDV - Blend where the selector is an XMM. 179 BLENDV, 180 181 /// BLENDxx - Blend where the selector is an immediate. 182 BLENDPW, 183 BLENDPS, 184 BLENDPD, 185 186 /// HADD - Integer horizontal add. 187 HADD, 188 189 /// HSUB - Integer horizontal sub. 190 HSUB, 191 192 /// FHADD - Floating point horizontal add. 193 FHADD, 194 195 /// FHSUB - Floating point horizontal sub. 196 FHSUB, 197 198 /// FMAX, FMIN - Floating point max and min. 199 /// 200 FMAX, FMIN, 201 202 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal 203 /// approximation. Note that these typically require refinement 204 /// in order to obtain suitable precision. 205 FRSQRT, FRCP, 206 207 // TLSADDR - Thread Local Storage. 208 TLSADDR, 209 210 // TLSCALL - Thread Local Storage. When calling to an OS provided 211 // thunk at the address from an earlier relocation. 212 TLSCALL, 213 214 // EH_RETURN - Exception Handling helpers. 215 EH_RETURN, 216 217 /// TC_RETURN - Tail call return. 218 /// operand #0 chain 219 /// operand #1 callee (register or absolute) 220 /// operand #2 stack adjustment 221 /// operand #3 optional in flag 222 TC_RETURN, 223 224 // VZEXT_MOVL - Vector move low and zero extend. 225 VZEXT_MOVL, 226 227 // VSEXT_MOVL - Vector move low and sign extend. 228 VSEXT_MOVL, 229 230 // VSHL, VSRL - 128-bit vector logical left / right shift 231 VSHLDQ, VSRLDQ, 232 233 // VSHL, VSRL, VSRA - Vector shift elements 234 VSHL, VSRL, VSRA, 235 236 // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate 237 VSHLI, VSRLI, VSRAI, 238 239 // CMPP - Vector packed double/float comparison. 240 CMPP, 241 242 // PCMP* - Vector integer comparisons. 243 PCMPEQ, PCMPGT, 244 245 // VPCOM, VPCOMU - XOP Vector integer comparisons. 246 VPCOM, VPCOMU, 247 248 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results. 249 ADD, SUB, ADC, SBB, SMUL, 250 INC, DEC, OR, XOR, AND, 251 252 ANDN, // ANDN - Bitwise AND NOT with FLAGS results. 253 254 BLSI, // BLSI - Extract lowest set isolated bit 255 BLSMSK, // BLSMSK - Get mask up to lowest set bit 256 BLSR, // BLSR - Reset lowest set bit 257 258 UMUL, // LOW, HI, FLAGS = umul LHS, RHS 259 260 // MUL_IMM - X86 specific multiply by immediate. 261 MUL_IMM, 262 263 // PTEST - Vector bitwise comparisons 264 PTEST, 265 266 // TESTP - Vector packed fp sign bitwise comparisons 267 TESTP, 268 269 // Several flavors of instructions with vector shuffle behaviors. 270 PALIGN, 271 PSHUFD, 272 PSHUFHW, 273 PSHUFLW, 274 SHUFP, 275 MOVDDUP, 276 MOVSHDUP, 277 MOVSLDUP, 278 MOVLHPS, 279 MOVLHPD, 280 MOVHLPS, 281 MOVLPS, 282 MOVLPD, 283 MOVSD, 284 MOVSS, 285 UNPCKL, 286 UNPCKH, 287 VPERMILP, 288 VPERM2X128, 289 VBROADCAST, 290 291 // PMULUDQ - Vector multiply packed unsigned doubleword integers 292 PMULUDQ, 293 294 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack, 295 // according to %al. An operator is needed so that this can be expanded 296 // with control flow. 297 VASTART_SAVE_XMM_REGS, 298 299 // WIN_ALLOCA - Windows's _chkstk call to do stack probing. 300 WIN_ALLOCA, 301 302 // SEG_ALLOCA - For allocating variable amounts of stack space when using 303 // segmented stacks. Check if the current stacklet has enough space, and 304 // falls back to heap allocation if not. 305 SEG_ALLOCA, 306 307 // WIN_FTOL - Windows's _ftol2 runtime routine to do fptoui. 308 WIN_FTOL, 309 310 // Memory barrier 311 MEMBARRIER, 312 MFENCE, 313 SFENCE, 314 LFENCE, 315 316 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG, 317 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG - 318 // Atomic 64-bit binary operations. 319 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, 320 ATOMSUB64_DAG, 321 ATOMOR64_DAG, 322 ATOMXOR64_DAG, 323 ATOMAND64_DAG, 324 ATOMNAND64_DAG, 325 ATOMSWAP64_DAG, 326 327 // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap. 328 LCMPXCHG_DAG, 329 LCMPXCHG8_DAG, 330 LCMPXCHG16_DAG, 331 332 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend. 333 VZEXT_LOAD, 334 335 // FNSTCW16m - Store FP control world into i16 memory. 336 FNSTCW16m, 337 338 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the 339 /// integer destination in memory and a FP reg source. This corresponds 340 /// to the X86::FIST*m instructions and the rounding mode change stuff. It 341 /// has two inputs (token chain and address) and two outputs (int value 342 /// and token chain). 343 FP_TO_INT16_IN_MEM, 344 FP_TO_INT32_IN_MEM, 345 FP_TO_INT64_IN_MEM, 346 347 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the 348 /// integer source in memory and FP reg result. This corresponds to the 349 /// X86::FILD*m instructions. It has three inputs (token chain, address, 350 /// and source type) and two outputs (FP value and token chain). FILD_FLAG 351 /// also produces a flag). 352 FILD, 353 FILD_FLAG, 354 355 /// FLD - This instruction implements an extending load to FP stack slots. 356 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain 357 /// operand, ptr to load from, and a ValueType node indicating the type 358 /// to load to. 359 FLD, 360 361 /// FST - This instruction implements a truncating store to FP stack 362 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a 363 /// chain operand, value to store, address, and a ValueType to store it 364 /// as. 365 FST, 366 367 /// VAARG_64 - This instruction grabs the address of the next argument 368 /// from a va_list. (reads and modifies the va_list in memory) 369 VAARG_64 370 371 // WARNING: Do not add anything in the end unless you want the node to 372 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be 373 // thought as target memory ops! 374 }; 375 } 376 377 /// Define some predicates that are used for node matching. 378 namespace X86 { 379 /// isVEXTRACTF128Index - Return true if the specified 380 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is 381 /// suitable for input to VEXTRACTF128. 382 bool isVEXTRACTF128Index(SDNode *N); 383 384 /// isVINSERTF128Index - Return true if the specified 385 /// INSERT_SUBVECTOR operand specifies a subvector insert that is 386 /// suitable for input to VINSERTF128. 387 bool isVINSERTF128Index(SDNode *N); 388 389 /// getExtractVEXTRACTF128Immediate - Return the appropriate 390 /// immediate to extract the specified EXTRACT_SUBVECTOR index 391 /// with VEXTRACTF128 instructions. 392 unsigned getExtractVEXTRACTF128Immediate(SDNode *N); 393 394 /// getInsertVINSERTF128Immediate - Return the appropriate 395 /// immediate to insert at the specified INSERT_SUBVECTOR index 396 /// with VINSERTF128 instructions. 397 unsigned getInsertVINSERTF128Immediate(SDNode *N); 398 399 /// isZeroNode - Returns true if Elt is a constant zero or a floating point 400 /// constant +0.0. 401 bool isZeroNode(SDValue Elt); 402 403 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be 404 /// fit into displacement field of the instruction. 405 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 406 bool hasSymbolicDisplacement = true); 407 408 409 /// isCalleePop - Determines whether the callee is required to pop its 410 /// own arguments. Callee pop is necessary to support tail calls. 411 bool isCalleePop(CallingConv::ID CallingConv, 412 bool is64Bit, bool IsVarArg, bool TailCallOpt); 413 } 414 415 //===--------------------------------------------------------------------===// 416 // X86TargetLowering - X86 Implementation of the TargetLowering interface 417 class X86TargetLowering : public TargetLowering { 418 public: 419 explicit X86TargetLowering(X86TargetMachine &TM); 420 421 virtual unsigned getJumpTableEncoding() const; 422 423 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i8; } 424 425 virtual const MCExpr * 426 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 427 const MachineBasicBlock *MBB, unsigned uid, 428 MCContext &Ctx) const; 429 430 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 431 /// jumptable. 432 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 433 SelectionDAG &DAG) const; 434 virtual const MCExpr * 435 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 436 unsigned JTI, MCContext &Ctx) const; 437 438 /// getStackPtrReg - Return the stack pointer register we are using: either 439 /// ESP or RSP. 440 unsigned getStackPtrReg() const { return X86StackPtr; } 441 442 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 443 /// function arguments in the caller parameter area. For X86, aggregates 444 /// that contains are placed at 16-byte boundaries while the rest are at 445 /// 4-byte boundaries. 446 virtual unsigned getByValTypeAlignment(Type *Ty) const; 447 448 /// getOptimalMemOpType - Returns the target specific optimal type for load 449 /// and store operations as a result of memset, memcpy, and memmove 450 /// lowering. If DstAlign is zero that means it's safe to destination 451 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 452 /// means there isn't a need to check it against alignment requirement, 453 /// probably because the source does not need to be loaded. If 454 /// 'IsZeroVal' is true, that means it's safe to return a 455 /// non-scalar-integer type, e.g. empty string source, constant, or loaded 456 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 457 /// constant so it does not need to be loaded. 458 /// It returns EVT::Other if the type should be determined using generic 459 /// target-independent logic. 460 virtual EVT 461 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 462 bool IsZeroVal, bool MemcpyStrSrc, 463 MachineFunction &MF) const; 464 465 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 466 /// unaligned memory accesses. of the specified type. 467 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 468 return true; 469 } 470 471 /// LowerOperation - Provide custom lowering hooks for some operations. 472 /// 473 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 474 475 /// ReplaceNodeResults - Replace the results of node with an illegal result 476 /// type with new values built out of custom code. 477 /// 478 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 479 SelectionDAG &DAG) const; 480 481 482 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 483 484 /// isTypeDesirableForOp - Return true if the target has native support for 485 /// the specified value type and it is 'desirable' to use the type for the 486 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 487 /// instruction encodings are longer and some i16 instructions are slow. 488 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const; 489 490 /// isTypeDesirable - Return true if the target has native support for the 491 /// specified value type and it is 'desirable' to use the type. e.g. On x86 492 /// i16 is legal, but undesirable since i16 instruction encodings are longer 493 /// and some i16 instructions are slow. 494 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const; 495 496 virtual MachineBasicBlock * 497 EmitInstrWithCustomInserter(MachineInstr *MI, 498 MachineBasicBlock *MBB) const; 499 500 501 /// getTargetNodeName - This method returns the name of a target specific 502 /// DAG node. 503 virtual const char *getTargetNodeName(unsigned Opcode) const; 504 505 /// getSetCCResultType - Return the value type to use for ISD::SETCC. 506 virtual EVT getSetCCResultType(EVT VT) const; 507 508 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 509 /// in Mask are known to be either zero or one and return them in the 510 /// KnownZero/KnownOne bitsets. 511 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 512 APInt &KnownZero, 513 APInt &KnownOne, 514 const SelectionDAG &DAG, 515 unsigned Depth = 0) const; 516 517 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the 518 // operation that are sign bits. 519 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 520 unsigned Depth) const; 521 522 virtual bool 523 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 524 525 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 526 527 virtual bool ExpandInlineAsm(CallInst *CI) const; 528 529 ConstraintType getConstraintType(const std::string &Constraint) const; 530 531 /// Examine constraint string and operand type and determine a weight value. 532 /// The operand object must already have been set up with the operand type. 533 virtual ConstraintWeight getSingleConstraintMatchWeight( 534 AsmOperandInfo &info, const char *constraint) const; 535 536 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 537 538 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 539 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 540 /// true it means one of the asm constraint of the inline asm instruction 541 /// being processed is 'm'. 542 virtual void LowerAsmOperandForConstraint(SDValue Op, 543 std::string &Constraint, 544 std::vector<SDValue> &Ops, 545 SelectionDAG &DAG) const; 546 547 /// getRegForInlineAsmConstraint - Given a physical register constraint 548 /// (e.g. {edx}), return the register number and the register class for the 549 /// register. This should only be used for C_Register constraints. On 550 /// error, this returns a register number of 0. 551 std::pair<unsigned, const TargetRegisterClass*> 552 getRegForInlineAsmConstraint(const std::string &Constraint, 553 EVT VT) const; 554 555 /// isLegalAddressingMode - Return true if the addressing mode represented 556 /// by AM is legal for this target, for a load/store of the specified type. 557 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const; 558 559 /// isTruncateFree - Return true if it's free to truncate a value of 560 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 561 /// register EAX to i16 by referencing its sub-register AX. 562 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const; 563 virtual bool isTruncateFree(EVT VT1, EVT VT2) const; 564 565 /// isZExtFree - Return true if any actual instruction that defines a 566 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 567 /// register. This does not necessarily include registers defined in 568 /// unknown ways, such as incoming arguments, or copies from unknown 569 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 570 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 571 /// all instructions that define 32-bit values implicit zero-extend the 572 /// result out to 64 bits. 573 virtual bool isZExtFree(Type *Ty1, Type *Ty2) const; 574 virtual bool isZExtFree(EVT VT1, EVT VT2) const; 575 576 /// isNarrowingProfitable - Return true if it's profitable to narrow 577 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 578 /// from i32 to i8 but not from i32 to i16. 579 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const; 580 581 /// isFPImmLegal - Returns true if the target can instruction select the 582 /// specified FP immediate natively. If false, the legalizer will 583 /// materialize the FP immediate as a load from a constant pool. 584 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 585 586 /// isShuffleMaskLegal - Targets can use this to indicate that they only 587 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 588 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask 589 /// values are assumed to be legal. 590 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 591 EVT VT) const; 592 593 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 594 /// used by Targets can use this to indicate if there is a suitable 595 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 596 /// pool entry. 597 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 598 EVT VT) const; 599 600 /// ShouldShrinkFPConstant - If true, then instruction selection should 601 /// seek to shrink the FP constant of the specified type to a smaller type 602 /// in order to save space and / or reduce runtime. 603 virtual bool ShouldShrinkFPConstant(EVT VT) const { 604 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more 605 // expensive than a straight movsd. On the other hand, it's important to 606 // shrink long double fp constant since fldt is very slow. 607 return !X86ScalarSSEf64 || VT == MVT::f80; 608 } 609 610 const X86Subtarget* getSubtarget() const { 611 return Subtarget; 612 } 613 614 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 615 /// computed in an SSE register, not on the X87 floating point stack. 616 bool isScalarFPTypeInSSEReg(EVT VT) const { 617 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 618 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 619 } 620 621 /// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine 622 /// for fptoui. 623 bool isTargetFTOL() const { 624 return Subtarget->isTargetWindows() && !Subtarget->is64Bit(); 625 } 626 627 /// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be 628 /// used for fptoui to the given type. 629 bool isIntegerTypeFTOL(EVT VT) const { 630 return isTargetFTOL() && VT == MVT::i64; 631 } 632 633 /// createFastISel - This method returns a target specific FastISel object, 634 /// or null if the target does not support "fast" ISel. 635 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const; 636 637 /// getStackCookieLocation - Return true if the target stores stack 638 /// protector cookies at a fixed offset in some non-standard address 639 /// space, and populates the address space and offset as 640 /// appropriate. 641 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const; 642 643 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, 644 SelectionDAG &DAG) const; 645 646 protected: 647 std::pair<const TargetRegisterClass*, uint8_t> 648 findRepresentativeClass(EVT VT) const; 649 650 private: 651 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 652 /// make the right decision when generating code for different targets. 653 const X86Subtarget *Subtarget; 654 const X86RegisterInfo *RegInfo; 655 const TargetData *TD; 656 657 /// X86StackPtr - X86 physical register used as stack ptr. 658 unsigned X86StackPtr; 659 660 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 661 /// floating point ops. 662 /// When SSE is available, use it for f32 operations. 663 /// When SSE2 is available, use it for f64 operations. 664 bool X86ScalarSSEf32; 665 bool X86ScalarSSEf64; 666 667 /// LegalFPImmediates - A list of legal fp immediates. 668 std::vector<APFloat> LegalFPImmediates; 669 670 /// addLegalFPImmediate - Indicate that this x86 target can instruction 671 /// select the specified FP immediate natively. 672 void addLegalFPImmediate(const APFloat& Imm) { 673 LegalFPImmediates.push_back(Imm); 674 } 675 676 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 677 CallingConv::ID CallConv, bool isVarArg, 678 const SmallVectorImpl<ISD::InputArg> &Ins, 679 DebugLoc dl, SelectionDAG &DAG, 680 SmallVectorImpl<SDValue> &InVals) const; 681 SDValue LowerMemArgument(SDValue Chain, 682 CallingConv::ID CallConv, 683 const SmallVectorImpl<ISD::InputArg> &ArgInfo, 684 DebugLoc dl, SelectionDAG &DAG, 685 const CCValAssign &VA, MachineFrameInfo *MFI, 686 unsigned i) const; 687 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 688 DebugLoc dl, SelectionDAG &DAG, 689 const CCValAssign &VA, 690 ISD::ArgFlagsTy Flags) const; 691 692 // Call lowering helpers. 693 694 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 695 /// for tail call optimization. Targets which want to do tail call 696 /// optimization should implement this function. 697 bool IsEligibleForTailCallOptimization(SDValue Callee, 698 CallingConv::ID CalleeCC, 699 bool isVarArg, 700 bool isCalleeStructRet, 701 bool isCallerStructRet, 702 const SmallVectorImpl<ISD::OutputArg> &Outs, 703 const SmallVectorImpl<SDValue> &OutVals, 704 const SmallVectorImpl<ISD::InputArg> &Ins, 705 SelectionDAG& DAG) const; 706 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const; 707 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, 708 SDValue Chain, bool IsTailCall, bool Is64Bit, 709 int FPDiff, DebugLoc dl) const; 710 711 unsigned GetAlignedArgumentStackSize(unsigned StackSize, 712 SelectionDAG &DAG) const; 713 714 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, 715 bool isSigned, 716 bool isReplace) const; 717 718 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 719 SelectionDAG &DAG) const; 720 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 721 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 722 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 723 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 724 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const; 725 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 726 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const; 727 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 728 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 729 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 730 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 731 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 732 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 733 int64_t Offset, SelectionDAG &DAG) const; 734 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 735 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 736 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const; 737 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const; 738 SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const; 739 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 740 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 741 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const; 742 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const; 743 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 744 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const; 745 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const; 746 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const; 747 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 748 SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const; 749 SDValue LowerToBT(SDValue And, ISD::CondCode CC, 750 DebugLoc dl, SelectionDAG &DAG) const; 751 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 752 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const; 753 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 754 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 755 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const; 756 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 757 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 758 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 759 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 760 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 761 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 762 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 763 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 764 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const; 765 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 766 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 767 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 768 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 769 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const; 770 SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) const; 771 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const; 772 SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const; 773 SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) const; 774 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 775 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const; 776 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const; 777 778 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 779 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const; 780 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const; 781 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const; 782 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; 783 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; 784 SDValue PerformTruncateCombine(SDNode* N, SelectionDAG &DAG, DAGCombinerInfo &DCI) const; 785 786 // Utility functions to help LowerVECTOR_SHUFFLE 787 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const; 788 SDValue LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const; 789 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const; 790 791 virtual SDValue 792 LowerFormalArguments(SDValue Chain, 793 CallingConv::ID CallConv, bool isVarArg, 794 const SmallVectorImpl<ISD::InputArg> &Ins, 795 DebugLoc dl, SelectionDAG &DAG, 796 SmallVectorImpl<SDValue> &InVals) const; 797 virtual SDValue 798 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, 799 bool isVarArg, bool doesNotRet, bool &isTailCall, 800 const SmallVectorImpl<ISD::OutputArg> &Outs, 801 const SmallVectorImpl<SDValue> &OutVals, 802 const SmallVectorImpl<ISD::InputArg> &Ins, 803 DebugLoc dl, SelectionDAG &DAG, 804 SmallVectorImpl<SDValue> &InVals) const; 805 806 virtual SDValue 807 LowerReturn(SDValue Chain, 808 CallingConv::ID CallConv, bool isVarArg, 809 const SmallVectorImpl<ISD::OutputArg> &Outs, 810 const SmallVectorImpl<SDValue> &OutVals, 811 DebugLoc dl, SelectionDAG &DAG) const; 812 813 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const; 814 815 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const; 816 817 virtual EVT 818 getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 819 ISD::NodeType ExtendKind) const; 820 821 virtual bool 822 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 823 bool isVarArg, 824 const SmallVectorImpl<ISD::OutputArg> &Outs, 825 LLVMContext &Context) const; 826 827 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results, 828 SelectionDAG &DAG, unsigned NewOp) const; 829 830 /// Utility function to emit string processing sse4.2 instructions 831 /// that return in xmm0. 832 /// This takes the instruction to expand, the associated machine basic 833 /// block, the number of args, and whether or not the second arg is 834 /// in memory or not. 835 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB, 836 unsigned argNum, bool inMem) const; 837 838 /// Utility functions to emit monitor and mwait instructions. These 839 /// need to make sure that the arguments to the intrinsic are in the 840 /// correct registers. 841 MachineBasicBlock *EmitMonitor(MachineInstr *MI, 842 MachineBasicBlock *BB) const; 843 MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const; 844 845 /// Utility function to emit atomic bitwise operations (and, or, xor). 846 /// It takes the bitwise instruction to expand, the associated machine basic 847 /// block, and the associated X86 opcodes for reg/reg and reg/imm. 848 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter( 849 MachineInstr *BInstr, 850 MachineBasicBlock *BB, 851 unsigned regOpc, 852 unsigned immOpc, 853 unsigned loadOpc, 854 unsigned cxchgOpc, 855 unsigned notOpc, 856 unsigned EAXreg, 857 const TargetRegisterClass *RC, 858 bool invSrc = false) const; 859 860 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter( 861 MachineInstr *BInstr, 862 MachineBasicBlock *BB, 863 unsigned regOpcL, 864 unsigned regOpcH, 865 unsigned immOpcL, 866 unsigned immOpcH, 867 bool invSrc = false) const; 868 869 /// Utility function to emit atomic min and max. It takes the min/max 870 /// instruction to expand, the associated basic block, and the associated 871 /// cmov opcode for moving the min or max value. 872 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr, 873 MachineBasicBlock *BB, 874 unsigned cmovOpc) const; 875 876 // Utility function to emit the low-level va_arg code for X86-64. 877 MachineBasicBlock *EmitVAARG64WithCustomInserter( 878 MachineInstr *MI, 879 MachineBasicBlock *MBB) const; 880 881 /// Utility function to emit the xmm reg save portion of va_start. 882 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter( 883 MachineInstr *BInstr, 884 MachineBasicBlock *BB) const; 885 886 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I, 887 MachineBasicBlock *BB) const; 888 889 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI, 890 MachineBasicBlock *BB) const; 891 892 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI, 893 MachineBasicBlock *BB, 894 bool Is64Bit) const; 895 896 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI, 897 MachineBasicBlock *BB) const; 898 899 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI, 900 MachineBasicBlock *BB) const; 901 902 /// Emit nodes that will be selected as "test Op0,Op0", or something 903 /// equivalent, for use with the given x86 condition code. 904 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const; 905 906 /// Emit nodes that will be selected as "cmp Op0,Op1", or something 907 /// equivalent, for use with the given x86 condition code. 908 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 909 SelectionDAG &DAG) const; 910 }; 911 912 namespace X86 { 913 FastISel *createFastISel(FunctionLoweringInfo &funcInfo); 914 } 915} 916 917#endif // X86ISELLOWERING_H 918