X86ISelLowering.h revision 207618
1//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef X86ISELLOWERING_H 16#define X86ISELLOWERING_H 17 18#include "X86Subtarget.h" 19#include "X86RegisterInfo.h" 20#include "X86MachineFunctionInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetOptions.h" 23#include "llvm/CodeGen/FastISel.h" 24#include "llvm/CodeGen/SelectionDAG.h" 25#include "llvm/CodeGen/CallingConvLower.h" 26 27namespace llvm { 28 namespace X86ISD { 29 // X86 Specific DAG Nodes 30 enum NodeType { 31 // Start the numbering where the builtin ops leave off. 32 FIRST_NUMBER = ISD::BUILTIN_OP_END, 33 34 /// BSF - Bit scan forward. 35 /// BSR - Bit scan reverse. 36 BSF, 37 BSR, 38 39 /// SHLD, SHRD - Double shift instructions. These correspond to 40 /// X86::SHLDxx and X86::SHRDxx instructions. 41 SHLD, 42 SHRD, 43 44 /// FAND - Bitwise logical AND of floating point values. This corresponds 45 /// to X86::ANDPS or X86::ANDPD. 46 FAND, 47 48 /// FOR - Bitwise logical OR of floating point values. This corresponds 49 /// to X86::ORPS or X86::ORPD. 50 FOR, 51 52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds 53 /// to X86::XORPS or X86::XORPD. 54 FXOR, 55 56 /// FSRL - Bitwise logical right shift of floating point values. These 57 /// corresponds to X86::PSRLDQ. 58 FSRL, 59 60 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the 61 /// integer source in memory and FP reg result. This corresponds to the 62 /// X86::FILD*m instructions. It has three inputs (token chain, address, 63 /// and source type) and two outputs (FP value and token chain). FILD_FLAG 64 /// also produces a flag). 65 FILD, 66 FILD_FLAG, 67 68 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the 69 /// integer destination in memory and a FP reg source. This corresponds 70 /// to the X86::FIST*m instructions and the rounding mode change stuff. It 71 /// has two inputs (token chain and address) and two outputs (int value 72 /// and token chain). 73 FP_TO_INT16_IN_MEM, 74 FP_TO_INT32_IN_MEM, 75 FP_TO_INT64_IN_MEM, 76 77 /// FLD - This instruction implements an extending load to FP stack slots. 78 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain 79 /// operand, ptr to load from, and a ValueType node indicating the type 80 /// to load to. 81 FLD, 82 83 /// FST - This instruction implements a truncating store to FP stack 84 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a 85 /// chain operand, value to store, address, and a ValueType to store it 86 /// as. 87 FST, 88 89 /// CALL - These operations represent an abstract X86 call 90 /// instruction, which includes a bunch of information. In particular the 91 /// operands of these node are: 92 /// 93 /// #0 - The incoming token chain 94 /// #1 - The callee 95 /// #2 - The number of arg bytes the caller pushes on the stack. 96 /// #3 - The number of arg bytes the callee pops off the stack. 97 /// #4 - The value to pass in AL/AX/EAX (optional) 98 /// #5 - The value to pass in DL/DX/EDX (optional) 99 /// 100 /// The result values of these nodes are: 101 /// 102 /// #0 - The outgoing token chain 103 /// #1 - The first register result value (optional) 104 /// #2 - The second register result value (optional) 105 /// 106 CALL, 107 108 /// RDTSC_DAG - This operation implements the lowering for 109 /// readcyclecounter 110 RDTSC_DAG, 111 112 /// X86 compare and logical compare instructions. 113 CMP, COMI, UCOMI, 114 115 /// X86 bit-test instructions. 116 BT, 117 118 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the flag 119 /// operand produced by a CMP instruction. 120 SETCC, 121 122 // Same as SETCC except it's materialized with a sbb and the value is all 123 // one's or all zero's. 124 SETCC_CARRY, 125 126 /// X86 conditional moves. Operand 0 and operand 1 are the two values 127 /// to select from. Operand 2 is the condition code, and operand 3 is the 128 /// flag operand produced by a CMP or TEST instruction. It also writes a 129 /// flag result. 130 CMOV, 131 132 /// X86 conditional branches. Operand 0 is the chain operand, operand 1 133 /// is the block to branch if condition is true, operand 2 is the 134 /// condition code, and operand 3 is the flag operand produced by a CMP 135 /// or TEST instruction. 136 BRCOND, 137 138 /// Return with a flag operand. Operand 0 is the chain operand, operand 139 /// 1 is the number of bytes of stack to pop. 140 RET_FLAG, 141 142 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx. 143 REP_STOS, 144 145 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx. 146 REP_MOVS, 147 148 /// GlobalBaseReg - On Darwin, this node represents the result of the popl 149 /// at function entry, used for PIC code. 150 GlobalBaseReg, 151 152 /// Wrapper - A wrapper node for TargetConstantPool, 153 /// TargetExternalSymbol, and TargetGlobalAddress. 154 Wrapper, 155 156 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP 157 /// relative displacements. 158 WrapperRIP, 159 160 /// MOVQ2DQ - Copies a 64-bit value from a vector to another vector. 161 /// Can be used to move a vector value from a MMX register to a XMM 162 /// register. 163 MOVQ2DQ, 164 165 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to 166 /// i32, corresponds to X86::PEXTRB. 167 PEXTRB, 168 169 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to 170 /// i32, corresponds to X86::PEXTRW. 171 PEXTRW, 172 173 /// INSERTPS - Insert any element of a 4 x float vector into any element 174 /// of a destination 4 x floatvector. 175 INSERTPS, 176 177 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector, 178 /// corresponds to X86::PINSRB. 179 PINSRB, 180 181 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector, 182 /// corresponds to X86::PINSRW. 183 PINSRW, MMX_PINSRW, 184 185 /// PSHUFB - Shuffle 16 8-bit values within a vector. 186 PSHUFB, 187 188 /// FMAX, FMIN - Floating point max and min. 189 /// 190 FMAX, FMIN, 191 192 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal 193 /// approximation. Note that these typically require refinement 194 /// in order to obtain suitable precision. 195 FRSQRT, FRCP, 196 197 // TLSADDR - Thread Local Storage. 198 TLSADDR, 199 200 // SegmentBaseAddress - The address segment:0 201 SegmentBaseAddress, 202 203 // EH_RETURN - Exception Handling helpers. 204 EH_RETURN, 205 206 /// TC_RETURN - Tail call return. 207 /// operand #0 chain 208 /// operand #1 callee (register or absolute) 209 /// operand #2 stack adjustment 210 /// operand #3 optional in flag 211 TC_RETURN, 212 213 // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap. 214 LCMPXCHG_DAG, 215 LCMPXCHG8_DAG, 216 217 // FNSTCW16m - Store FP control world into i16 memory. 218 FNSTCW16m, 219 220 // VZEXT_MOVL - Vector move low and zero extend. 221 VZEXT_MOVL, 222 223 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend. 224 VZEXT_LOAD, 225 226 // VSHL, VSRL - Vector logical left / right shift. 227 VSHL, VSRL, 228 229 // CMPPD, CMPPS - Vector double/float comparison. 230 // CMPPD, CMPPS - Vector double/float comparison. 231 CMPPD, CMPPS, 232 233 // PCMP* - Vector integer comparisons. 234 PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ, 235 PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ, 236 237 // ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results. 238 ADD, SUB, SMUL, UMUL, 239 INC, DEC, OR, XOR, AND, 240 241 // MUL_IMM - X86 specific multiply by immediate. 242 MUL_IMM, 243 244 // PTEST - Vector bitwise comparisons 245 PTEST, 246 247 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack, 248 // according to %al. An operator is needed so that this can be expanded 249 // with control flow. 250 VASTART_SAVE_XMM_REGS, 251 252 // MINGW_ALLOCA - MingW's __alloca call to do stack probing. 253 MINGW_ALLOCA, 254 255 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG, 256 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG - 257 // Atomic 64-bit binary operations. 258 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, 259 ATOMSUB64_DAG, 260 ATOMOR64_DAG, 261 ATOMXOR64_DAG, 262 ATOMAND64_DAG, 263 ATOMNAND64_DAG, 264 ATOMSWAP64_DAG 265 266 // WARNING: Do not add anything in the end unless you want the node to 267 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be 268 // thought as target memory ops! 269 }; 270 } 271 272 /// Define some predicates that are used for node matching. 273 namespace X86 { 274 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand 275 /// specifies a shuffle of elements that is suitable for input to PSHUFD. 276 bool isPSHUFDMask(ShuffleVectorSDNode *N); 277 278 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand 279 /// specifies a shuffle of elements that is suitable for input to PSHUFD. 280 bool isPSHUFHWMask(ShuffleVectorSDNode *N); 281 282 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand 283 /// specifies a shuffle of elements that is suitable for input to PSHUFD. 284 bool isPSHUFLWMask(ShuffleVectorSDNode *N); 285 286 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 287 /// specifies a shuffle of elements that is suitable for input to SHUFP*. 288 bool isSHUFPMask(ShuffleVectorSDNode *N); 289 290 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 291 /// specifies a shuffle of elements that is suitable for input to MOVHLPS. 292 bool isMOVHLPSMask(ShuffleVectorSDNode *N); 293 294 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 295 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 296 /// <2, 3, 2, 3> 297 bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N); 298 299 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 300 /// specifies a shuffle of elements that is suitable for MOVLP{S|D}. 301 bool isMOVLPMask(ShuffleVectorSDNode *N); 302 303 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand 304 /// specifies a shuffle of elements that is suitable for MOVHP{S|D}. 305 /// as well as MOVLHPS. 306 bool isMOVLHPSMask(ShuffleVectorSDNode *N); 307 308 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 309 /// specifies a shuffle of elements that is suitable for input to UNPCKL. 310 bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false); 311 312 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 313 /// specifies a shuffle of elements that is suitable for input to UNPCKH. 314 bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false); 315 316 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 317 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 318 /// <0, 0, 1, 1> 319 bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N); 320 321 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 322 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 323 /// <2, 2, 3, 3> 324 bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N); 325 326 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 327 /// specifies a shuffle of elements that is suitable for input to MOVSS, 328 /// MOVSD, and MOVD, i.e. setting the lowest element. 329 bool isMOVLMask(ShuffleVectorSDNode *N); 330 331 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 332 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 333 bool isMOVSHDUPMask(ShuffleVectorSDNode *N); 334 335 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 336 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 337 bool isMOVSLDUPMask(ShuffleVectorSDNode *N); 338 339 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 340 /// specifies a shuffle of elements that is suitable for input to MOVDDUP. 341 bool isMOVDDUPMask(ShuffleVectorSDNode *N); 342 343 /// isPALIGNRMask - Return true if the specified VECTOR_SHUFFLE operand 344 /// specifies a shuffle of elements that is suitable for input to PALIGNR. 345 bool isPALIGNRMask(ShuffleVectorSDNode *N); 346 347 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 348 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* 349 /// instructions. 350 unsigned getShuffleSHUFImmediate(SDNode *N); 351 352 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 353 /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction. 354 unsigned getShufflePSHUFHWImmediate(SDNode *N); 355 356 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 357 /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction. 358 unsigned getShufflePSHUFLWImmediate(SDNode *N); 359 360 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 361 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 362 unsigned getShufflePALIGNRImmediate(SDNode *N); 363 364 /// isZeroNode - Returns true if Elt is a constant zero or a floating point 365 /// constant +0.0. 366 bool isZeroNode(SDValue Elt); 367 368 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be 369 /// fit into displacement field of the instruction. 370 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 371 bool hasSymbolicDisplacement = true); 372 } 373 374 //===--------------------------------------------------------------------===// 375 // X86TargetLowering - X86 Implementation of the TargetLowering interface 376 class X86TargetLowering : public TargetLowering { 377 public: 378 explicit X86TargetLowering(X86TargetMachine &TM); 379 380 /// getPICBaseSymbol - Return the X86-32 PIC base. 381 MCSymbol *getPICBaseSymbol(const MachineFunction *MF, MCContext &Ctx) const; 382 383 virtual unsigned getJumpTableEncoding() const; 384 385 virtual const MCExpr * 386 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 387 const MachineBasicBlock *MBB, unsigned uid, 388 MCContext &Ctx) const; 389 390 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 391 /// jumptable. 392 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 393 SelectionDAG &DAG) const; 394 virtual const MCExpr * 395 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 396 unsigned JTI, MCContext &Ctx) const; 397 398 /// getStackPtrReg - Return the stack pointer register we are using: either 399 /// ESP or RSP. 400 unsigned getStackPtrReg() const { return X86StackPtr; } 401 402 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 403 /// function arguments in the caller parameter area. For X86, aggregates 404 /// that contains are placed at 16-byte boundaries while the rest are at 405 /// 4-byte boundaries. 406 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 407 408 /// getOptimalMemOpType - Returns the target specific optimal type for load 409 /// and store operations as a result of memset, memcpy, and memmove 410 /// lowering. If DstAlign is zero that means it's safe to destination 411 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 412 /// means there isn't a need to check it against alignment requirement, 413 /// probably because the source does not need to be loaded. If 414 /// 'NonScalarIntSafe' is true, that means it's safe to return a 415 /// non-scalar-integer type, e.g. empty string source, constant, or loaded 416 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 417 /// constant so it does not need to be loaded. 418 /// It returns EVT::Other if the type should be determined using generic 419 /// target-independent logic. 420 virtual EVT 421 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 422 bool NonScalarIntSafe, bool MemcpyStrSrc, 423 MachineFunction &MF) const; 424 425 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 426 /// unaligned memory accesses. of the specified type. 427 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 428 return true; 429 } 430 431 /// LowerOperation - Provide custom lowering hooks for some operations. 432 /// 433 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 434 435 /// ReplaceNodeResults - Replace the results of node with an illegal result 436 /// type with new values built out of custom code. 437 /// 438 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 439 SelectionDAG &DAG) const; 440 441 442 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 443 444 /// isTypeDesirableForOp - Return true if the target has native support for 445 /// the specified value type and it is 'desirable' to use the type for the 446 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 447 /// instruction encodings are longer and some i16 instructions are slow. 448 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const; 449 450 /// isTypeDesirable - Return true if the target has native support for the 451 /// specified value type and it is 'desirable' to use the type. e.g. On x86 452 /// i16 is legal, but undesirable since i16 instruction encodings are longer 453 /// and some i16 instructions are slow. 454 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const; 455 456 virtual MachineBasicBlock * 457 EmitInstrWithCustomInserter(MachineInstr *MI, 458 MachineBasicBlock *MBB) const; 459 460 461 /// getTargetNodeName - This method returns the name of a target specific 462 /// DAG node. 463 virtual const char *getTargetNodeName(unsigned Opcode) const; 464 465 /// getSetCCResultType - Return the ISD::SETCC ValueType 466 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const; 467 468 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 469 /// in Mask are known to be either zero or one and return them in the 470 /// KnownZero/KnownOne bitsets. 471 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 472 const APInt &Mask, 473 APInt &KnownZero, 474 APInt &KnownOne, 475 const SelectionDAG &DAG, 476 unsigned Depth = 0) const; 477 478 virtual bool 479 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 480 481 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 482 483 virtual bool ExpandInlineAsm(CallInst *CI) const; 484 485 ConstraintType getConstraintType(const std::string &Constraint) const; 486 487 std::vector<unsigned> 488 getRegClassForInlineAsmConstraint(const std::string &Constraint, 489 EVT VT) const; 490 491 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 492 493 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 494 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 495 /// true it means one of the asm constraint of the inline asm instruction 496 /// being processed is 'm'. 497 virtual void LowerAsmOperandForConstraint(SDValue Op, 498 char ConstraintLetter, 499 bool hasMemory, 500 std::vector<SDValue> &Ops, 501 SelectionDAG &DAG) const; 502 503 /// getRegForInlineAsmConstraint - Given a physical register constraint 504 /// (e.g. {edx}), return the register number and the register class for the 505 /// register. This should only be used for C_Register constraints. On 506 /// error, this returns a register number of 0. 507 std::pair<unsigned, const TargetRegisterClass*> 508 getRegForInlineAsmConstraint(const std::string &Constraint, 509 EVT VT) const; 510 511 /// isLegalAddressingMode - Return true if the addressing mode represented 512 /// by AM is legal for this target, for a load/store of the specified type. 513 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 514 515 /// isTruncateFree - Return true if it's free to truncate a value of 516 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 517 /// register EAX to i16 by referencing its sub-register AX. 518 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const; 519 virtual bool isTruncateFree(EVT VT1, EVT VT2) const; 520 521 /// isZExtFree - Return true if any actual instruction that defines a 522 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 523 /// register. This does not necessarily include registers defined in 524 /// unknown ways, such as incoming arguments, or copies from unknown 525 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 526 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 527 /// all instructions that define 32-bit values implicit zero-extend the 528 /// result out to 64 bits. 529 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const; 530 virtual bool isZExtFree(EVT VT1, EVT VT2) const; 531 532 /// isNarrowingProfitable - Return true if it's profitable to narrow 533 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 534 /// from i32 to i8 but not from i32 to i16. 535 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const; 536 537 /// isFPImmLegal - Returns true if the target can instruction select the 538 /// specified FP immediate natively. If false, the legalizer will 539 /// materialize the FP immediate as a load from a constant pool. 540 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 541 542 /// isShuffleMaskLegal - Targets can use this to indicate that they only 543 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 544 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask 545 /// values are assumed to be legal. 546 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 547 EVT VT) const; 548 549 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 550 /// used by Targets can use this to indicate if there is a suitable 551 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 552 /// pool entry. 553 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 554 EVT VT) const; 555 556 /// ShouldShrinkFPConstant - If true, then instruction selection should 557 /// seek to shrink the FP constant of the specified type to a smaller type 558 /// in order to save space and / or reduce runtime. 559 virtual bool ShouldShrinkFPConstant(EVT VT) const { 560 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more 561 // expensive than a straight movsd. On the other hand, it's important to 562 // shrink long double fp constant since fldt is very slow. 563 return !X86ScalarSSEf64 || VT == MVT::f80; 564 } 565 566 virtual const X86Subtarget* getSubtarget() const { 567 return Subtarget; 568 } 569 570 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 571 /// computed in an SSE register, not on the X87 floating point stack. 572 bool isScalarFPTypeInSSEReg(EVT VT) const { 573 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 574 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 575 } 576 577 /// createFastISel - This method returns a target specific FastISel object, 578 /// or null if the target does not support "fast" ISel. 579 virtual FastISel * 580 createFastISel(MachineFunction &mf, 581 DenseMap<const Value *, unsigned> &, 582 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 583 DenseMap<const AllocaInst *, int> &, 584 std::vector<std::pair<MachineInstr*, unsigned> > & 585#ifndef NDEBUG 586 , SmallSet<const Instruction *, 8> & 587#endif 588 ) const; 589 590 /// getFunctionAlignment - Return the Log2 alignment of this function. 591 virtual unsigned getFunctionAlignment(const Function *F) const; 592 593 private: 594 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 595 /// make the right decision when generating code for different targets. 596 const X86Subtarget *Subtarget; 597 const X86RegisterInfo *RegInfo; 598 const TargetData *TD; 599 600 /// X86StackPtr - X86 physical register used as stack ptr. 601 unsigned X86StackPtr; 602 603 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 604 /// floating point ops. 605 /// When SSE is available, use it for f32 operations. 606 /// When SSE2 is available, use it for f64 operations. 607 bool X86ScalarSSEf32; 608 bool X86ScalarSSEf64; 609 610 /// LegalFPImmediates - A list of legal fp immediates. 611 std::vector<APFloat> LegalFPImmediates; 612 613 /// addLegalFPImmediate - Indicate that this x86 target can instruction 614 /// select the specified FP immediate natively. 615 void addLegalFPImmediate(const APFloat& Imm) { 616 LegalFPImmediates.push_back(Imm); 617 } 618 619 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 620 CallingConv::ID CallConv, bool isVarArg, 621 const SmallVectorImpl<ISD::InputArg> &Ins, 622 DebugLoc dl, SelectionDAG &DAG, 623 SmallVectorImpl<SDValue> &InVals) const; 624 SDValue LowerMemArgument(SDValue Chain, 625 CallingConv::ID CallConv, 626 const SmallVectorImpl<ISD::InputArg> &ArgInfo, 627 DebugLoc dl, SelectionDAG &DAG, 628 const CCValAssign &VA, MachineFrameInfo *MFI, 629 unsigned i) const; 630 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 631 DebugLoc dl, SelectionDAG &DAG, 632 const CCValAssign &VA, 633 ISD::ArgFlagsTy Flags) const; 634 635 // Call lowering helpers. 636 637 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 638 /// for tail call optimization. Targets which want to do tail call 639 /// optimization should implement this function. 640 bool IsEligibleForTailCallOptimization(SDValue Callee, 641 CallingConv::ID CalleeCC, 642 bool isVarArg, 643 bool isCalleeStructRet, 644 bool isCallerStructRet, 645 const SmallVectorImpl<ISD::OutputArg> &Outs, 646 const SmallVectorImpl<ISD::InputArg> &Ins, 647 SelectionDAG& DAG) const; 648 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const; 649 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, 650 SDValue Chain, bool IsTailCall, bool Is64Bit, 651 int FPDiff, DebugLoc dl) const; 652 653 CCAssignFn *CCAssignFnForNode(CallingConv::ID CallConv) const; 654 unsigned GetAlignedArgumentStackSize(unsigned StackSize, 655 SelectionDAG &DAG) const; 656 657 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, 658 bool isSigned) const; 659 660 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 661 SelectionDAG &DAG) const; 662 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 663 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 664 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 665 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 666 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const; 667 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 668 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const; 669 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 670 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 671 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 672 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 673 int64_t Offset, SelectionDAG &DAG) const; 674 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 675 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 676 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const; 677 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const; 678 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, 679 SelectionDAG &DAG) const; 680 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 681 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 682 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const; 683 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const; 684 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 685 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const; 686 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const; 687 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const; 688 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 689 SDValue LowerToBT(SDValue And, ISD::CondCode CC, 690 DebugLoc dl, SelectionDAG &DAG) const; 691 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 692 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const; 693 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 694 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 695 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const; 696 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 697 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 698 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 699 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 700 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 701 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 702 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 703 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 704 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const; 705 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 706 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 707 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 708 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const; 709 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const; 710 SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const; 711 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const; 712 713 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 714 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const; 715 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const; 716 717 virtual SDValue 718 LowerFormalArguments(SDValue Chain, 719 CallingConv::ID CallConv, bool isVarArg, 720 const SmallVectorImpl<ISD::InputArg> &Ins, 721 DebugLoc dl, SelectionDAG &DAG, 722 SmallVectorImpl<SDValue> &InVals) const; 723 virtual SDValue 724 LowerCall(SDValue Chain, SDValue Callee, 725 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, 726 const SmallVectorImpl<ISD::OutputArg> &Outs, 727 const SmallVectorImpl<ISD::InputArg> &Ins, 728 DebugLoc dl, SelectionDAG &DAG, 729 SmallVectorImpl<SDValue> &InVals) const; 730 731 virtual SDValue 732 LowerReturn(SDValue Chain, 733 CallingConv::ID CallConv, bool isVarArg, 734 const SmallVectorImpl<ISD::OutputArg> &Outs, 735 DebugLoc dl, SelectionDAG &DAG) const; 736 737 virtual bool 738 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 739 const SmallVectorImpl<EVT> &OutTys, 740 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, 741 SelectionDAG &DAG) const; 742 743 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results, 744 SelectionDAG &DAG, unsigned NewOp) const; 745 746 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 747 SDValue Chain, 748 SDValue Dst, SDValue Src, 749 SDValue Size, unsigned Align, 750 bool isVolatile, 751 const Value *DstSV, 752 uint64_t DstSVOff) const; 753 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 754 SDValue Chain, 755 SDValue Dst, SDValue Src, 756 SDValue Size, unsigned Align, 757 bool isVolatile, bool AlwaysInline, 758 const Value *DstSV, 759 uint64_t DstSVOff, 760 const Value *SrcSV, 761 uint64_t SrcSVOff) const; 762 763 /// Utility function to emit string processing sse4.2 instructions 764 /// that return in xmm0. 765 /// This takes the instruction to expand, the associated machine basic 766 /// block, the number of args, and whether or not the second arg is 767 /// in memory or not. 768 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB, 769 unsigned argNum, bool inMem) const; 770 771 /// Utility function to emit atomic bitwise operations (and, or, xor). 772 /// It takes the bitwise instruction to expand, the associated machine basic 773 /// block, and the associated X86 opcodes for reg/reg and reg/imm. 774 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter( 775 MachineInstr *BInstr, 776 MachineBasicBlock *BB, 777 unsigned regOpc, 778 unsigned immOpc, 779 unsigned loadOpc, 780 unsigned cxchgOpc, 781 unsigned copyOpc, 782 unsigned notOpc, 783 unsigned EAXreg, 784 TargetRegisterClass *RC, 785 bool invSrc = false) const; 786 787 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter( 788 MachineInstr *BInstr, 789 MachineBasicBlock *BB, 790 unsigned regOpcL, 791 unsigned regOpcH, 792 unsigned immOpcL, 793 unsigned immOpcH, 794 bool invSrc = false) const; 795 796 /// Utility function to emit atomic min and max. It takes the min/max 797 /// instruction to expand, the associated basic block, and the associated 798 /// cmov opcode for moving the min or max value. 799 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr, 800 MachineBasicBlock *BB, 801 unsigned cmovOpc) const; 802 803 /// Utility function to emit the xmm reg save portion of va_start. 804 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter( 805 MachineInstr *BInstr, 806 MachineBasicBlock *BB) const; 807 808 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I, 809 MachineBasicBlock *BB) const; 810 811 MachineBasicBlock *EmitLoweredMingwAlloca(MachineInstr *MI, 812 MachineBasicBlock *BB) const; 813 814 /// Emit nodes that will be selected as "test Op0,Op0", or something 815 /// equivalent, for use with the given x86 condition code. 816 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const; 817 818 /// Emit nodes that will be selected as "cmp Op0,Op1", or something 819 /// equivalent, for use with the given x86 condition code. 820 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 821 SelectionDAG &DAG) const; 822 }; 823 824 namespace X86 { 825 FastISel *createFastISel(MachineFunction &mf, 826 DenseMap<const Value *, unsigned> &, 827 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 828 DenseMap<const AllocaInst *, int> &, 829 std::vector<std::pair<MachineInstr*, unsigned> > & 830#ifndef NDEBUG 831 , SmallSet<const Instruction*, 8> & 832#endif 833 ); 834 } 835} 836 837#endif // X86ISELLOWERING_H 838