X86ISelLowering.h revision 198090
1//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef X86ISELLOWERING_H 16#define X86ISELLOWERING_H 17 18#include "X86Subtarget.h" 19#include "X86RegisterInfo.h" 20#include "X86MachineFunctionInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/CodeGen/FastISel.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24#include "llvm/CodeGen/CallingConvLower.h" 25 26namespace llvm { 27 namespace X86ISD { 28 // X86 Specific DAG Nodes 29 enum NodeType { 30 // Start the numbering where the builtin ops leave off. 31 FIRST_NUMBER = ISD::BUILTIN_OP_END, 32 33 /// BSF - Bit scan forward. 34 /// BSR - Bit scan reverse. 35 BSF, 36 BSR, 37 38 /// SHLD, SHRD - Double shift instructions. These correspond to 39 /// X86::SHLDxx and X86::SHRDxx instructions. 40 SHLD, 41 SHRD, 42 43 /// FAND - Bitwise logical AND of floating point values. This corresponds 44 /// to X86::ANDPS or X86::ANDPD. 45 FAND, 46 47 /// FOR - Bitwise logical OR of floating point values. This corresponds 48 /// to X86::ORPS or X86::ORPD. 49 FOR, 50 51 /// FXOR - Bitwise logical XOR of floating point values. This corresponds 52 /// to X86::XORPS or X86::XORPD. 53 FXOR, 54 55 /// FSRL - Bitwise logical right shift of floating point values. These 56 /// corresponds to X86::PSRLDQ. 57 FSRL, 58 59 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the 60 /// integer source in memory and FP reg result. This corresponds to the 61 /// X86::FILD*m instructions. It has three inputs (token chain, address, 62 /// and source type) and two outputs (FP value and token chain). FILD_FLAG 63 /// also produces a flag). 64 FILD, 65 FILD_FLAG, 66 67 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the 68 /// integer destination in memory and a FP reg source. This corresponds 69 /// to the X86::FIST*m instructions and the rounding mode change stuff. It 70 /// has two inputs (token chain and address) and two outputs (int value 71 /// and token chain). 72 FP_TO_INT16_IN_MEM, 73 FP_TO_INT32_IN_MEM, 74 FP_TO_INT64_IN_MEM, 75 76 /// FLD - This instruction implements an extending load to FP stack slots. 77 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain 78 /// operand, ptr to load from, and a ValueType node indicating the type 79 /// to load to. 80 FLD, 81 82 /// FST - This instruction implements a truncating store to FP stack 83 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a 84 /// chain operand, value to store, address, and a ValueType to store it 85 /// as. 86 FST, 87 88 /// CALL - These operations represent an abstract X86 call 89 /// instruction, which includes a bunch of information. In particular the 90 /// operands of these node are: 91 /// 92 /// #0 - The incoming token chain 93 /// #1 - The callee 94 /// #2 - The number of arg bytes the caller pushes on the stack. 95 /// #3 - The number of arg bytes the callee pops off the stack. 96 /// #4 - The value to pass in AL/AX/EAX (optional) 97 /// #5 - The value to pass in DL/DX/EDX (optional) 98 /// 99 /// The result values of these nodes are: 100 /// 101 /// #0 - The outgoing token chain 102 /// #1 - The first register result value (optional) 103 /// #2 - The second register result value (optional) 104 /// 105 CALL, 106 107 /// RDTSC_DAG - This operation implements the lowering for 108 /// readcyclecounter 109 RDTSC_DAG, 110 111 /// X86 compare and logical compare instructions. 112 CMP, COMI, UCOMI, 113 114 /// X86 bit-test instructions. 115 BT, 116 117 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the flag 118 /// operand produced by a CMP instruction. 119 SETCC, 120 121 /// X86 conditional moves. Operand 0 and operand 1 are the two values 122 /// to select from. Operand 2 is the condition code, and operand 3 is the 123 /// flag operand produced by a CMP or TEST instruction. It also writes a 124 /// flag result. 125 CMOV, 126 127 /// X86 conditional branches. Operand 0 is the chain operand, operand 1 128 /// is the block to branch if condition is true, operand 2 is the 129 /// condition code, and operand 3 is the flag operand produced by a CMP 130 /// or TEST instruction. 131 BRCOND, 132 133 /// Return with a flag operand. Operand 0 is the chain operand, operand 134 /// 1 is the number of bytes of stack to pop. 135 RET_FLAG, 136 137 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx. 138 REP_STOS, 139 140 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx. 141 REP_MOVS, 142 143 /// GlobalBaseReg - On Darwin, this node represents the result of the popl 144 /// at function entry, used for PIC code. 145 GlobalBaseReg, 146 147 /// Wrapper - A wrapper node for TargetConstantPool, 148 /// TargetExternalSymbol, and TargetGlobalAddress. 149 Wrapper, 150 151 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP 152 /// relative displacements. 153 WrapperRIP, 154 155 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to 156 /// i32, corresponds to X86::PEXTRB. 157 PEXTRB, 158 159 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to 160 /// i32, corresponds to X86::PEXTRW. 161 PEXTRW, 162 163 /// INSERTPS - Insert any element of a 4 x float vector into any element 164 /// of a destination 4 x floatvector. 165 INSERTPS, 166 167 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector, 168 /// corresponds to X86::PINSRB. 169 PINSRB, 170 171 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector, 172 /// corresponds to X86::PINSRW. 173 PINSRW, 174 175 /// PSHUFB - Shuffle 16 8-bit values within a vector. 176 PSHUFB, 177 178 /// FMAX, FMIN - Floating point max and min. 179 /// 180 FMAX, FMIN, 181 182 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal 183 /// approximation. Note that these typically require refinement 184 /// in order to obtain suitable precision. 185 FRSQRT, FRCP, 186 187 // TLSADDR - Thread Local Storage. 188 TLSADDR, 189 190 // SegmentBaseAddress - The address segment:0 191 SegmentBaseAddress, 192 193 // EH_RETURN - Exception Handling helpers. 194 EH_RETURN, 195 196 /// TC_RETURN - Tail call return. 197 /// operand #0 chain 198 /// operand #1 callee (register or absolute) 199 /// operand #2 stack adjustment 200 /// operand #3 optional in flag 201 TC_RETURN, 202 203 // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap. 204 LCMPXCHG_DAG, 205 LCMPXCHG8_DAG, 206 207 // FNSTCW16m - Store FP control world into i16 memory. 208 FNSTCW16m, 209 210 // VZEXT_MOVL - Vector move low and zero extend. 211 VZEXT_MOVL, 212 213 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend. 214 VZEXT_LOAD, 215 216 // VSHL, VSRL - Vector logical left / right shift. 217 VSHL, VSRL, 218 219 // CMPPD, CMPPS - Vector double/float comparison. 220 // CMPPD, CMPPS - Vector double/float comparison. 221 CMPPD, CMPPS, 222 223 // PCMP* - Vector integer comparisons. 224 PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ, 225 PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ, 226 227 // ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results. 228 ADD, SUB, SMUL, UMUL, 229 INC, DEC, OR, XOR, AND, 230 231 // MUL_IMM - X86 specific multiply by immediate. 232 MUL_IMM, 233 234 // PTEST - Vector bitwise comparisons 235 PTEST, 236 237 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack, 238 // according to %al. An operator is needed so that this can be expanded 239 // with control flow. 240 VASTART_SAVE_XMM_REGS, 241 242 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG, 243 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG - 244 // Atomic 64-bit binary operations. 245 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, 246 ATOMSUB64_DAG, 247 ATOMOR64_DAG, 248 ATOMXOR64_DAG, 249 ATOMAND64_DAG, 250 ATOMNAND64_DAG, 251 ATOMSWAP64_DAG 252 }; 253 } 254 255 /// Define some predicates that are used for node matching. 256 namespace X86 { 257 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand 258 /// specifies a shuffle of elements that is suitable for input to PSHUFD. 259 bool isPSHUFDMask(ShuffleVectorSDNode *N); 260 261 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand 262 /// specifies a shuffle of elements that is suitable for input to PSHUFD. 263 bool isPSHUFHWMask(ShuffleVectorSDNode *N); 264 265 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand 266 /// specifies a shuffle of elements that is suitable for input to PSHUFD. 267 bool isPSHUFLWMask(ShuffleVectorSDNode *N); 268 269 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 270 /// specifies a shuffle of elements that is suitable for input to SHUFP*. 271 bool isSHUFPMask(ShuffleVectorSDNode *N); 272 273 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 274 /// specifies a shuffle of elements that is suitable for input to MOVHLPS. 275 bool isMOVHLPSMask(ShuffleVectorSDNode *N); 276 277 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 278 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 279 /// <2, 3, 2, 3> 280 bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N); 281 282 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 283 /// specifies a shuffle of elements that is suitable for MOVLP{S|D}. 284 bool isMOVLPMask(ShuffleVectorSDNode *N); 285 286 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand 287 /// specifies a shuffle of elements that is suitable for MOVHP{S|D}. 288 /// as well as MOVLHPS. 289 bool isMOVHPMask(ShuffleVectorSDNode *N); 290 291 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 292 /// specifies a shuffle of elements that is suitable for input to UNPCKL. 293 bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false); 294 295 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 296 /// specifies a shuffle of elements that is suitable for input to UNPCKH. 297 bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false); 298 299 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 300 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 301 /// <0, 0, 1, 1> 302 bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N); 303 304 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 305 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 306 /// <2, 2, 3, 3> 307 bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N); 308 309 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 310 /// specifies a shuffle of elements that is suitable for input to MOVSS, 311 /// MOVSD, and MOVD, i.e. setting the lowest element. 312 bool isMOVLMask(ShuffleVectorSDNode *N); 313 314 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 315 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 316 bool isMOVSHDUPMask(ShuffleVectorSDNode *N); 317 318 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 319 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 320 bool isMOVSLDUPMask(ShuffleVectorSDNode *N); 321 322 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 323 /// specifies a shuffle of elements that is suitable for input to MOVDDUP. 324 bool isMOVDDUPMask(ShuffleVectorSDNode *N); 325 326 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 327 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* 328 /// instructions. 329 unsigned getShuffleSHUFImmediate(SDNode *N); 330 331 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 332 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW 333 /// instructions. 334 unsigned getShufflePSHUFHWImmediate(SDNode *N); 335 336 /// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle 337 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW 338 /// instructions. 339 unsigned getShufflePSHUFLWImmediate(SDNode *N); 340 341 /// isZeroNode - Returns true if Elt is a constant zero or a floating point 342 /// constant +0.0. 343 bool isZeroNode(SDValue Elt); 344 345 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be 346 /// fit into displacement field of the instruction. 347 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 348 bool hasSymbolicDisplacement = true); 349 } 350 351 //===--------------------------------------------------------------------===// 352 // X86TargetLowering - X86 Implementation of the TargetLowering interface 353 class X86TargetLowering : public TargetLowering { 354 int VarArgsFrameIndex; // FrameIndex for start of varargs area. 355 int RegSaveFrameIndex; // X86-64 vararg func register save area. 356 unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset. 357 unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset. 358 int BytesToPopOnReturn; // Number of arg bytes ret should pop. 359 int BytesCallerReserves; // Number of arg bytes caller makes. 360 361 public: 362 explicit X86TargetLowering(X86TargetMachine &TM); 363 364 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 365 /// jumptable. 366 SDValue getPICJumpTableRelocBase(SDValue Table, 367 SelectionDAG &DAG) const; 368 369 // Return the number of bytes that a function should pop when it returns (in 370 // addition to the space used by the return address). 371 // 372 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; } 373 374 // Return the number of bytes that the caller reserves for arguments passed 375 // to this function. 376 unsigned getBytesCallerReserves() const { return BytesCallerReserves; } 377 378 /// getStackPtrReg - Return the stack pointer register we are using: either 379 /// ESP or RSP. 380 unsigned getStackPtrReg() const { return X86StackPtr; } 381 382 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 383 /// function arguments in the caller parameter area. For X86, aggregates 384 /// that contains are placed at 16-byte boundaries while the rest are at 385 /// 4-byte boundaries. 386 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 387 388 /// getOptimalMemOpType - Returns the target specific optimal type for load 389 /// and store operations as a result of memset, memcpy, and memmove 390 /// lowering. It returns EVT::iAny if SelectionDAG should be responsible for 391 /// determining it. 392 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align, 393 bool isSrcConst, bool isSrcStr, 394 SelectionDAG &DAG) const; 395 396 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 397 /// unaligned memory accesses. of the specified type. 398 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 399 return true; 400 } 401 402 /// LowerOperation - Provide custom lowering hooks for some operations. 403 /// 404 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 405 406 /// ReplaceNodeResults - Replace the results of node with an illegal result 407 /// type with new values built out of custom code. 408 /// 409 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 410 SelectionDAG &DAG); 411 412 413 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 414 415 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 416 MachineBasicBlock *MBB, 417 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; 418 419 420 /// getTargetNodeName - This method returns the name of a target specific 421 /// DAG node. 422 virtual const char *getTargetNodeName(unsigned Opcode) const; 423 424 /// getSetCCResultType - Return the ISD::SETCC ValueType 425 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const; 426 427 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 428 /// in Mask are known to be either zero or one and return them in the 429 /// KnownZero/KnownOne bitsets. 430 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 431 const APInt &Mask, 432 APInt &KnownZero, 433 APInt &KnownOne, 434 const SelectionDAG &DAG, 435 unsigned Depth = 0) const; 436 437 virtual bool 438 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const; 439 440 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG); 441 442 virtual bool ExpandInlineAsm(CallInst *CI) const; 443 444 ConstraintType getConstraintType(const std::string &Constraint) const; 445 446 std::vector<unsigned> 447 getRegClassForInlineAsmConstraint(const std::string &Constraint, 448 EVT VT) const; 449 450 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 451 452 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 453 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 454 /// true it means one of the asm constraint of the inline asm instruction 455 /// being processed is 'm'. 456 virtual void LowerAsmOperandForConstraint(SDValue Op, 457 char ConstraintLetter, 458 bool hasMemory, 459 std::vector<SDValue> &Ops, 460 SelectionDAG &DAG) const; 461 462 /// getRegForInlineAsmConstraint - Given a physical register constraint 463 /// (e.g. {edx}), return the register number and the register class for the 464 /// register. This should only be used for C_Register constraints. On 465 /// error, this returns a register number of 0. 466 std::pair<unsigned, const TargetRegisterClass*> 467 getRegForInlineAsmConstraint(const std::string &Constraint, 468 EVT VT) const; 469 470 /// isLegalAddressingMode - Return true if the addressing mode represented 471 /// by AM is legal for this target, for a load/store of the specified type. 472 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 473 474 /// isTruncateFree - Return true if it's free to truncate a value of 475 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 476 /// register EAX to i16 by referencing its sub-register AX. 477 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const; 478 virtual bool isTruncateFree(EVT VT1, EVT VT2) const; 479 480 /// isZExtFree - Return true if any actual instruction that defines a 481 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 482 /// register. This does not necessarily include registers defined in 483 /// unknown ways, such as incoming arguments, or copies from unknown 484 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 485 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 486 /// all instructions that define 32-bit values implicit zero-extend the 487 /// result out to 64 bits. 488 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const; 489 virtual bool isZExtFree(EVT VT1, EVT VT2) const; 490 491 /// isNarrowingProfitable - Return true if it's profitable to narrow 492 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 493 /// from i32 to i8 but not from i32 to i16. 494 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const; 495 496 /// isShuffleMaskLegal - Targets can use this to indicate that they only 497 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 498 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask 499 /// values are assumed to be legal. 500 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 501 EVT VT) const; 502 503 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 504 /// used by Targets can use this to indicate if there is a suitable 505 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 506 /// pool entry. 507 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 508 EVT VT) const; 509 510 /// ShouldShrinkFPConstant - If true, then instruction selection should 511 /// seek to shrink the FP constant of the specified type to a smaller type 512 /// in order to save space and / or reduce runtime. 513 virtual bool ShouldShrinkFPConstant(EVT VT) const { 514 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more 515 // expensive than a straight movsd. On the other hand, it's important to 516 // shrink long double fp constant since fldt is very slow. 517 return !X86ScalarSSEf64 || VT == MVT::f80; 518 } 519 520 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 521 /// for tail call optimization. Targets which want to do tail call 522 /// optimization should implement this function. 523 virtual bool 524 IsEligibleForTailCallOptimization(SDValue Callee, 525 CallingConv::ID CalleeCC, 526 bool isVarArg, 527 const SmallVectorImpl<ISD::InputArg> &Ins, 528 SelectionDAG& DAG) const; 529 530 virtual const X86Subtarget* getSubtarget() { 531 return Subtarget; 532 } 533 534 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 535 /// computed in an SSE register, not on the X87 floating point stack. 536 bool isScalarFPTypeInSSEReg(EVT VT) const { 537 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 538 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 539 } 540 541 /// getWidenVectorType: given a vector type, returns the type to widen 542 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 543 /// If there is no vector type that we want to widen to, returns EVT::Other 544 /// When and were to widen is target dependent based on the cost of 545 /// scalarizing vs using the wider vector type. 546 virtual EVT getWidenVectorType(EVT VT) const; 547 548 /// createFastISel - This method returns a target specific FastISel object, 549 /// or null if the target does not support "fast" ISel. 550 virtual FastISel * 551 createFastISel(MachineFunction &mf, 552 MachineModuleInfo *mmi, DwarfWriter *dw, 553 DenseMap<const Value *, unsigned> &, 554 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 555 DenseMap<const AllocaInst *, int> & 556#ifndef NDEBUG 557 , SmallSet<Instruction*, 8> & 558#endif 559 ); 560 561 /// getFunctionAlignment - Return the Log2 alignment of this function. 562 virtual unsigned getFunctionAlignment(const Function *F) const; 563 564 private: 565 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 566 /// make the right decision when generating code for different targets. 567 const X86Subtarget *Subtarget; 568 const X86RegisterInfo *RegInfo; 569 const TargetData *TD; 570 571 /// X86StackPtr - X86 physical register used as stack ptr. 572 unsigned X86StackPtr; 573 574 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 575 /// floating point ops. 576 /// When SSE is available, use it for f32 operations. 577 /// When SSE2 is available, use it for f64 operations. 578 bool X86ScalarSSEf32; 579 bool X86ScalarSSEf64; 580 581 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 582 CallingConv::ID CallConv, bool isVarArg, 583 const SmallVectorImpl<ISD::InputArg> &Ins, 584 DebugLoc dl, SelectionDAG &DAG, 585 SmallVectorImpl<SDValue> &InVals); 586 SDValue LowerMemArgument(SDValue Chain, 587 CallingConv::ID CallConv, 588 const SmallVectorImpl<ISD::InputArg> &ArgInfo, 589 DebugLoc dl, SelectionDAG &DAG, 590 const CCValAssign &VA, MachineFrameInfo *MFI, 591 unsigned i); 592 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 593 DebugLoc dl, SelectionDAG &DAG, 594 const CCValAssign &VA, 595 ISD::ArgFlagsTy Flags); 596 597 // Call lowering helpers. 598 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv); 599 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, 600 SDValue Chain, bool IsTailCall, bool Is64Bit, 601 int FPDiff, DebugLoc dl); 602 603 CCAssignFn *CCAssignFnForNode(CallingConv::ID CallConv) const; 604 NameDecorationStyle NameDecorationForCallConv(CallingConv::ID CallConv); 605 unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG); 606 607 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, 608 bool isSigned); 609 610 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); 611 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); 612 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); 613 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG); 614 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); 615 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG); 616 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG); 617 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); 618 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 619 int64_t Offset, SelectionDAG &DAG) const; 620 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); 621 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); 622 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG); 623 SDValue LowerShift(SDValue Op, SelectionDAG &DAG); 624 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, 625 SelectionDAG &DAG); 626 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG); 627 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG); 628 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG); 629 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG); 630 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG); 631 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG); 632 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG); 633 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG); 634 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG); 635 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG); 636 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG); 637 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG); 638 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG); 639 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG); 640 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG); 641 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG); 642 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG); 643 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG); 644 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG); 645 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG); 646 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG); 647 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); 648 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG); 649 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG); 650 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG); 651 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG); 652 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG); 653 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG); 654 SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG); 655 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG); 656 657 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG); 658 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG); 659 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG); 660 661 virtual SDValue 662 LowerFormalArguments(SDValue Chain, 663 CallingConv::ID CallConv, bool isVarArg, 664 const SmallVectorImpl<ISD::InputArg> &Ins, 665 DebugLoc dl, SelectionDAG &DAG, 666 SmallVectorImpl<SDValue> &InVals); 667 virtual SDValue 668 LowerCall(SDValue Chain, SDValue Callee, 669 CallingConv::ID CallConv, bool isVarArg, bool isTailCall, 670 const SmallVectorImpl<ISD::OutputArg> &Outs, 671 const SmallVectorImpl<ISD::InputArg> &Ins, 672 DebugLoc dl, SelectionDAG &DAG, 673 SmallVectorImpl<SDValue> &InVals); 674 675 virtual SDValue 676 LowerReturn(SDValue Chain, 677 CallingConv::ID CallConv, bool isVarArg, 678 const SmallVectorImpl<ISD::OutputArg> &Outs, 679 DebugLoc dl, SelectionDAG &DAG); 680 681 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results, 682 SelectionDAG &DAG, unsigned NewOp); 683 684 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 685 SDValue Chain, 686 SDValue Dst, SDValue Src, 687 SDValue Size, unsigned Align, 688 const Value *DstSV, uint64_t DstSVOff); 689 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 690 SDValue Chain, 691 SDValue Dst, SDValue Src, 692 SDValue Size, unsigned Align, 693 bool AlwaysInline, 694 const Value *DstSV, uint64_t DstSVOff, 695 const Value *SrcSV, uint64_t SrcSVOff); 696 697 /// Utility function to emit string processing sse4.2 instructions 698 /// that return in xmm0. 699 /// This takes the instruction to expand, the associated machine basic 700 /// block, the number of args, and whether or not the second arg is 701 /// in memory or not. 702 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB, 703 unsigned argNum, bool inMem) const; 704 705 /// Utility function to emit atomic bitwise operations (and, or, xor). 706 /// It takes the bitwise instruction to expand, the associated machine basic 707 /// block, and the associated X86 opcodes for reg/reg and reg/imm. 708 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter( 709 MachineInstr *BInstr, 710 MachineBasicBlock *BB, 711 unsigned regOpc, 712 unsigned immOpc, 713 unsigned loadOpc, 714 unsigned cxchgOpc, 715 unsigned copyOpc, 716 unsigned notOpc, 717 unsigned EAXreg, 718 TargetRegisterClass *RC, 719 bool invSrc = false) const; 720 721 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter( 722 MachineInstr *BInstr, 723 MachineBasicBlock *BB, 724 unsigned regOpcL, 725 unsigned regOpcH, 726 unsigned immOpcL, 727 unsigned immOpcH, 728 bool invSrc = false) const; 729 730 /// Utility function to emit atomic min and max. It takes the min/max 731 /// instruction to expand, the associated basic block, and the associated 732 /// cmov opcode for moving the min or max value. 733 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr, 734 MachineBasicBlock *BB, 735 unsigned cmovOpc) const; 736 737 /// Utility function to emit the xmm reg save portion of va_start. 738 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter( 739 MachineInstr *BInstr, 740 MachineBasicBlock *BB) const; 741 742 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I, 743 MachineBasicBlock *BB, 744 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; 745 746 /// Emit nodes that will be selected as "test Op0,Op0", or something 747 /// equivalent, for use with the given x86 condition code. 748 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG); 749 750 /// Emit nodes that will be selected as "cmp Op0,Op1", or something 751 /// equivalent, for use with the given x86 condition code. 752 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 753 SelectionDAG &DAG); 754 }; 755 756 namespace X86 { 757 FastISel *createFastISel(MachineFunction &mf, 758 MachineModuleInfo *mmi, DwarfWriter *dw, 759 DenseMap<const Value *, unsigned> &, 760 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 761 DenseMap<const AllocaInst *, int> & 762#ifndef NDEBUG 763 , SmallSet<Instruction*, 8> & 764#endif 765 ); 766 } 767} 768 769#endif // X86ISELLOWERING_H 770