X86ISelDAGToDAG.cpp revision 193323
1//===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines a DAG pattern matching instruction selector for X86, 11// converting from a legalized dag to a X86 dag. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86MachineFunctionInfo.h" 20#include "X86RegisterInfo.h" 21#include "X86Subtarget.h" 22#include "X86TargetMachine.h" 23#include "llvm/GlobalValue.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/Support/CFG.h" 27#include "llvm/Type.h" 28#include "llvm/CodeGen/MachineConstantPool.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineFrameInfo.h" 31#include "llvm/CodeGen/MachineInstrBuilder.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/CodeGen/SelectionDAGISel.h" 34#include "llvm/Target/TargetMachine.h" 35#include "llvm/Target/TargetOptions.h" 36#include "llvm/Support/Compiler.h" 37#include "llvm/Support/Debug.h" 38#include "llvm/Support/MathExtras.h" 39#include "llvm/Support/Streams.h" 40#include "llvm/ADT/SmallPtrSet.h" 41#include "llvm/ADT/Statistic.h" 42using namespace llvm; 43 44#include "llvm/Support/CommandLine.h" 45static cl::opt<bool> AvoidDupAddrCompute("x86-avoid-dup-address", cl::Hidden); 46 47STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor"); 48 49//===----------------------------------------------------------------------===// 50// Pattern Matcher Implementation 51//===----------------------------------------------------------------------===// 52 53namespace { 54 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses 55 /// SDValue's instead of register numbers for the leaves of the matched 56 /// tree. 57 struct X86ISelAddressMode { 58 enum { 59 RegBase, 60 FrameIndexBase 61 } BaseType; 62 63 struct { // This is really a union, discriminated by BaseType! 64 SDValue Reg; 65 int FrameIndex; 66 } Base; 67 68 bool isRIPRel; // RIP as base? 69 unsigned Scale; 70 SDValue IndexReg; 71 int32_t Disp; 72 SDValue Segment; 73 GlobalValue *GV; 74 Constant *CP; 75 const char *ES; 76 int JT; 77 unsigned Align; // CP alignment. 78 79 X86ISelAddressMode() 80 : BaseType(RegBase), isRIPRel(false), Scale(1), IndexReg(), Disp(0), 81 Segment(), GV(0), CP(0), ES(0), JT(-1), Align(0) { 82 } 83 84 bool hasSymbolicDisplacement() const { 85 return GV != 0 || CP != 0 || ES != 0 || JT != -1; 86 } 87 88 void dump() { 89 cerr << "X86ISelAddressMode " << this << "\n"; 90 cerr << "Base.Reg "; 91 if (Base.Reg.getNode() != 0) Base.Reg.getNode()->dump(); 92 else cerr << "nul"; 93 cerr << " Base.FrameIndex " << Base.FrameIndex << "\n"; 94 cerr << "isRIPRel " << isRIPRel << " Scale" << Scale << "\n"; 95 cerr << "IndexReg "; 96 if (IndexReg.getNode() != 0) IndexReg.getNode()->dump(); 97 else cerr << "nul"; 98 cerr << " Disp " << Disp << "\n"; 99 cerr << "GV "; if (GV) GV->dump(); 100 else cerr << "nul"; 101 cerr << " CP "; if (CP) CP->dump(); 102 else cerr << "nul"; 103 cerr << "\n"; 104 cerr << "ES "; if (ES) cerr << ES; else cerr << "nul"; 105 cerr << " JT" << JT << " Align" << Align << "\n"; 106 } 107 }; 108} 109 110namespace { 111 //===--------------------------------------------------------------------===// 112 /// ISel - X86 specific code to select X86 machine instructions for 113 /// SelectionDAG operations. 114 /// 115 class VISIBILITY_HIDDEN X86DAGToDAGISel : public SelectionDAGISel { 116 /// TM - Keep a reference to X86TargetMachine. 117 /// 118 X86TargetMachine &TM; 119 120 /// X86Lowering - This object fully describes how to lower LLVM code to an 121 /// X86-specific SelectionDAG. 122 X86TargetLowering &X86Lowering; 123 124 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 125 /// make the right decision when generating code for different targets. 126 const X86Subtarget *Subtarget; 127 128 /// CurBB - Current BB being isel'd. 129 /// 130 MachineBasicBlock *CurBB; 131 132 /// OptForSize - If true, selector should try to optimize for code size 133 /// instead of performance. 134 bool OptForSize; 135 136 public: 137 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel) 138 : SelectionDAGISel(tm, OptLevel), 139 TM(tm), X86Lowering(*TM.getTargetLowering()), 140 Subtarget(&TM.getSubtarget<X86Subtarget>()), 141 OptForSize(false) {} 142 143 virtual const char *getPassName() const { 144 return "X86 DAG->DAG Instruction Selection"; 145 } 146 147 /// InstructionSelect - This callback is invoked by 148 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 149 virtual void InstructionSelect(); 150 151 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF); 152 153 virtual 154 bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const; 155 156// Include the pieces autogenerated from the target description. 157#include "X86GenDAGISel.inc" 158 159 private: 160 SDNode *Select(SDValue N); 161 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc); 162 163 bool MatchSegmentBaseAddress(SDValue N, X86ISelAddressMode &AM); 164 bool MatchLoad(SDValue N, X86ISelAddressMode &AM); 165 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM); 166 bool MatchAddress(SDValue N, X86ISelAddressMode &AM, 167 unsigned Depth = 0); 168 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM); 169 bool SelectAddr(SDValue Op, SDValue N, SDValue &Base, 170 SDValue &Scale, SDValue &Index, SDValue &Disp, 171 SDValue &Segment); 172 bool SelectLEAAddr(SDValue Op, SDValue N, SDValue &Base, 173 SDValue &Scale, SDValue &Index, SDValue &Disp); 174 bool SelectScalarSSELoad(SDValue Op, SDValue Pred, 175 SDValue N, SDValue &Base, SDValue &Scale, 176 SDValue &Index, SDValue &Disp, 177 SDValue &Segment, 178 SDValue &InChain, SDValue &OutChain); 179 bool TryFoldLoad(SDValue P, SDValue N, 180 SDValue &Base, SDValue &Scale, 181 SDValue &Index, SDValue &Disp, 182 SDValue &Segment); 183 void PreprocessForRMW(); 184 void PreprocessForFPConvert(); 185 186 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for 187 /// inline asm expressions. 188 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 189 char ConstraintCode, 190 std::vector<SDValue> &OutOps); 191 192 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI); 193 194 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base, 195 SDValue &Scale, SDValue &Index, 196 SDValue &Disp, SDValue &Segment) { 197 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ? 198 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) : 199 AM.Base.Reg; 200 Scale = getI8Imm(AM.Scale); 201 Index = AM.IndexReg; 202 // These are 32-bit even in 64-bit mode since RIP relative offset 203 // is 32-bit. 204 if (AM.GV) 205 Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp); 206 else if (AM.CP) 207 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32, 208 AM.Align, AM.Disp); 209 else if (AM.ES) 210 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32); 211 else if (AM.JT != -1) 212 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32); 213 else 214 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32); 215 216 if (AM.Segment.getNode()) 217 Segment = AM.Segment; 218 else 219 Segment = CurDAG->getRegister(0, MVT::i32); 220 } 221 222 /// getI8Imm - Return a target constant with the specified value, of type 223 /// i8. 224 inline SDValue getI8Imm(unsigned Imm) { 225 return CurDAG->getTargetConstant(Imm, MVT::i8); 226 } 227 228 /// getI16Imm - Return a target constant with the specified value, of type 229 /// i16. 230 inline SDValue getI16Imm(unsigned Imm) { 231 return CurDAG->getTargetConstant(Imm, MVT::i16); 232 } 233 234 /// getI32Imm - Return a target constant with the specified value, of type 235 /// i32. 236 inline SDValue getI32Imm(unsigned Imm) { 237 return CurDAG->getTargetConstant(Imm, MVT::i32); 238 } 239 240 /// getGlobalBaseReg - Return an SDNode that returns the value of 241 /// the global base register. Output instructions required to 242 /// initialize the global base register, if necessary. 243 /// 244 SDNode *getGlobalBaseReg(); 245 246#ifndef NDEBUG 247 unsigned Indent; 248#endif 249 }; 250} 251 252 253bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U, 254 SDNode *Root) const { 255 if (OptLevel == CodeGenOpt::None) return false; 256 257 if (U == Root) 258 switch (U->getOpcode()) { 259 default: break; 260 case ISD::ADD: 261 case ISD::ADDC: 262 case ISD::ADDE: 263 case ISD::AND: 264 case ISD::OR: 265 case ISD::XOR: { 266 SDValue Op1 = U->getOperand(1); 267 268 // If the other operand is a 8-bit immediate we should fold the immediate 269 // instead. This reduces code size. 270 // e.g. 271 // movl 4(%esp), %eax 272 // addl $4, %eax 273 // vs. 274 // movl $4, %eax 275 // addl 4(%esp), %eax 276 // The former is 2 bytes shorter. In case where the increment is 1, then 277 // the saving can be 4 bytes (by using incl %eax). 278 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1)) 279 if (Imm->getAPIntValue().isSignedIntN(8)) 280 return false; 281 282 // If the other operand is a TLS address, we should fold it instead. 283 // This produces 284 // movl %gs:0, %eax 285 // leal i@NTPOFF(%eax), %eax 286 // instead of 287 // movl $i@NTPOFF, %eax 288 // addl %gs:0, %eax 289 // if the block also has an access to a second TLS address this will save 290 // a load. 291 // FIXME: This is probably also true for non TLS addresses. 292 if (Op1.getOpcode() == X86ISD::Wrapper) { 293 SDValue Val = Op1.getOperand(0); 294 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress) 295 return false; 296 } 297 } 298 } 299 300 // Proceed to 'generic' cycle finder code 301 return SelectionDAGISel::IsLegalAndProfitableToFold(N, U, Root); 302} 303 304/// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand 305/// and move load below the TokenFactor. Replace store's chain operand with 306/// load's chain result. 307static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load, 308 SDValue Store, SDValue TF) { 309 SmallVector<SDValue, 4> Ops; 310 for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i) 311 if (Load.getNode() == TF.getOperand(i).getNode()) 312 Ops.push_back(Load.getOperand(0)); 313 else 314 Ops.push_back(TF.getOperand(i)); 315 CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size()); 316 CurDAG->UpdateNodeOperands(Load, TF, Load.getOperand(1), Load.getOperand(2)); 317 CurDAG->UpdateNodeOperands(Store, Load.getValue(1), Store.getOperand(1), 318 Store.getOperand(2), Store.getOperand(3)); 319} 320 321/// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG. 322/// 323static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address, 324 SDValue &Load) { 325 if (N.getOpcode() == ISD::BIT_CONVERT) 326 N = N.getOperand(0); 327 328 LoadSDNode *LD = dyn_cast<LoadSDNode>(N); 329 if (!LD || LD->isVolatile()) 330 return false; 331 if (LD->getAddressingMode() != ISD::UNINDEXED) 332 return false; 333 334 ISD::LoadExtType ExtType = LD->getExtensionType(); 335 if (ExtType != ISD::NON_EXTLOAD && ExtType != ISD::EXTLOAD) 336 return false; 337 338 if (N.hasOneUse() && 339 N.getOperand(1) == Address && 340 N.getNode()->isOperandOf(Chain.getNode())) { 341 Load = N; 342 return true; 343 } 344 return false; 345} 346 347/// MoveBelowCallSeqStart - Replace CALLSEQ_START operand with load's chain 348/// operand and move load below the call's chain operand. 349static void MoveBelowCallSeqStart(SelectionDAG *CurDAG, SDValue Load, 350 SDValue Call, SDValue CallSeqStart) { 351 SmallVector<SDValue, 8> Ops; 352 SDValue Chain = CallSeqStart.getOperand(0); 353 if (Chain.getNode() == Load.getNode()) 354 Ops.push_back(Load.getOperand(0)); 355 else { 356 assert(Chain.getOpcode() == ISD::TokenFactor && 357 "Unexpected CallSeqStart chain operand"); 358 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) 359 if (Chain.getOperand(i).getNode() == Load.getNode()) 360 Ops.push_back(Load.getOperand(0)); 361 else 362 Ops.push_back(Chain.getOperand(i)); 363 SDValue NewChain = 364 CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(), 365 MVT::Other, &Ops[0], Ops.size()); 366 Ops.clear(); 367 Ops.push_back(NewChain); 368 } 369 for (unsigned i = 1, e = CallSeqStart.getNumOperands(); i != e; ++i) 370 Ops.push_back(CallSeqStart.getOperand(i)); 371 CurDAG->UpdateNodeOperands(CallSeqStart, &Ops[0], Ops.size()); 372 CurDAG->UpdateNodeOperands(Load, Call.getOperand(0), 373 Load.getOperand(1), Load.getOperand(2)); 374 Ops.clear(); 375 Ops.push_back(SDValue(Load.getNode(), 1)); 376 for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i) 377 Ops.push_back(Call.getOperand(i)); 378 CurDAG->UpdateNodeOperands(Call, &Ops[0], Ops.size()); 379} 380 381/// isCalleeLoad - Return true if call address is a load and it can be 382/// moved below CALLSEQ_START and the chains leading up to the call. 383/// Return the CALLSEQ_START by reference as a second output. 384static bool isCalleeLoad(SDValue Callee, SDValue &Chain) { 385 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse()) 386 return false; 387 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode()); 388 if (!LD || 389 LD->isVolatile() || 390 LD->getAddressingMode() != ISD::UNINDEXED || 391 LD->getExtensionType() != ISD::NON_EXTLOAD) 392 return false; 393 394 // Now let's find the callseq_start. 395 while (Chain.getOpcode() != ISD::CALLSEQ_START) { 396 if (!Chain.hasOneUse()) 397 return false; 398 Chain = Chain.getOperand(0); 399 } 400 401 if (Chain.getOperand(0).getNode() == Callee.getNode()) 402 return true; 403 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor && 404 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode())) 405 return true; 406 return false; 407} 408 409 410/// PreprocessForRMW - Preprocess the DAG to make instruction selection better. 411/// This is only run if not in -O0 mode. 412/// This allows the instruction selector to pick more read-modify-write 413/// instructions. This is a common case: 414/// 415/// [Load chain] 416/// ^ 417/// | 418/// [Load] 419/// ^ ^ 420/// | | 421/// / \- 422/// / | 423/// [TokenFactor] [Op] 424/// ^ ^ 425/// | | 426/// \ / 427/// \ / 428/// [Store] 429/// 430/// The fact the store's chain operand != load's chain will prevent the 431/// (store (op (load))) instruction from being selected. We can transform it to: 432/// 433/// [Load chain] 434/// ^ 435/// | 436/// [TokenFactor] 437/// ^ 438/// | 439/// [Load] 440/// ^ ^ 441/// | | 442/// | \- 443/// | | 444/// | [Op] 445/// | ^ 446/// | | 447/// \ / 448/// \ / 449/// [Store] 450void X86DAGToDAGISel::PreprocessForRMW() { 451 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 452 E = CurDAG->allnodes_end(); I != E; ++I) { 453 if (I->getOpcode() == X86ISD::CALL) { 454 /// Also try moving call address load from outside callseq_start to just 455 /// before the call to allow it to be folded. 456 /// 457 /// [Load chain] 458 /// ^ 459 /// | 460 /// [Load] 461 /// ^ ^ 462 /// | | 463 /// / \-- 464 /// / | 465 ///[CALLSEQ_START] | 466 /// ^ | 467 /// | | 468 /// [LOAD/C2Reg] | 469 /// | | 470 /// \ / 471 /// \ / 472 /// [CALL] 473 SDValue Chain = I->getOperand(0); 474 SDValue Load = I->getOperand(1); 475 if (!isCalleeLoad(Load, Chain)) 476 continue; 477 MoveBelowCallSeqStart(CurDAG, Load, SDValue(I, 0), Chain); 478 ++NumLoadMoved; 479 continue; 480 } 481 482 if (!ISD::isNON_TRUNCStore(I)) 483 continue; 484 SDValue Chain = I->getOperand(0); 485 486 if (Chain.getNode()->getOpcode() != ISD::TokenFactor) 487 continue; 488 489 SDValue N1 = I->getOperand(1); 490 SDValue N2 = I->getOperand(2); 491 if ((N1.getValueType().isFloatingPoint() && 492 !N1.getValueType().isVector()) || 493 !N1.hasOneUse()) 494 continue; 495 496 bool RModW = false; 497 SDValue Load; 498 unsigned Opcode = N1.getNode()->getOpcode(); 499 switch (Opcode) { 500 case ISD::ADD: 501 case ISD::MUL: 502 case ISD::AND: 503 case ISD::OR: 504 case ISD::XOR: 505 case ISD::ADDC: 506 case ISD::ADDE: 507 case ISD::VECTOR_SHUFFLE: { 508 SDValue N10 = N1.getOperand(0); 509 SDValue N11 = N1.getOperand(1); 510 RModW = isRMWLoad(N10, Chain, N2, Load); 511 if (!RModW) 512 RModW = isRMWLoad(N11, Chain, N2, Load); 513 break; 514 } 515 case ISD::SUB: 516 case ISD::SHL: 517 case ISD::SRA: 518 case ISD::SRL: 519 case ISD::ROTL: 520 case ISD::ROTR: 521 case ISD::SUBC: 522 case ISD::SUBE: 523 case X86ISD::SHLD: 524 case X86ISD::SHRD: { 525 SDValue N10 = N1.getOperand(0); 526 RModW = isRMWLoad(N10, Chain, N2, Load); 527 break; 528 } 529 } 530 531 if (RModW) { 532 MoveBelowTokenFactor(CurDAG, Load, SDValue(I, 0), Chain); 533 ++NumLoadMoved; 534 } 535 } 536} 537 538 539/// PreprocessForFPConvert - Walk over the dag lowering fpround and fpextend 540/// nodes that target the FP stack to be store and load to the stack. This is a 541/// gross hack. We would like to simply mark these as being illegal, but when 542/// we do that, legalize produces these when it expands calls, then expands 543/// these in the same legalize pass. We would like dag combine to be able to 544/// hack on these between the call expansion and the node legalization. As such 545/// this pass basically does "really late" legalization of these inline with the 546/// X86 isel pass. 547void X86DAGToDAGISel::PreprocessForFPConvert() { 548 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 549 E = CurDAG->allnodes_end(); I != E; ) { 550 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues. 551 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND) 552 continue; 553 554 // If the source and destination are SSE registers, then this is a legal 555 // conversion that should not be lowered. 556 MVT SrcVT = N->getOperand(0).getValueType(); 557 MVT DstVT = N->getValueType(0); 558 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT); 559 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT); 560 if (SrcIsSSE && DstIsSSE) 561 continue; 562 563 if (!SrcIsSSE && !DstIsSSE) { 564 // If this is an FPStack extension, it is a noop. 565 if (N->getOpcode() == ISD::FP_EXTEND) 566 continue; 567 // If this is a value-preserving FPStack truncation, it is a noop. 568 if (N->getConstantOperandVal(1)) 569 continue; 570 } 571 572 // Here we could have an FP stack truncation or an FPStack <-> SSE convert. 573 // FPStack has extload and truncstore. SSE can fold direct loads into other 574 // operations. Based on this, decide what we want to do. 575 MVT MemVT; 576 if (N->getOpcode() == ISD::FP_ROUND) 577 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'. 578 else 579 MemVT = SrcIsSSE ? SrcVT : DstVT; 580 581 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT); 582 DebugLoc dl = N->getDebugLoc(); 583 584 // FIXME: optimize the case where the src/dest is a load or store? 585 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl, 586 N->getOperand(0), 587 MemTmp, NULL, 0, MemVT); 588 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp, 589 NULL, 0, MemVT); 590 591 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the 592 // extload we created. This will cause general havok on the dag because 593 // anything below the conversion could be folded into other existing nodes. 594 // To avoid invalidating 'I', back it up to the convert node. 595 --I; 596 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); 597 598 // Now that we did that, the node is dead. Increment the iterator to the 599 // next node to process, then delete N. 600 ++I; 601 CurDAG->DeleteNode(N); 602 } 603} 604 605/// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel 606/// when it has created a SelectionDAG for us to codegen. 607void X86DAGToDAGISel::InstructionSelect() { 608 CurBB = BB; // BB can change as result of isel. 609 const Function *F = CurDAG->getMachineFunction().getFunction(); 610 OptForSize = F->hasFnAttr(Attribute::OptimizeForSize); 611 612 DEBUG(BB->dump()); 613 if (OptLevel != CodeGenOpt::None) 614 PreprocessForRMW(); 615 616 // FIXME: This should only happen when not compiled with -O0. 617 PreprocessForFPConvert(); 618 619 // Codegen the basic block. 620#ifndef NDEBUG 621 DOUT << "===== Instruction selection begins:\n"; 622 Indent = 0; 623#endif 624 SelectRoot(*CurDAG); 625#ifndef NDEBUG 626 DOUT << "===== Instruction selection ends:\n"; 627#endif 628 629 CurDAG->RemoveDeadNodes(); 630} 631 632/// EmitSpecialCodeForMain - Emit any code that needs to be executed only in 633/// the main function. 634void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB, 635 MachineFrameInfo *MFI) { 636 const TargetInstrInfo *TII = TM.getInstrInfo(); 637 if (Subtarget->isTargetCygMing()) 638 BuildMI(BB, DebugLoc::getUnknownLoc(), 639 TII->get(X86::CALLpcrel32)).addExternalSymbol("__main"); 640} 641 642void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) { 643 // If this is main, emit special code for main. 644 MachineBasicBlock *BB = MF.begin(); 645 if (Fn.hasExternalLinkage() && Fn.getName() == "main") 646 EmitSpecialCodeForMain(BB, MF.getFrameInfo()); 647} 648 649 650bool X86DAGToDAGISel::MatchSegmentBaseAddress(SDValue N, 651 X86ISelAddressMode &AM) { 652 assert(N.getOpcode() == X86ISD::SegmentBaseAddress); 653 SDValue Segment = N.getOperand(0); 654 655 if (AM.Segment.getNode() == 0) { 656 AM.Segment = Segment; 657 return false; 658 } 659 660 return true; 661} 662 663bool X86DAGToDAGISel::MatchLoad(SDValue N, X86ISelAddressMode &AM) { 664 // This optimization is valid because the GNU TLS model defines that 665 // gs:0 (or fs:0 on X86-64) contains its own address. 666 // For more information see http://people.redhat.com/drepper/tls.pdf 667 668 SDValue Address = N.getOperand(1); 669 if (Address.getOpcode() == X86ISD::SegmentBaseAddress && 670 !MatchSegmentBaseAddress (Address, AM)) 671 return false; 672 673 return true; 674} 675 676bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) { 677 bool is64Bit = Subtarget->is64Bit(); 678 DOUT << "Wrapper: 64bit " << is64Bit; 679 DOUT << " AM "; DEBUG(AM.dump()); DOUT << "\n"; 680 681 // Under X86-64 non-small code model, GV (and friends) are 64-bits. 682 if (is64Bit && (TM.getCodeModel() != CodeModel::Small)) 683 return true; 684 685 // Base and index reg must be 0 in order to use rip as base. 686 bool canUsePICRel = !AM.Base.Reg.getNode() && !AM.IndexReg.getNode(); 687 if (is64Bit && !canUsePICRel && TM.symbolicAddressesAreRIPRel()) 688 return true; 689 690 if (AM.hasSymbolicDisplacement()) 691 return true; 692 // If value is available in a register both base and index components have 693 // been picked, we can't fit the result available in the register in the 694 // addressing mode. Duplicate GlobalAddress or ConstantPool as displacement. 695 696 SDValue N0 = N.getOperand(0); 697 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) { 698 uint64_t Offset = G->getOffset(); 699 if (!is64Bit || isInt32(AM.Disp + Offset)) { 700 GlobalValue *GV = G->getGlobal(); 701 bool isRIPRel = TM.symbolicAddressesAreRIPRel(); 702 if (N0.getOpcode() == llvm::ISD::TargetGlobalTLSAddress) { 703 TLSModel::Model model = 704 getTLSModel (GV, TM.getRelocationModel()); 705 if (is64Bit && model == TLSModel::InitialExec) 706 isRIPRel = true; 707 } 708 AM.GV = GV; 709 AM.Disp += Offset; 710 AM.isRIPRel = isRIPRel; 711 return false; 712 } 713 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) { 714 uint64_t Offset = CP->getOffset(); 715 if (!is64Bit || isInt32(AM.Disp + Offset)) { 716 AM.CP = CP->getConstVal(); 717 AM.Align = CP->getAlignment(); 718 AM.Disp += Offset; 719 AM.isRIPRel = TM.symbolicAddressesAreRIPRel(); 720 return false; 721 } 722 } else if (ExternalSymbolSDNode *S =dyn_cast<ExternalSymbolSDNode>(N0)) { 723 AM.ES = S->getSymbol(); 724 AM.isRIPRel = TM.symbolicAddressesAreRIPRel(); 725 return false; 726 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) { 727 AM.JT = J->getIndex(); 728 AM.isRIPRel = TM.symbolicAddressesAreRIPRel(); 729 return false; 730 } 731 732 return true; 733} 734 735/// MatchAddress - Add the specified node to the specified addressing mode, 736/// returning true if it cannot be done. This just pattern matches for the 737/// addressing mode. 738bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM, 739 unsigned Depth) { 740 bool is64Bit = Subtarget->is64Bit(); 741 DebugLoc dl = N.getDebugLoc(); 742 DOUT << "MatchAddress: "; DEBUG(AM.dump()); 743 // Limit recursion. 744 if (Depth > 5) 745 return MatchAddressBase(N, AM); 746 747 // RIP relative addressing: %rip + 32-bit displacement! 748 if (AM.isRIPRel) { 749 if (!AM.ES && AM.JT != -1 && N.getOpcode() == ISD::Constant) { 750 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue(); 751 if (!is64Bit || isInt32(AM.Disp + Val)) { 752 AM.Disp += Val; 753 return false; 754 } 755 } 756 return true; 757 } 758 759 switch (N.getOpcode()) { 760 default: break; 761 case ISD::Constant: { 762 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue(); 763 if (!is64Bit || isInt32(AM.Disp + Val)) { 764 AM.Disp += Val; 765 return false; 766 } 767 break; 768 } 769 770 case X86ISD::SegmentBaseAddress: 771 if (!MatchSegmentBaseAddress(N, AM)) 772 return false; 773 break; 774 775 case X86ISD::Wrapper: 776 if (!MatchWrapper(N, AM)) 777 return false; 778 break; 779 780 case ISD::LOAD: 781 if (!MatchLoad(N, AM)) 782 return false; 783 break; 784 785 case ISD::FrameIndex: 786 if (AM.BaseType == X86ISelAddressMode::RegBase 787 && AM.Base.Reg.getNode() == 0) { 788 AM.BaseType = X86ISelAddressMode::FrameIndexBase; 789 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex(); 790 return false; 791 } 792 break; 793 794 case ISD::SHL: 795 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1 || AM.isRIPRel) 796 break; 797 798 if (ConstantSDNode 799 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) { 800 unsigned Val = CN->getZExtValue(); 801 if (Val == 1 || Val == 2 || Val == 3) { 802 AM.Scale = 1 << Val; 803 SDValue ShVal = N.getNode()->getOperand(0); 804 805 // Okay, we know that we have a scale by now. However, if the scaled 806 // value is an add of something and a constant, we can fold the 807 // constant into the disp field here. 808 if (ShVal.getNode()->getOpcode() == ISD::ADD && ShVal.hasOneUse() && 809 isa<ConstantSDNode>(ShVal.getNode()->getOperand(1))) { 810 AM.IndexReg = ShVal.getNode()->getOperand(0); 811 ConstantSDNode *AddVal = 812 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1)); 813 uint64_t Disp = AM.Disp + (AddVal->getSExtValue() << Val); 814 if (!is64Bit || isInt32(Disp)) 815 AM.Disp = Disp; 816 else 817 AM.IndexReg = ShVal; 818 } else { 819 AM.IndexReg = ShVal; 820 } 821 return false; 822 } 823 break; 824 } 825 826 case ISD::SMUL_LOHI: 827 case ISD::UMUL_LOHI: 828 // A mul_lohi where we need the low part can be folded as a plain multiply. 829 if (N.getResNo() != 0) break; 830 // FALL THROUGH 831 case ISD::MUL: 832 case X86ISD::MUL_IMM: 833 // X*[3,5,9] -> X+X*[2,4,8] 834 if (AM.BaseType == X86ISelAddressMode::RegBase && 835 AM.Base.Reg.getNode() == 0 && 836 AM.IndexReg.getNode() == 0 && 837 !AM.isRIPRel) { 838 if (ConstantSDNode 839 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) 840 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 || 841 CN->getZExtValue() == 9) { 842 AM.Scale = unsigned(CN->getZExtValue())-1; 843 844 SDValue MulVal = N.getNode()->getOperand(0); 845 SDValue Reg; 846 847 // Okay, we know that we have a scale by now. However, if the scaled 848 // value is an add of something and a constant, we can fold the 849 // constant into the disp field here. 850 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() && 851 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) { 852 Reg = MulVal.getNode()->getOperand(0); 853 ConstantSDNode *AddVal = 854 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1)); 855 uint64_t Disp = AM.Disp + AddVal->getSExtValue() * 856 CN->getZExtValue(); 857 if (!is64Bit || isInt32(Disp)) 858 AM.Disp = Disp; 859 else 860 Reg = N.getNode()->getOperand(0); 861 } else { 862 Reg = N.getNode()->getOperand(0); 863 } 864 865 AM.IndexReg = AM.Base.Reg = Reg; 866 return false; 867 } 868 } 869 break; 870 871 case ISD::SUB: { 872 // Given A-B, if A can be completely folded into the address and 873 // the index field with the index field unused, use -B as the index. 874 // This is a win if a has multiple parts that can be folded into 875 // the address. Also, this saves a mov if the base register has 876 // other uses, since it avoids a two-address sub instruction, however 877 // it costs an additional mov if the index register has other uses. 878 879 // Test if the LHS of the sub can be folded. 880 X86ISelAddressMode Backup = AM; 881 if (MatchAddress(N.getNode()->getOperand(0), AM, Depth+1)) { 882 AM = Backup; 883 break; 884 } 885 // Test if the index field is free for use. 886 if (AM.IndexReg.getNode() || AM.isRIPRel) { 887 AM = Backup; 888 break; 889 } 890 int Cost = 0; 891 SDValue RHS = N.getNode()->getOperand(1); 892 // If the RHS involves a register with multiple uses, this 893 // transformation incurs an extra mov, due to the neg instruction 894 // clobbering its operand. 895 if (!RHS.getNode()->hasOneUse() || 896 RHS.getNode()->getOpcode() == ISD::CopyFromReg || 897 RHS.getNode()->getOpcode() == ISD::TRUNCATE || 898 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND || 899 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND && 900 RHS.getNode()->getOperand(0).getValueType() == MVT::i32)) 901 ++Cost; 902 // If the base is a register with multiple uses, this 903 // transformation may save a mov. 904 if ((AM.BaseType == X86ISelAddressMode::RegBase && 905 AM.Base.Reg.getNode() && 906 !AM.Base.Reg.getNode()->hasOneUse()) || 907 AM.BaseType == X86ISelAddressMode::FrameIndexBase) 908 --Cost; 909 // If the folded LHS was interesting, this transformation saves 910 // address arithmetic. 911 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) + 912 ((AM.Disp != 0) && (Backup.Disp == 0)) + 913 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2) 914 --Cost; 915 // If it doesn't look like it may be an overall win, don't do it. 916 if (Cost >= 0) { 917 AM = Backup; 918 break; 919 } 920 921 // Ok, the transformation is legal and appears profitable. Go for it. 922 SDValue Zero = CurDAG->getConstant(0, N.getValueType()); 923 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS); 924 AM.IndexReg = Neg; 925 AM.Scale = 1; 926 927 // Insert the new nodes into the topological ordering. 928 if (Zero.getNode()->getNodeId() == -1 || 929 Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) { 930 CurDAG->RepositionNode(N.getNode(), Zero.getNode()); 931 Zero.getNode()->setNodeId(N.getNode()->getNodeId()); 932 } 933 if (Neg.getNode()->getNodeId() == -1 || 934 Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) { 935 CurDAG->RepositionNode(N.getNode(), Neg.getNode()); 936 Neg.getNode()->setNodeId(N.getNode()->getNodeId()); 937 } 938 return false; 939 } 940 941 case ISD::ADD: { 942 X86ISelAddressMode Backup = AM; 943 if (!MatchAddress(N.getNode()->getOperand(0), AM, Depth+1) && 944 !MatchAddress(N.getNode()->getOperand(1), AM, Depth+1)) 945 return false; 946 AM = Backup; 947 if (!MatchAddress(N.getNode()->getOperand(1), AM, Depth+1) && 948 !MatchAddress(N.getNode()->getOperand(0), AM, Depth+1)) 949 return false; 950 AM = Backup; 951 952 // If we couldn't fold both operands into the address at the same time, 953 // see if we can just put each operand into a register and fold at least 954 // the add. 955 if (AM.BaseType == X86ISelAddressMode::RegBase && 956 !AM.Base.Reg.getNode() && 957 !AM.IndexReg.getNode() && 958 !AM.isRIPRel) { 959 AM.Base.Reg = N.getNode()->getOperand(0); 960 AM.IndexReg = N.getNode()->getOperand(1); 961 AM.Scale = 1; 962 return false; 963 } 964 break; 965 } 966 967 case ISD::OR: 968 // Handle "X | C" as "X + C" iff X is known to have C bits clear. 969 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 970 X86ISelAddressMode Backup = AM; 971 uint64_t Offset = CN->getSExtValue(); 972 // Start with the LHS as an addr mode. 973 if (!MatchAddress(N.getOperand(0), AM, Depth+1) && 974 // Address could not have picked a GV address for the displacement. 975 AM.GV == NULL && 976 // On x86-64, the resultant disp must fit in 32-bits. 977 (!is64Bit || isInt32(AM.Disp + Offset)) && 978 // Check to see if the LHS & C is zero. 979 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) { 980 AM.Disp += Offset; 981 return false; 982 } 983 AM = Backup; 984 } 985 break; 986 987 case ISD::AND: { 988 // Perform some heroic transforms on an and of a constant-count shift 989 // with a constant to enable use of the scaled offset field. 990 991 SDValue Shift = N.getOperand(0); 992 if (Shift.getNumOperands() != 2) break; 993 994 // Scale must not be used already. 995 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break; 996 997 // Not when RIP is used as the base. 998 if (AM.isRIPRel) break; 999 1000 SDValue X = Shift.getOperand(0); 1001 ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N.getOperand(1)); 1002 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Shift.getOperand(1)); 1003 if (!C1 || !C2) break; 1004 1005 // Handle "(X >> (8-C1)) & C2" as "(X >> 8) & 0xff)" if safe. This 1006 // allows us to convert the shift and and into an h-register extract and 1007 // a scaled index. 1008 if (Shift.getOpcode() == ISD::SRL && Shift.hasOneUse()) { 1009 unsigned ScaleLog = 8 - C1->getZExtValue(); 1010 if (ScaleLog > 0 && ScaleLog < 4 && 1011 C2->getZExtValue() == (UINT64_C(0xff) << ScaleLog)) { 1012 SDValue Eight = CurDAG->getConstant(8, MVT::i8); 1013 SDValue Mask = CurDAG->getConstant(0xff, N.getValueType()); 1014 SDValue Srl = CurDAG->getNode(ISD::SRL, dl, N.getValueType(), 1015 X, Eight); 1016 SDValue And = CurDAG->getNode(ISD::AND, dl, N.getValueType(), 1017 Srl, Mask); 1018 SDValue ShlCount = CurDAG->getConstant(ScaleLog, MVT::i8); 1019 SDValue Shl = CurDAG->getNode(ISD::SHL, dl, N.getValueType(), 1020 And, ShlCount); 1021 1022 // Insert the new nodes into the topological ordering. 1023 if (Eight.getNode()->getNodeId() == -1 || 1024 Eight.getNode()->getNodeId() > X.getNode()->getNodeId()) { 1025 CurDAG->RepositionNode(X.getNode(), Eight.getNode()); 1026 Eight.getNode()->setNodeId(X.getNode()->getNodeId()); 1027 } 1028 if (Mask.getNode()->getNodeId() == -1 || 1029 Mask.getNode()->getNodeId() > X.getNode()->getNodeId()) { 1030 CurDAG->RepositionNode(X.getNode(), Mask.getNode()); 1031 Mask.getNode()->setNodeId(X.getNode()->getNodeId()); 1032 } 1033 if (Srl.getNode()->getNodeId() == -1 || 1034 Srl.getNode()->getNodeId() > Shift.getNode()->getNodeId()) { 1035 CurDAG->RepositionNode(Shift.getNode(), Srl.getNode()); 1036 Srl.getNode()->setNodeId(Shift.getNode()->getNodeId()); 1037 } 1038 if (And.getNode()->getNodeId() == -1 || 1039 And.getNode()->getNodeId() > N.getNode()->getNodeId()) { 1040 CurDAG->RepositionNode(N.getNode(), And.getNode()); 1041 And.getNode()->setNodeId(N.getNode()->getNodeId()); 1042 } 1043 if (ShlCount.getNode()->getNodeId() == -1 || 1044 ShlCount.getNode()->getNodeId() > X.getNode()->getNodeId()) { 1045 CurDAG->RepositionNode(X.getNode(), ShlCount.getNode()); 1046 ShlCount.getNode()->setNodeId(N.getNode()->getNodeId()); 1047 } 1048 if (Shl.getNode()->getNodeId() == -1 || 1049 Shl.getNode()->getNodeId() > N.getNode()->getNodeId()) { 1050 CurDAG->RepositionNode(N.getNode(), Shl.getNode()); 1051 Shl.getNode()->setNodeId(N.getNode()->getNodeId()); 1052 } 1053 CurDAG->ReplaceAllUsesWith(N, Shl); 1054 AM.IndexReg = And; 1055 AM.Scale = (1 << ScaleLog); 1056 return false; 1057 } 1058 } 1059 1060 // Handle "(X << C1) & C2" as "(X & (C2>>C1)) << C1" if safe and if this 1061 // allows us to fold the shift into this addressing mode. 1062 if (Shift.getOpcode() != ISD::SHL) break; 1063 1064 // Not likely to be profitable if either the AND or SHIFT node has more 1065 // than one use (unless all uses are for address computation). Besides, 1066 // isel mechanism requires their node ids to be reused. 1067 if (!N.hasOneUse() || !Shift.hasOneUse()) 1068 break; 1069 1070 // Verify that the shift amount is something we can fold. 1071 unsigned ShiftCst = C1->getZExtValue(); 1072 if (ShiftCst != 1 && ShiftCst != 2 && ShiftCst != 3) 1073 break; 1074 1075 // Get the new AND mask, this folds to a constant. 1076 SDValue NewANDMask = CurDAG->getNode(ISD::SRL, dl, N.getValueType(), 1077 SDValue(C2, 0), SDValue(C1, 0)); 1078 SDValue NewAND = CurDAG->getNode(ISD::AND, dl, N.getValueType(), X, 1079 NewANDMask); 1080 SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, dl, N.getValueType(), 1081 NewAND, SDValue(C1, 0)); 1082 1083 // Insert the new nodes into the topological ordering. 1084 if (C1->getNodeId() > X.getNode()->getNodeId()) { 1085 CurDAG->RepositionNode(X.getNode(), C1); 1086 C1->setNodeId(X.getNode()->getNodeId()); 1087 } 1088 if (NewANDMask.getNode()->getNodeId() == -1 || 1089 NewANDMask.getNode()->getNodeId() > X.getNode()->getNodeId()) { 1090 CurDAG->RepositionNode(X.getNode(), NewANDMask.getNode()); 1091 NewANDMask.getNode()->setNodeId(X.getNode()->getNodeId()); 1092 } 1093 if (NewAND.getNode()->getNodeId() == -1 || 1094 NewAND.getNode()->getNodeId() > Shift.getNode()->getNodeId()) { 1095 CurDAG->RepositionNode(Shift.getNode(), NewAND.getNode()); 1096 NewAND.getNode()->setNodeId(Shift.getNode()->getNodeId()); 1097 } 1098 if (NewSHIFT.getNode()->getNodeId() == -1 || 1099 NewSHIFT.getNode()->getNodeId() > N.getNode()->getNodeId()) { 1100 CurDAG->RepositionNode(N.getNode(), NewSHIFT.getNode()); 1101 NewSHIFT.getNode()->setNodeId(N.getNode()->getNodeId()); 1102 } 1103 1104 CurDAG->ReplaceAllUsesWith(N, NewSHIFT); 1105 1106 AM.Scale = 1 << ShiftCst; 1107 AM.IndexReg = NewAND; 1108 return false; 1109 } 1110 } 1111 1112 return MatchAddressBase(N, AM); 1113} 1114 1115/// MatchAddressBase - Helper for MatchAddress. Add the specified node to the 1116/// specified addressing mode without any further recursion. 1117bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) { 1118 // Is the base register already occupied? 1119 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.getNode()) { 1120 // If so, check to see if the scale index register is set. 1121 if (AM.IndexReg.getNode() == 0 && !AM.isRIPRel) { 1122 AM.IndexReg = N; 1123 AM.Scale = 1; 1124 return false; 1125 } 1126 1127 // Otherwise, we cannot select it. 1128 return true; 1129 } 1130 1131 // Default, generate it as a register. 1132 AM.BaseType = X86ISelAddressMode::RegBase; 1133 AM.Base.Reg = N; 1134 return false; 1135} 1136 1137/// SelectAddr - returns true if it is able pattern match an addressing mode. 1138/// It returns the operands which make up the maximal addressing mode it can 1139/// match by reference. 1140bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base, 1141 SDValue &Scale, SDValue &Index, 1142 SDValue &Disp, SDValue &Segment) { 1143 X86ISelAddressMode AM; 1144 bool Done = false; 1145 if (AvoidDupAddrCompute && !N.hasOneUse()) { 1146 unsigned Opcode = N.getOpcode(); 1147 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex && 1148 Opcode != X86ISD::Wrapper) { 1149 // If we are able to fold N into addressing mode, then we'll allow it even 1150 // if N has multiple uses. In general, addressing computation is used as 1151 // addresses by all of its uses. But watch out for CopyToReg uses, that 1152 // means the address computation is liveout. It will be computed by a LEA 1153 // so we want to avoid computing the address twice. 1154 for (SDNode::use_iterator UI = N.getNode()->use_begin(), 1155 UE = N.getNode()->use_end(); UI != UE; ++UI) { 1156 if (UI->getOpcode() == ISD::CopyToReg) { 1157 MatchAddressBase(N, AM); 1158 Done = true; 1159 break; 1160 } 1161 } 1162 } 1163 } 1164 1165 if (!Done && MatchAddress(N, AM)) 1166 return false; 1167 1168 MVT VT = N.getValueType(); 1169 if (AM.BaseType == X86ISelAddressMode::RegBase) { 1170 if (!AM.Base.Reg.getNode()) 1171 AM.Base.Reg = CurDAG->getRegister(0, VT); 1172 } 1173 1174 if (!AM.IndexReg.getNode()) 1175 AM.IndexReg = CurDAG->getRegister(0, VT); 1176 1177 getAddressOperands(AM, Base, Scale, Index, Disp, Segment); 1178 return true; 1179} 1180 1181/// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to 1182/// match a load whose top elements are either undef or zeros. The load flavor 1183/// is derived from the type of N, which is either v4f32 or v2f64. 1184bool X86DAGToDAGISel::SelectScalarSSELoad(SDValue Op, SDValue Pred, 1185 SDValue N, SDValue &Base, 1186 SDValue &Scale, SDValue &Index, 1187 SDValue &Disp, SDValue &Segment, 1188 SDValue &InChain, 1189 SDValue &OutChain) { 1190 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) { 1191 InChain = N.getOperand(0).getValue(1); 1192 if (ISD::isNON_EXTLoad(InChain.getNode()) && 1193 InChain.getValue(0).hasOneUse() && 1194 N.hasOneUse() && 1195 IsLegalAndProfitableToFold(N.getNode(), Pred.getNode(), Op.getNode())) { 1196 LoadSDNode *LD = cast<LoadSDNode>(InChain); 1197 if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment)) 1198 return false; 1199 OutChain = LD->getChain(); 1200 return true; 1201 } 1202 } 1203 1204 // Also handle the case where we explicitly require zeros in the top 1205 // elements. This is a vector shuffle from the zero vector. 1206 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() && 1207 // Check to see if the top elements are all zeros (or bitcast of zeros). 1208 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR && 1209 N.getOperand(0).getNode()->hasOneUse() && 1210 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) && 1211 N.getOperand(0).getOperand(0).hasOneUse()) { 1212 // Okay, this is a zero extending load. Fold it. 1213 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0)); 1214 if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment)) 1215 return false; 1216 OutChain = LD->getChain(); 1217 InChain = SDValue(LD, 1); 1218 return true; 1219 } 1220 return false; 1221} 1222 1223 1224/// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing 1225/// mode it matches can be cost effectively emitted as an LEA instruction. 1226bool X86DAGToDAGISel::SelectLEAAddr(SDValue Op, SDValue N, 1227 SDValue &Base, SDValue &Scale, 1228 SDValue &Index, SDValue &Disp) { 1229 X86ISelAddressMode AM; 1230 1231 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support 1232 // segments. 1233 SDValue Copy = AM.Segment; 1234 SDValue T = CurDAG->getRegister(0, MVT::i32); 1235 AM.Segment = T; 1236 if (MatchAddress(N, AM)) 1237 return false; 1238 assert (T == AM.Segment); 1239 AM.Segment = Copy; 1240 1241 MVT VT = N.getValueType(); 1242 unsigned Complexity = 0; 1243 if (AM.BaseType == X86ISelAddressMode::RegBase) 1244 if (AM.Base.Reg.getNode()) 1245 Complexity = 1; 1246 else 1247 AM.Base.Reg = CurDAG->getRegister(0, VT); 1248 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase) 1249 Complexity = 4; 1250 1251 if (AM.IndexReg.getNode()) 1252 Complexity++; 1253 else 1254 AM.IndexReg = CurDAG->getRegister(0, VT); 1255 1256 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with 1257 // a simple shift. 1258 if (AM.Scale > 1) 1259 Complexity++; 1260 1261 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA 1262 // to a LEA. This is determined with some expermentation but is by no means 1263 // optimal (especially for code size consideration). LEA is nice because of 1264 // its three-address nature. Tweak the cost function again when we can run 1265 // convertToThreeAddress() at register allocation time. 1266 if (AM.hasSymbolicDisplacement()) { 1267 // For X86-64, we should always use lea to materialize RIP relative 1268 // addresses. 1269 if (Subtarget->is64Bit()) 1270 Complexity = 4; 1271 else 1272 Complexity += 2; 1273 } 1274 1275 if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode())) 1276 Complexity++; 1277 1278 if (Complexity > 2) { 1279 SDValue Segment; 1280 getAddressOperands(AM, Base, Scale, Index, Disp, Segment); 1281 return true; 1282 } 1283 return false; 1284} 1285 1286bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N, 1287 SDValue &Base, SDValue &Scale, 1288 SDValue &Index, SDValue &Disp, 1289 SDValue &Segment) { 1290 if (ISD::isNON_EXTLoad(N.getNode()) && 1291 N.hasOneUse() && 1292 IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode())) 1293 return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp, Segment); 1294 return false; 1295} 1296 1297/// getGlobalBaseReg - Return an SDNode that returns the value of 1298/// the global base register. Output instructions required to 1299/// initialize the global base register, if necessary. 1300/// 1301SDNode *X86DAGToDAGISel::getGlobalBaseReg() { 1302 MachineFunction *MF = CurBB->getParent(); 1303 unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF); 1304 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode(); 1305} 1306 1307static SDNode *FindCallStartFromCall(SDNode *Node) { 1308 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 1309 assert(Node->getOperand(0).getValueType() == MVT::Other && 1310 "Node doesn't have a token chain argument!"); 1311 return FindCallStartFromCall(Node->getOperand(0).getNode()); 1312} 1313 1314SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) { 1315 SDValue Chain = Node->getOperand(0); 1316 SDValue In1 = Node->getOperand(1); 1317 SDValue In2L = Node->getOperand(2); 1318 SDValue In2H = Node->getOperand(3); 1319 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 1320 if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) 1321 return NULL; 1322 SDValue LSI = Node->getOperand(4); // MemOperand 1323 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, LSI, Chain}; 1324 return CurDAG->getTargetNode(Opc, Node->getDebugLoc(), 1325 MVT::i32, MVT::i32, MVT::Other, Ops, 1326 array_lengthof(Ops)); 1327} 1328 1329SDNode *X86DAGToDAGISel::Select(SDValue N) { 1330 SDNode *Node = N.getNode(); 1331 MVT NVT = Node->getValueType(0); 1332 unsigned Opc, MOpc; 1333 unsigned Opcode = Node->getOpcode(); 1334 DebugLoc dl = Node->getDebugLoc(); 1335 1336#ifndef NDEBUG 1337 DOUT << std::string(Indent, ' ') << "Selecting: "; 1338 DEBUG(Node->dump(CurDAG)); 1339 DOUT << "\n"; 1340 Indent += 2; 1341#endif 1342 1343 if (Node->isMachineOpcode()) { 1344#ifndef NDEBUG 1345 DOUT << std::string(Indent-2, ' ') << "== "; 1346 DEBUG(Node->dump(CurDAG)); 1347 DOUT << "\n"; 1348 Indent -= 2; 1349#endif 1350 return NULL; // Already selected. 1351 } 1352 1353 switch (Opcode) { 1354 default: break; 1355 case X86ISD::GlobalBaseReg: 1356 return getGlobalBaseReg(); 1357 1358 case X86ISD::ATOMOR64_DAG: 1359 return SelectAtomic64(Node, X86::ATOMOR6432); 1360 case X86ISD::ATOMXOR64_DAG: 1361 return SelectAtomic64(Node, X86::ATOMXOR6432); 1362 case X86ISD::ATOMADD64_DAG: 1363 return SelectAtomic64(Node, X86::ATOMADD6432); 1364 case X86ISD::ATOMSUB64_DAG: 1365 return SelectAtomic64(Node, X86::ATOMSUB6432); 1366 case X86ISD::ATOMNAND64_DAG: 1367 return SelectAtomic64(Node, X86::ATOMNAND6432); 1368 case X86ISD::ATOMAND64_DAG: 1369 return SelectAtomic64(Node, X86::ATOMAND6432); 1370 case X86ISD::ATOMSWAP64_DAG: 1371 return SelectAtomic64(Node, X86::ATOMSWAP6432); 1372 1373 case ISD::SMUL_LOHI: 1374 case ISD::UMUL_LOHI: { 1375 SDValue N0 = Node->getOperand(0); 1376 SDValue N1 = Node->getOperand(1); 1377 1378 bool isSigned = Opcode == ISD::SMUL_LOHI; 1379 if (!isSigned) 1380 switch (NVT.getSimpleVT()) { 1381 default: assert(0 && "Unsupported VT!"); 1382 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break; 1383 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break; 1384 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break; 1385 case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break; 1386 } 1387 else 1388 switch (NVT.getSimpleVT()) { 1389 default: assert(0 && "Unsupported VT!"); 1390 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break; 1391 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break; 1392 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break; 1393 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break; 1394 } 1395 1396 unsigned LoReg, HiReg; 1397 switch (NVT.getSimpleVT()) { 1398 default: assert(0 && "Unsupported VT!"); 1399 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break; 1400 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break; 1401 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break; 1402 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break; 1403 } 1404 1405 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 1406 bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); 1407 // multiplty is commmutative 1408 if (!foldedLoad) { 1409 foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); 1410 if (foldedLoad) 1411 std::swap(N0, N1); 1412 } 1413 1414 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, 1415 N0, SDValue()).getValue(1); 1416 1417 if (foldedLoad) { 1418 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), 1419 InFlag }; 1420 SDNode *CNode = 1421 CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops, 1422 array_lengthof(Ops)); 1423 InFlag = SDValue(CNode, 1); 1424 // Update the chain. 1425 ReplaceUses(N1.getValue(1), SDValue(CNode, 0)); 1426 } else { 1427 InFlag = 1428 SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0); 1429 } 1430 1431 // Copy the low half of the result, if it is needed. 1432 if (!N.getValue(0).use_empty()) { 1433 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 1434 LoReg, NVT, InFlag); 1435 InFlag = Result.getValue(2); 1436 ReplaceUses(N.getValue(0), Result); 1437#ifndef NDEBUG 1438 DOUT << std::string(Indent-2, ' ') << "=> "; 1439 DEBUG(Result.getNode()->dump(CurDAG)); 1440 DOUT << "\n"; 1441#endif 1442 } 1443 // Copy the high half of the result, if it is needed. 1444 if (!N.getValue(1).use_empty()) { 1445 SDValue Result; 1446 if (HiReg == X86::AH && Subtarget->is64Bit()) { 1447 // Prevent use of AH in a REX instruction by referencing AX instead. 1448 // Shift it down 8 bits. 1449 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 1450 X86::AX, MVT::i16, InFlag); 1451 InFlag = Result.getValue(2); 1452 Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16, 1453 Result, 1454 CurDAG->getTargetConstant(8, MVT::i8)), 0); 1455 // Then truncate it down to i8. 1456 SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, MVT::i32); 1457 Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl, 1458 MVT::i8, Result, SRIdx), 0); 1459 } else { 1460 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 1461 HiReg, NVT, InFlag); 1462 InFlag = Result.getValue(2); 1463 } 1464 ReplaceUses(N.getValue(1), Result); 1465#ifndef NDEBUG 1466 DOUT << std::string(Indent-2, ' ') << "=> "; 1467 DEBUG(Result.getNode()->dump(CurDAG)); 1468 DOUT << "\n"; 1469#endif 1470 } 1471 1472#ifndef NDEBUG 1473 Indent -= 2; 1474#endif 1475 1476 return NULL; 1477 } 1478 1479 case ISD::SDIVREM: 1480 case ISD::UDIVREM: { 1481 SDValue N0 = Node->getOperand(0); 1482 SDValue N1 = Node->getOperand(1); 1483 1484 bool isSigned = Opcode == ISD::SDIVREM; 1485 if (!isSigned) 1486 switch (NVT.getSimpleVT()) { 1487 default: assert(0 && "Unsupported VT!"); 1488 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break; 1489 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break; 1490 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break; 1491 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break; 1492 } 1493 else 1494 switch (NVT.getSimpleVT()) { 1495 default: assert(0 && "Unsupported VT!"); 1496 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break; 1497 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break; 1498 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break; 1499 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break; 1500 } 1501 1502 unsigned LoReg, HiReg; 1503 unsigned ClrOpcode, SExtOpcode; 1504 switch (NVT.getSimpleVT()) { 1505 default: assert(0 && "Unsupported VT!"); 1506 case MVT::i8: 1507 LoReg = X86::AL; HiReg = X86::AH; 1508 ClrOpcode = 0; 1509 SExtOpcode = X86::CBW; 1510 break; 1511 case MVT::i16: 1512 LoReg = X86::AX; HiReg = X86::DX; 1513 ClrOpcode = X86::MOV16r0; 1514 SExtOpcode = X86::CWD; 1515 break; 1516 case MVT::i32: 1517 LoReg = X86::EAX; HiReg = X86::EDX; 1518 ClrOpcode = X86::MOV32r0; 1519 SExtOpcode = X86::CDQ; 1520 break; 1521 case MVT::i64: 1522 LoReg = X86::RAX; HiReg = X86::RDX; 1523 ClrOpcode = X86::MOV64r0; 1524 SExtOpcode = X86::CQO; 1525 break; 1526 } 1527 1528 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 1529 bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); 1530 bool signBitIsZero = CurDAG->SignBitIsZero(N0); 1531 1532 SDValue InFlag; 1533 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) { 1534 // Special case for div8, just use a move with zero extension to AX to 1535 // clear the upper 8 bits (AH). 1536 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain; 1537 if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { 1538 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) }; 1539 Move = 1540 SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, MVT::i16, 1541 MVT::Other, Ops, 1542 array_lengthof(Ops)), 0); 1543 Chain = Move.getValue(1); 1544 ReplaceUses(N0.getValue(1), Chain); 1545 } else { 1546 Move = 1547 SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0); 1548 Chain = CurDAG->getEntryNode(); 1549 } 1550 Chain = CurDAG->getCopyToReg(Chain, dl, X86::AX, Move, SDValue()); 1551 InFlag = Chain.getValue(1); 1552 } else { 1553 InFlag = 1554 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, 1555 LoReg, N0, SDValue()).getValue(1); 1556 if (isSigned && !signBitIsZero) { 1557 // Sign extend the low part into the high part. 1558 InFlag = 1559 SDValue(CurDAG->getTargetNode(SExtOpcode, dl, MVT::Flag, InFlag),0); 1560 } else { 1561 // Zero out the high part, effectively zero extending the input. 1562 SDValue ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, dl, NVT), 1563 0); 1564 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, HiReg, 1565 ClrNode, InFlag).getValue(1); 1566 } 1567 } 1568 1569 if (foldedLoad) { 1570 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), 1571 InFlag }; 1572 SDNode *CNode = 1573 CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops, 1574 array_lengthof(Ops)); 1575 InFlag = SDValue(CNode, 1); 1576 // Update the chain. 1577 ReplaceUses(N1.getValue(1), SDValue(CNode, 0)); 1578 } else { 1579 InFlag = 1580 SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0); 1581 } 1582 1583 // Copy the division (low) result, if it is needed. 1584 if (!N.getValue(0).use_empty()) { 1585 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 1586 LoReg, NVT, InFlag); 1587 InFlag = Result.getValue(2); 1588 ReplaceUses(N.getValue(0), Result); 1589#ifndef NDEBUG 1590 DOUT << std::string(Indent-2, ' ') << "=> "; 1591 DEBUG(Result.getNode()->dump(CurDAG)); 1592 DOUT << "\n"; 1593#endif 1594 } 1595 // Copy the remainder (high) result, if it is needed. 1596 if (!N.getValue(1).use_empty()) { 1597 SDValue Result; 1598 if (HiReg == X86::AH && Subtarget->is64Bit()) { 1599 // Prevent use of AH in a REX instruction by referencing AX instead. 1600 // Shift it down 8 bits. 1601 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 1602 X86::AX, MVT::i16, InFlag); 1603 InFlag = Result.getValue(2); 1604 Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16, 1605 Result, 1606 CurDAG->getTargetConstant(8, MVT::i8)), 1607 0); 1608 // Then truncate it down to i8. 1609 SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, MVT::i32); 1610 Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl, 1611 MVT::i8, Result, SRIdx), 0); 1612 } else { 1613 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 1614 HiReg, NVT, InFlag); 1615 InFlag = Result.getValue(2); 1616 } 1617 ReplaceUses(N.getValue(1), Result); 1618#ifndef NDEBUG 1619 DOUT << std::string(Indent-2, ' ') << "=> "; 1620 DEBUG(Result.getNode()->dump(CurDAG)); 1621 DOUT << "\n"; 1622#endif 1623 } 1624 1625#ifndef NDEBUG 1626 Indent -= 2; 1627#endif 1628 1629 return NULL; 1630 } 1631 1632 case ISD::DECLARE: { 1633 // Handle DECLARE nodes here because the second operand may have been 1634 // wrapped in X86ISD::Wrapper. 1635 SDValue Chain = Node->getOperand(0); 1636 SDValue N1 = Node->getOperand(1); 1637 SDValue N2 = Node->getOperand(2); 1638 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1); 1639 1640 // FIXME: We need to handle this for VLAs. 1641 if (!FINode) { 1642 ReplaceUses(N.getValue(0), Chain); 1643 return NULL; 1644 } 1645 1646 if (N2.getOpcode() == ISD::ADD && 1647 N2.getOperand(0).getOpcode() == X86ISD::GlobalBaseReg) 1648 N2 = N2.getOperand(1); 1649 1650 // If N2 is not Wrapper(decriptor) then the llvm.declare is mangled 1651 // somehow, just ignore it. 1652 if (N2.getOpcode() != X86ISD::Wrapper) { 1653 ReplaceUses(N.getValue(0), Chain); 1654 return NULL; 1655 } 1656 GlobalAddressSDNode *GVNode = 1657 dyn_cast<GlobalAddressSDNode>(N2.getOperand(0)); 1658 if (GVNode == 0) { 1659 ReplaceUses(N.getValue(0), Chain); 1660 return NULL; 1661 } 1662 SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(), 1663 TLI.getPointerTy()); 1664 SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GVNode->getGlobal(), 1665 TLI.getPointerTy()); 1666 SDValue Ops[] = { Tmp1, Tmp2, Chain }; 1667 return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl, 1668 MVT::Other, Ops, 1669 array_lengthof(Ops)); 1670 } 1671 } 1672 1673 SDNode *ResNode = SelectCode(N); 1674 1675#ifndef NDEBUG 1676 DOUT << std::string(Indent-2, ' ') << "=> "; 1677 if (ResNode == NULL || ResNode == N.getNode()) 1678 DEBUG(N.getNode()->dump(CurDAG)); 1679 else 1680 DEBUG(ResNode->dump(CurDAG)); 1681 DOUT << "\n"; 1682 Indent -= 2; 1683#endif 1684 1685 return ResNode; 1686} 1687 1688bool X86DAGToDAGISel:: 1689SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, 1690 std::vector<SDValue> &OutOps) { 1691 SDValue Op0, Op1, Op2, Op3, Op4; 1692 switch (ConstraintCode) { 1693 case 'o': // offsetable ?? 1694 case 'v': // not offsetable ?? 1695 default: return true; 1696 case 'm': // memory 1697 if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3, Op4)) 1698 return true; 1699 break; 1700 } 1701 1702 OutOps.push_back(Op0); 1703 OutOps.push_back(Op1); 1704 OutOps.push_back(Op2); 1705 OutOps.push_back(Op3); 1706 OutOps.push_back(Op4); 1707 return false; 1708} 1709 1710/// createX86ISelDag - This pass converts a legalized DAG into a 1711/// X86-specific DAG, ready for instruction scheduling. 1712/// 1713FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, 1714 llvm::CodeGenOpt::Level OptLevel) { 1715 return new X86DAGToDAGISel(TM, OptLevel); 1716} 1717