1251607Sdim//===-- SystemZPatterns.td - SystemZ-specific pattern rules ---*- tblgen-*-===// 2251607Sdim// 3251607Sdim// The LLVM Compiler Infrastructure 4251607Sdim// 5251607Sdim// This file is distributed under the University of Illinois Open Source 6251607Sdim// License. See LICENSE.TXT for details. 7251607Sdim// 8251607Sdim//===----------------------------------------------------------------------===// 9251607Sdim 10251607Sdim// Record that INSN performs a 64-bit version of unary operator OPERATOR 11251607Sdim// in which the operand is sign-extended from 32 to 64 bits. 12251607Sdimmulticlass SXU<SDPatternOperator operator, Instruction insn> { 13251607Sdim def : Pat<(operator (sext (i32 GR32:$src))), 14251607Sdim (insn GR32:$src)>; 15251607Sdim def : Pat<(operator (sext_inreg GR64:$src, i32)), 16261991Sdim (insn (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 17251607Sdim} 18251607Sdim 19251607Sdim// Record that INSN performs a 64-bit version of binary operator OPERATOR 20251607Sdim// in which the first operand has class CLS and which the second operand 21251607Sdim// is sign-extended from a 32-bit register. 22251607Sdimmulticlass SXB<SDPatternOperator operator, RegisterOperand cls, 23251607Sdim Instruction insn> { 24251607Sdim def : Pat<(operator cls:$src1, (sext GR32:$src2)), 25251607Sdim (insn cls:$src1, GR32:$src2)>; 26251607Sdim def : Pat<(operator cls:$src1, (sext_inreg GR64:$src2, i32)), 27261991Sdim (insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_l32))>; 28251607Sdim} 29251607Sdim 30251607Sdim// Like SXB, but for zero extension. 31251607Sdimmulticlass ZXB<SDPatternOperator operator, RegisterOperand cls, 32251607Sdim Instruction insn> { 33251607Sdim def : Pat<(operator cls:$src1, (zext GR32:$src2)), 34251607Sdim (insn cls:$src1, GR32:$src2)>; 35251607Sdim def : Pat<(operator cls:$src1, (and GR64:$src2, 0xffffffff)), 36261991Sdim (insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_l32))>; 37251607Sdim} 38251607Sdim 39251607Sdim// Record that INSN performs a binary read-modify-write operation, 40251607Sdim// with LOAD, OPERATOR and STORE being the read, modify and write 41251607Sdim// respectively. MODE is the addressing mode and IMM is the type 42251607Sdim// of the second operand. 43251607Sdimclass RMWI<SDPatternOperator load, SDPatternOperator operator, 44251607Sdim SDPatternOperator store, AddressingMode mode, 45251607Sdim PatFrag imm, Instruction insn> 46251607Sdim : Pat<(store (operator (load mode:$addr), imm:$src), mode:$addr), 47251607Sdim (insn mode:$addr, (UIMM8 imm:$src))>; 48251607Sdim 49251607Sdim// Record that INSN performs binary operation OPERATION on a byte 50251607Sdim// memory location. IMM is the type of the second operand. 51251607Sdimmulticlass RMWIByte<SDPatternOperator operator, AddressingMode mode, 52251607Sdim Instruction insn> { 53261991Sdim def : RMWI<anyextloadi8, operator, truncstorei8, mode, imm32, insn>; 54261991Sdim def : RMWI<anyextloadi8, operator, truncstorei8, mode, imm64, insn>; 55251607Sdim} 56251607Sdim 57251607Sdim// Record that INSN performs insertion TYPE into a register of class CLS. 58251607Sdim// The inserted operand is loaded using LOAD from an address of mode MODE. 59251607Sdimmulticlass InsertMem<string type, Instruction insn, RegisterOperand cls, 60251607Sdim SDPatternOperator load, AddressingMode mode> { 61251607Sdim def : Pat<(!cast<SDPatternOperator>("or_as_"##type) 62251607Sdim cls:$src1, (load mode:$src2)), 63251607Sdim (insn cls:$src1, mode:$src2)>; 64251607Sdim def : Pat<(!cast<SDPatternOperator>("or_as_rev"##type) 65251607Sdim (load mode:$src2), cls:$src1), 66251607Sdim (insn cls:$src1, mode:$src2)>; 67251607Sdim} 68261991Sdim 69261991Sdim// INSN stores the low 32 bits of a GPR to a memory with addressing mode MODE. 70261991Sdim// Record that it is equivalent to using OPERATOR to store a GR64. 71261991Sdimclass StoreGR64<Instruction insn, SDPatternOperator operator, 72261991Sdim AddressingMode mode> 73261991Sdim : Pat<(operator GR64:$R1, mode:$XBD2), 74261991Sdim (insn (EXTRACT_SUBREG GR64:$R1, subreg_l32), mode:$XBD2)>; 75261991Sdim 76261991Sdim// INSN and INSNY are an RX/RXY pair of instructions that store the low 77261991Sdim// 32 bits of a GPR to memory. Record that they are equivalent to using 78261991Sdim// OPERATOR to store a GR64. 79261991Sdimmulticlass StoreGR64Pair<Instruction insn, Instruction insny, 80261991Sdim SDPatternOperator operator> { 81261991Sdim def : StoreGR64<insn, operator, bdxaddr12pair>; 82261991Sdim def : StoreGR64<insny, operator, bdxaddr20pair>; 83261991Sdim} 84261991Sdim 85261991Sdim// INSN stores the low 32 bits of a GPR using PC-relative addressing. 86261991Sdim// Record that it is equivalent to using OPERATOR to store a GR64. 87261991Sdimclass StoreGR64PC<Instruction insn, SDPatternOperator operator> 88261991Sdim : Pat<(operator GR64:$R1, pcrel32:$XBD2), 89261991Sdim (insn (EXTRACT_SUBREG GR64:$R1, subreg_l32), pcrel32:$XBD2)> { 90261991Sdim // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 91261991Sdim // However, BDXs have two extra operands and are therefore 6 units more 92261991Sdim // complex. 93261991Sdim let AddedComplexity = 7; 94261991Sdim} 95261991Sdim 96261991Sdim// INSN and INSNINV conditionally store the low 32 bits of a GPR to memory, 97261991Sdim// with INSN storing when the condition is true and INSNINV storing when the 98261991Sdim// condition is false. Record that they are equivalent to a LOAD/select/STORE 99261991Sdim// sequence for GR64s. 100261991Sdimmulticlass CondStores64<Instruction insn, Instruction insninv, 101261991Sdim SDPatternOperator store, SDPatternOperator load, 102261991Sdim AddressingMode mode> { 103261991Sdim def : Pat<(store (z_select_ccmask GR64:$new, (load mode:$addr), 104276479Sdim imm32zx4:$valid, imm32zx4:$cc), 105261991Sdim mode:$addr), 106261991Sdim (insn (EXTRACT_SUBREG GR64:$new, subreg_l32), mode:$addr, 107276479Sdim imm32zx4:$valid, imm32zx4:$cc)>; 108261991Sdim def : Pat<(store (z_select_ccmask (load mode:$addr), GR64:$new, 109276479Sdim imm32zx4:$valid, imm32zx4:$cc), 110261991Sdim mode:$addr), 111261991Sdim (insninv (EXTRACT_SUBREG GR64:$new, subreg_l32), mode:$addr, 112276479Sdim imm32zx4:$valid, imm32zx4:$cc)>; 113261991Sdim} 114261991Sdim 115261991Sdim// Try to use MVC instruction INSN for a load of type LOAD followed by a store 116261991Sdim// of the same size. VT is the type of the intermediate (legalized) value and 117261991Sdim// LENGTH is the number of bytes loaded by LOAD. 118261991Sdimmulticlass MVCLoadStore<SDPatternOperator load, ValueType vt, Instruction insn, 119261991Sdim bits<5> length> { 120261991Sdim def : Pat<(mvc_store (vt (load bdaddr12only:$src)), bdaddr12only:$dest), 121261991Sdim (insn bdaddr12only:$dest, bdaddr12only:$src, length)>; 122261991Sdim} 123261991Sdim 124261991Sdim// Use NC-like instruction INSN for block_op operation OPERATOR. 125261991Sdim// The other operand is a load of type LOAD, which accesses LENGTH bytes. 126261991Sdim// VT is the intermediate legalized type in which the binary operation 127261991Sdim// is actually done. 128261991Sdimmulticlass BinaryLoadStore<SDPatternOperator operator, SDPatternOperator load, 129261991Sdim ValueType vt, Instruction insn, bits<5> length> { 130261991Sdim def : Pat<(operator (vt (load bdaddr12only:$src)), bdaddr12only:$dest), 131261991Sdim (insn bdaddr12only:$dest, bdaddr12only:$src, length)>; 132261991Sdim} 133261991Sdim 134261991Sdim// A convenient way of generating all block peepholes for a particular 135261991Sdim// LOAD/VT/LENGTH combination. 136261991Sdimmulticlass BlockLoadStore<SDPatternOperator load, ValueType vt, 137261991Sdim Instruction mvc, Instruction nc, Instruction oc, 138261991Sdim Instruction xc, bits<5> length> { 139261991Sdim defm : MVCLoadStore<load, vt, mvc, length>; 140261991Sdim defm : BinaryLoadStore<block_and1, load, vt, nc, length>; 141261991Sdim defm : BinaryLoadStore<block_and2, load, vt, nc, length>; 142261991Sdim defm : BinaryLoadStore<block_or1, load, vt, oc, length>; 143261991Sdim defm : BinaryLoadStore<block_or2, load, vt, oc, length>; 144261991Sdim defm : BinaryLoadStore<block_xor1, load, vt, xc, length>; 145261991Sdim defm : BinaryLoadStore<block_xor2, load, vt, xc, length>; 146261991Sdim} 147261991Sdim 148261991Sdim// Record that INSN is a LOAD AND TEST that can be used to compare 149261991Sdim// registers in CLS against zero. The instruction has separate R1 and R2 150261991Sdim// operands, but they must be the same when the instruction is used like this. 151276479Sdimmulticlass CompareZeroFP<Instruction insn, RegisterOperand cls> { 152276479Sdim def : Pat<(z_fcmp cls:$reg, (fpimm0)), (insn cls:$reg, cls:$reg)>; 153276479Sdim // The sign of the zero makes no difference. 154276479Sdim def : Pat<(z_fcmp cls:$reg, (fpimmneg0)), (insn cls:$reg, cls:$reg)>; 155276479Sdim} 156288943Sdim 157288943Sdim// Use INSN for performing binary operation OPERATION of type VT 158288943Sdim// on registers of class CLS. 159288943Sdimclass BinaryRRWithType<Instruction insn, RegisterOperand cls, 160288943Sdim SDPatternOperator operator, ValueType vt> 161288943Sdim : Pat<(vt (operator cls:$x, cls:$y)), (insn cls:$x, cls:$y)>; 162288943Sdim 163288943Sdim// Use INSN to perform conversion operation OPERATOR, with the input being 164288943Sdim// TR2 and the output being TR1. SUPPRESS is 4 to suppress inexact conditions 165288943Sdim// and 0 to allow them. MODE is the rounding mode to use. 166288943Sdimclass FPConversion<Instruction insn, SDPatternOperator operator, TypedReg tr1, 167288943Sdim TypedReg tr2, bits<3> suppress, bits<4> mode> 168288943Sdim : Pat<(tr1.vt (operator (tr2.vt tr2.op:$vec))), 169288943Sdim (insn tr2.op:$vec, suppress, mode)>; 170