SystemZISelLowering.h revision 296417
11556Srgrimes//===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===// 21556Srgrimes// 31556Srgrimes// The LLVM Compiler Infrastructure 41556Srgrimes// 51556Srgrimes// This file is distributed under the University of Illinois Open Source 61556Srgrimes// License. See LICENSE.TXT for details. 71556Srgrimes// 81556Srgrimes//===----------------------------------------------------------------------===// 91556Srgrimes// 101556Srgrimes// This file defines the interfaces that SystemZ uses to lower LLVM code into a 111556Srgrimes// selection DAG. 121556Srgrimes// 131556Srgrimes//===----------------------------------------------------------------------===// 141556Srgrimes 151556Srgrimes#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H 161556Srgrimes#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H 171556Srgrimes 181556Srgrimes#include "SystemZ.h" 191556Srgrimes#include "llvm/CodeGen/MachineBasicBlock.h" 201556Srgrimes#include "llvm/CodeGen/SelectionDAG.h" 211556Srgrimes#include "llvm/Target/TargetLowering.h" 221556Srgrimes 231556Srgrimesnamespace llvm { 241556Srgrimesnamespace SystemZISD { 251556Srgrimesenum NodeType : unsigned { 261556Srgrimes FIRST_NUMBER = ISD::BUILTIN_OP_END, 271556Srgrimes 281556Srgrimes // Return with a flag operand. Operand 0 is the chain operand. 291556Srgrimes RET_FLAG, 301556Srgrimes 311556Srgrimes // Calls a function. Operand 0 is the chain operand and operand 1 321556Srgrimes // is the target address. The arguments start at operand 2. 331556Srgrimes // There is an optional glue operand at the end. 341556Srgrimes CALL, 3535773Scharnier SIBCALL, 3636007Scharnier 3735773Scharnier // TLS calls. Like regular calls, except operand 1 is the TLS symbol. 381556Srgrimes // (The call target is implicitly __tls_get_offset.) 3999109Sobrien TLS_GDCALL, 4099109Sobrien TLS_LDCALL, 411556Srgrimes 421556Srgrimes // Wraps a TargetGlobalAddress that should be loaded using PC-relative 431556Srgrimes // accesses (LARL). Operand 0 is the address. 441556Srgrimes PCREL_WRAPPER, 451556Srgrimes 46111629Smarkm // Used in cases where an offset is applied to a TargetGlobalAddress. 471556Srgrimes // Operand 0 is the full TargetGlobalAddress and operand 1 is a 48250469Seadler // PCREL_WRAPPER for an anchor point. This is used so that we can 491556Srgrimes // cheaply refer to either the full address or the anchor point 501556Srgrimes // as a register base. 511556Srgrimes PCREL_OFFSET, 521556Srgrimes 531556Srgrimes // Integer absolute. 541556Srgrimes IABS, 5590108Simp 5690108Simp // Integer comparisons. There are three operands: the two values 5790108Simp // to compare, and an integer of type SystemZICMP. 5890108Simp ICMP, 5990108Simp 6090108Simp // Floating-point comparisons. The two operands are the values to compare. 6190108Simp FCMP, 62133762Srwatson 6390108Simp // Test under mask. The first operand is ANDed with the second operand 6490108Simp // and the condition codes are set on the result. The third operand is 6590108Simp // a boolean that is true if the condition codes need to distinguish 6690108Simp // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the 6790108Simp // register forms do but the memory forms don't). 6890108Simp TM, 69264059Sdelphij 70111629Smarkm // Branches if a condition is true. Operand 0 is the chain operand; 7190108Simp // operand 1 is the 4-bit condition-code mask, with bit N in 721556Srgrimes // big-endian order meaning "branch if CC=N"; operand 2 is the 7351208Sgreen // target block and operand 3 is the flag operand. 7454245Sgreen BR_CCMASK, 7590108Simp 761556Srgrimes // Selects between operand 0 and operand 1. Operand 2 is the 771556Srgrimes // mask of condition-code values for which operand 0 should be 781556Srgrimes // chosen over operand 1; it has the same form as BR_CCMASK. 791556Srgrimes // Operand 3 is the flag operand. 801556Srgrimes SELECT_CCMASK, 811556Srgrimes 821556Srgrimes // Evaluates to the gap between the stack pointer and the 83133762Srwatson // base of the dynamically-allocatable area. 841556Srgrimes ADJDYNALLOC, 851556Srgrimes 8657523Sgreen // Extracts the value of a 32-bit access register. Operand 0 is 871556Srgrimes // the number of the register. 881556Srgrimes EXTRACT_ACCESS, 8957523Sgreen 901556Srgrimes // Count number of bits set in operand 0 per byte. 911556Srgrimes POPCNT, 92264059Sdelphij 931556Srgrimes // Wrappers around the ISD opcodes of the same name. The output and 941556Srgrimes // first input operands are GR128s. The trailing numbers are the 951556Srgrimes // widths of the second operand in bits. 961556Srgrimes UMUL_LOHI64, 971556Srgrimes SDIVREM32, 981556Srgrimes SDIVREM64, 991556Srgrimes UDIVREM32, 1001556Srgrimes UDIVREM64, 10190108Simp 1021556Srgrimes // Use a series of MVCs to copy bytes from one memory location to another. 1031556Srgrimes // The operands are: 1041556Srgrimes // - the target address 1051556Srgrimes // - the source address 1061556Srgrimes // - the constant length 1071556Srgrimes // 10819720Sphk // This isn't a memory opcode because we'd need to attach two 10930230Seivind // MachineMemOperands rather than one. 11048051Sgreen MVC, 1111556Srgrimes 1121556Srgrimes // Like MVC, but implemented as a loop that handles X*256 bytes 1131556Srgrimes // followed by straight-line code to handle the rest (if any). 1141556Srgrimes // The value of X is passed as an additional operand. 1151556Srgrimes MVC_LOOP, 1161556Srgrimes 11748051Sgreen // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR). 11848051Sgreen NC, 11948051Sgreen NC_LOOP, 1201556Srgrimes OC, 1211556Srgrimes OC_LOOP, 12248051Sgreen XC, 12348051Sgreen XC_LOOP, 1241556Srgrimes 1251556Srgrimes // Use CLC to compare two blocks of memory, with the same comments 1261556Srgrimes // as for MVC and MVC_LOOP. 1271556Srgrimes CLC, 1281556Srgrimes CLC_LOOP, 1291556Srgrimes 1301556Srgrimes // Use an MVST-based sequence to implement stpcpy(). 1311556Srgrimes STPCPY, 1321556Srgrimes 1331556Srgrimes // Use a CLST-based sequence to implement strcmp(). The two input operands 1341556Srgrimes // are the addresses of the strings to compare. 1351556Srgrimes STRCMP, 13662311Sgreen 13762311Sgreen // Use an SRST-based sequence to search a block of memory. The first 1381556Srgrimes // operand is the end address, the second is the start, and the third 1391556Srgrimes // is the character to search for. CC is set to 1 on success and 2 1401556Srgrimes // on failure. 14162311Sgreen SEARCH_STRING, 1421556Srgrimes 1431556Srgrimes // Store the CC value in bits 29 and 28 of an integer. 1441556Srgrimes IPM, 1451556Srgrimes 1461556Srgrimes // Perform a serialization operation. (BCR 15,0 or BCR 14,0.) 1471556Srgrimes SERIALIZE, 1481556Srgrimes 14951249Sgreen // Transaction begin. The first operand is the chain, the second 1501556Srgrimes // the TDB pointer, and the third the immediate control field. 1511556Srgrimes // Returns chain and glue. 1521556Srgrimes TBEGIN, 1531556Srgrimes TBEGIN_NOFLOAT, 1541556Srgrimes 1551556Srgrimes // Transaction end. Just the chain operand. Returns chain and glue. 15651249Sgreen TEND, 1571556Srgrimes 1581556Srgrimes // Create a vector constant by filling byte N of the result with bit 1591556Srgrimes // 15-N of the single operand. 1601556Srgrimes BYTE_MASK, 1611556Srgrimes 1621556Srgrimes // Create a vector constant by replicating an element-sized RISBG-style mask. 1631556Srgrimes // The first operand specifies the starting set bit and the second operand 1641556Srgrimes // specifies the ending set bit. Both operands count from the MSB of the 1651556Srgrimes // element. 1661556Srgrimes ROTATE_MASK, 1671556Srgrimes 16851249Sgreen // Replicate a GPR scalar value into all elements of a vector. 16951208Sgreen REPLICATE, 17051208Sgreen 17151208Sgreen // Create a vector from two i64 GPRs. 172111629Smarkm JOIN_DWORDS, 173111629Smarkm 174273743Spi // Replicate one element of a vector into all elements. The first operand 175273743Spi // is the vector and the second is the index of the element to replicate. 1761556Srgrimes SPLAT, 1771556Srgrimes 1781556Srgrimes // Interleave elements from the high half of operand 0 and the high half 17990108Simp // of operand 1. 1801556Srgrimes MERGE_HIGH, 1811556Srgrimes 18254278Sgreen // Likewise for the low halves. 18354278Sgreen MERGE_LOW, 1841556Srgrimes 1851556Srgrimes // Concatenate the vectors in the first two operands, shift them left 1861556Srgrimes // by the third operand, and take the first half of the result. 18790108Simp SHL_DOUBLE, 1881556Srgrimes 189273743Spi // Take one element of the first v2i64 operand and the one element of 1901556Srgrimes // the second v2i64 operand and concatenate them to form a v2i64 result. 191273743Spi // The third operand is a 4-bit value of the form 0A0B, where A and B 192273743Spi // are the element selectors for the first operand and second operands 193273743Spi // respectively. 194273743Spi PERMUTE_DWORDS, 1951556Srgrimes 1961556Srgrimes // Perform a general vector permute on vector operands 0 and 1. 1971556Srgrimes // Each byte of operand 2 controls the corresponding byte of the result, 19890108Simp // in the same way as a byte-level VECTOR_SHUFFLE mask. 1991556Srgrimes PERMUTE, 200273743Spi 2011556Srgrimes // Pack vector operands 0 and 1 into a single vector with half-sized elements. 202273743Spi PACK, 203273743Spi 204273743Spi // Likewise, but saturate the result and set CC. PACKS_CC does signed 205273743Spi // saturation and PACKLS_CC does unsigned saturation. 2061556Srgrimes PACKS_CC, 2071556Srgrimes PACKLS_CC, 2081556Srgrimes 20990108Simp // Unpack the first half of vector operand 0 into double-sized elements. 2101556Srgrimes // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends. 211273743Spi UNPACK_HIGH, 2121556Srgrimes UNPACKL_HIGH, 213273743Spi 214273743Spi // Likewise for the second half. 215273743Spi UNPACK_LOW, 216273743Spi UNPACKL_LOW, 217273743Spi 218273743Spi // Shift each element of vector operand 0 by the number of bits specified 219273743Spi // by scalar operand 1. 2201556Srgrimes VSHL_BY_SCALAR, 2211556Srgrimes VSRL_BY_SCALAR, 2221556Srgrimes VSRA_BY_SCALAR, 22390108Simp 2241556Srgrimes // For each element of the output type, sum across all sub-elements of 2251556Srgrimes // operand 0 belonging to the corresponding element, and add in the 22651137Sgreen // rightmost sub-element of the corresponding element of operand 1. 22751249Sgreen VSUM, 228273743Spi 2291556Srgrimes // Compare integer vector operands 0 and 1 to produce the usual 0/-1 2301556Srgrimes // vector result. VICMPE is for equality, VICMPH for "signed greater than" 2311556Srgrimes // and VICMPHL for "unsigned greater than". 232133762Srwatson VICMPE, 233133762Srwatson VICMPH, 234133762Srwatson VICMPHL, 235133762Srwatson 236133762Srwatson // Likewise, but also set the condition codes on the result. 237133762Srwatson VICMPES, 238133762Srwatson VICMPHS, 239133762Srwatson VICMPHLS, 240133762Srwatson 241133762Srwatson // Compare floating-point vector operands 0 and 1 to preoduce the usual 0/-1 24290108Simp // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and 2431556Srgrimes // greater than" and VFCMPHE for "ordered and greater than or equal to". 244273743Spi VFCMPE, 2451556Srgrimes VFCMPH, 24648051Sgreen VFCMPHE, 247273743Spi 248273743Spi // Likewise, but also set the condition codes on the result. 249273743Spi VFCMPES, 250273743Spi VFCMPHS, 251273743Spi VFCMPHES, 25248051Sgreen 2531556Srgrimes // Test floating-point data class for vectors. 2541556Srgrimes VFTCI, 2551556Srgrimes 25690108Simp // Extend the even f32 elements of vector operand 0 to produce a vector 2571556Srgrimes // of f64 elements. 2581556Srgrimes VEXTEND, 2591556Srgrimes 2601556Srgrimes // Round the f64 elements of vector operand 0 to f32s and store them in the 2611556Srgrimes // even elements of the result. 2621556Srgrimes VROUND, 26390108Simp 2641556Srgrimes // AND the two vector operands together and set CC based on the result. 265273743Spi VTM, 2661556Srgrimes 26748051Sgreen // String operations that set CC as a side-effect. 268273743Spi VFAE_CC, 269273743Spi VFAEZ_CC, 270273743Spi VFEE_CC, 271273743Spi VFEEZ_CC, 272273743Spi VFENE_CC, 27348051Sgreen VFENEZ_CC, 2741556Srgrimes VISTR_CC, 2751556Srgrimes VSTRC_CC, 2761556Srgrimes VSTRCZ_CC, 27790108Simp 2781556Srgrimes // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or 2791556Srgrimes // ATOMIC_LOAD_<op>. 2801556Srgrimes // 2811556Srgrimes // Operand 0: the address of the containing 32-bit-aligned field 2821556Srgrimes // Operand 1: the second operand of <op>, in the high bits of an i32 2831556Srgrimes // for everything except ATOMIC_SWAPW 28490108Simp // Operand 2: how many bits to rotate the i32 left to bring the first 2851556Srgrimes // operand into the high bits 2861556Srgrimes // Operand 3: the negative of operand 2, for rotating the other way 28789788Sgreen // Operand 4: the width of the field in bits (8 or 16) 2881556Srgrimes ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE, 2891556Srgrimes ATOMIC_LOADW_ADD, 2901556Srgrimes ATOMIC_LOADW_SUB, 29190108Simp ATOMIC_LOADW_AND, 2921556Srgrimes ATOMIC_LOADW_OR, 2931556Srgrimes ATOMIC_LOADW_XOR, 29489788Sgreen ATOMIC_LOADW_NAND, 2951556Srgrimes ATOMIC_LOADW_MIN, 2961556Srgrimes ATOMIC_LOADW_MAX, 297264059Sdelphij ATOMIC_LOADW_UMIN, 298264059Sdelphij ATOMIC_LOADW_UMAX, 299264059Sdelphij 300264059Sdelphij // A wrapper around the inner loop of an ATOMIC_CMP_SWAP. 301264059Sdelphij // 302264059Sdelphij // Operand 0: the address of the containing 32-bit-aligned field 303264059Sdelphij // Operand 1: the compare value, in the low bits of an i32 304264059Sdelphij // Operand 2: the swap value, in the low bits of an i32 305264059Sdelphij // Operand 3: how many bits to rotate the i32 left to bring the first 306264059Sdelphij // operand into the high bits 307264059Sdelphij // Operand 4: the negative of operand 2, for rotating the other way 308264059Sdelphij // Operand 5: the width of the field in bits (8 or 16) 30951208Sgreen ATOMIC_CMP_SWAPW, 31054245Sgreen 3111556Srgrimes // Prefetch from the second operand using the 4-bit control code in 31251208Sgreen // the first operand. The code is 1 for a load prefetch and 2 for 3131556Srgrimes // a store prefetch. 3141556Srgrimes PREFETCH 3151556Srgrimes}; 3161556Srgrimes 3171556Srgrimes// Return true if OPCODE is some kind of PC-relative address. 3181556Srgrimesinline bool isPCREL(unsigned Opcode) { 3191556Srgrimes return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET; 3201556Srgrimes} 3211556Srgrimes} // end namespace SystemZISD 3221556Srgrimes 3231556Srgrimesnamespace SystemZICMP { 32431120Sjoerg// Describes whether an integer comparison needs to be signed or unsigned, 325126667Sphk// or whether either type is OK. 326126667Sphkenum { 327126667Sphk Any, 328126667Sphk UnsignedOnly, 32930312Sjoerg SignedOnly 3301556Srgrimes}; 3311556Srgrimes} // end namespace SystemZICMP 3321556Srgrimes 3331556Srgrimesclass SystemZSubtarget; 3341556Srgrimesclass SystemZTargetMachine; 3351556Srgrimes 3361556Srgrimesclass SystemZTargetLowering : public TargetLowering { 33790108Simppublic: 3381556Srgrimes explicit SystemZTargetLowering(const TargetMachine &TM, 3391556Srgrimes const SystemZSubtarget &STI); 3401556Srgrimes 3411556Srgrimes // Override TargetLowering. 3421556Srgrimes MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 34351208Sgreen return MVT::i32; 34451208Sgreen } 34551208Sgreen MVT getVectorIdxTy(const DataLayout &DL) const override { 3461556Srgrimes // Only the lower 12 bits of an element index are used, so we don't 3471556Srgrimes // want to clobber the upper 32 bits of a GPR unnecessarily. 3481556Srgrimes return MVT::i32; 3491556Srgrimes } 3501556Srgrimes TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) 3511556Srgrimes const override { 3521556Srgrimes // Widen subvectors to the full width rather than promoting integer 3531556Srgrimes // elements. This is better because: 3541556Srgrimes // 3551556Srgrimes // (a) it means that we can handle the ABI for passing and returning 35690108Simp // sub-128 vectors without having to handle them as legal types. 3571556Srgrimes // 3581556Srgrimes // (b) we don't have instructions to extend on load and truncate on store, 35954278Sgreen // so promoting the integers is less efficient. 36054278Sgreen // 3611556Srgrimes // (c) there are no multiplication instructions for the widest integer 3621556Srgrimes // type (v2i64). 363295260Strasz if (VT.getVectorElementType().getSizeInBits() % 8 == 0) 364295260Strasz return TypeWidenVector; 365295260Strasz return TargetLoweringBase::getPreferredVectorAction(VT); 366295260Strasz } 367295260Strasz EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, 368295260Strasz EVT) const override; 369295260Strasz bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 370295260Strasz bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 371295260Strasz bool isLegalICmpImmediate(int64_t Imm) const override; 372295260Strasz bool isLegalAddImmediate(int64_t Imm) const override; 373295260Strasz bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 374295260Strasz unsigned AS) const override; 375295260Strasz bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, 376295260Strasz unsigned Align, 377295260Strasz bool *Fast) const override; 378295260Strasz bool isTruncateFree(Type *, Type *) const override; 379295260Strasz bool isTruncateFree(EVT, EVT) const override; 380295260Strasz const char *getTargetNodeName(unsigned Opcode) const override; 381295260Strasz std::pair<unsigned, const TargetRegisterClass *> 382295260Strasz getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 383295260Strasz StringRef Constraint, MVT VT) const override; 384295260Strasz TargetLowering::ConstraintType 385295260Strasz getConstraintType(StringRef Constraint) const override; 386295261Strasz TargetLowering::ConstraintWeight 387295261Strasz getSingleConstraintMatchWeight(AsmOperandInfo &info, 388295261Strasz const char *constraint) const override; 389295261Strasz void LowerAsmOperandForConstraint(SDValue Op, 390295261Strasz std::string &Constraint, 391295261Strasz std::vector<SDValue> &Ops, 392295261Strasz SelectionDAG &DAG) const override; 393295261Strasz 394295260Strasz unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 395295260Strasz if (ConstraintCode.size() == 1) { 396295260Strasz switch(ConstraintCode[0]) { 397295260Strasz default: 398295260Strasz break; 399295260Strasz case 'Q': 400295260Strasz return InlineAsm::Constraint_Q; 401295260Strasz case 'R': 402295260Strasz return InlineAsm::Constraint_R; 4031556Srgrimes case 'S': 404111629Smarkm return InlineAsm::Constraint_S; 4051556Srgrimes case 'T': 406132933Spjd return InlineAsm::Constraint_T; 407132933Spjd } 408132933Spjd } 409132933Spjd return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 410132933Spjd } 411132933Spjd 412132933Spjd /// If a physical register, this returns the register that receives the 413132933Spjd /// exception address on entry to an EH pad. 4141556Srgrimes unsigned 415111629Smarkm getExceptionPointerRegister(const Constant *PersonalityFn) const override { 41690108Simp return SystemZ::R6D; 4171556Srgrimes } 418111629Smarkm 4191556Srgrimes /// If a physical register, this returns the register that receives the 4201556Srgrimes /// exception typeid on entry to a landing pad. 42148051Sgreen unsigned 422273743Spi getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 42351208Sgreen return SystemZ::R7D; 42448051Sgreen } 425273743Spi 42651208Sgreen MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 4271556Srgrimes MachineBasicBlock *BB) const 4281556Srgrimes override; 429295260Strasz SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 4301556Srgrimes bool allowTruncateForTailCall(Type *, Type *) const override; 43189788Sgreen bool mayBeEmittedAsTailCall(CallInst *CI) const override; 43289788Sgreen SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 43389788Sgreen bool isVarArg, 43489788Sgreen const SmallVectorImpl<ISD::InputArg> &Ins, 43589788Sgreen SDLoc DL, SelectionDAG &DAG, 43689788Sgreen SmallVectorImpl<SDValue> &InVals) const override; 43789788Sgreen SDValue LowerCall(CallLoweringInfo &CLI, 43889788Sgreen SmallVectorImpl<SDValue> &InVals) const override; 43989788Sgreen 44051137Sgreen bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 4411556Srgrimes bool isVarArg, 4421556Srgrimes const SmallVectorImpl<ISD::OutputArg> &Outs, 4431556Srgrimes LLVMContext &Context) const override; 444132933Spjd SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 4451556Srgrimes const SmallVectorImpl<ISD::OutputArg> &Outs, 44689788Sgreen const SmallVectorImpl<SDValue> &OutVals, 44789788Sgreen SDLoc DL, SelectionDAG &DAG) const override; 44889788Sgreen SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, 44989788Sgreen SelectionDAG &DAG) const override; 45051137Sgreen SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 45151137Sgreen 45251137Sgreenprivate: 4531556Srgrimes const SystemZSubtarget &Subtarget; 4541556Srgrimes 4551556Srgrimes // Implement LowerOperation for individual opcodes. 4561556Srgrimes SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 4571556Srgrimes SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 45851208Sgreen SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 45989788Sgreen SDValue lowerGlobalAddress(GlobalAddressSDNode *Node, 46089788Sgreen SelectionDAG &DAG) const; 46189788Sgreen SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node, 46289788Sgreen SelectionDAG &DAG, unsigned Opcode, 463111629Smarkm SDValue GOTOffset) const; 46489788Sgreen SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node, 46551208Sgreen SelectionDAG &DAG) const; 46690108Simp SDValue lowerBlockAddress(BlockAddressSDNode *Node, 46751208Sgreen SelectionDAG &DAG) const; 468111629Smarkm SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const; 46989788Sgreen SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const; 47051208Sgreen SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 47189788Sgreen SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 47289788Sgreen SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 47389788Sgreen SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 47489788Sgreen SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 47589788Sgreen SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const; 47689788Sgreen SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 47789788Sgreen SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 47889788Sgreen SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const; 479295260Strasz SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const; 48089788Sgreen SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const; 48189788Sgreen SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const; 48289788Sgreen SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG, 48389788Sgreen unsigned Opcode) const; 48489788Sgreen SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const; 48589788Sgreen SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 48689788Sgreen SDValue lowerLOAD_SEQUENCE_POINT(SDValue Op, SelectionDAG &DAG) const; 48789788Sgreen SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; 48889788Sgreen SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; 48989788Sgreen SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const; 49089788Sgreen SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 49189788Sgreen SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 49289788Sgreen SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 49389788Sgreen SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 494132933Spjd SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 49589788Sgreen SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 496111629Smarkm SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 49789788Sgreen SDValue lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG, 49889788Sgreen unsigned UnpackHigh) const; 49990331Sgreen SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const; 50089788Sgreen 50189788Sgreen SDValue combineExtract(SDLoc DL, EVT ElemVT, EVT VecVT, SDValue OrigOp, 50289788Sgreen unsigned Index, DAGCombinerInfo &DCI, 50389788Sgreen bool Force) const; 50489788Sgreen SDValue combineTruncateExtract(SDLoc DL, EVT TruncVT, SDValue Op, 50589788Sgreen DAGCombinerInfo &DCI) const; 50689788Sgreen 50751208Sgreen // If the last instruction before MBBI in MBB was some form of COMPARE, 508 // try to replace it with a COMPARE AND BRANCH just before MBBI. 509 // CCMask and Target are the BRC-like operands for the branch. 510 // Return true if the change was made. 511 bool convertPrevCompareToBranch(MachineBasicBlock *MBB, 512 MachineBasicBlock::iterator MBBI, 513 unsigned CCMask, 514 MachineBasicBlock *Target) const; 515 516 // Implement EmitInstrWithCustomInserter for individual operation types. 517 MachineBasicBlock *emitSelect(MachineInstr *MI, 518 MachineBasicBlock *BB) const; 519 MachineBasicBlock *emitCondStore(MachineInstr *MI, 520 MachineBasicBlock *BB, 521 unsigned StoreOpcode, unsigned STOCOpcode, 522 bool Invert) const; 523 MachineBasicBlock *emitExt128(MachineInstr *MI, 524 MachineBasicBlock *MBB, 525 bool ClearEven, unsigned SubReg) const; 526 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI, 527 MachineBasicBlock *BB, 528 unsigned BinOpcode, unsigned BitSize, 529 bool Invert = false) const; 530 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI, 531 MachineBasicBlock *MBB, 532 unsigned CompareOpcode, 533 unsigned KeepOldMask, 534 unsigned BitSize) const; 535 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI, 536 MachineBasicBlock *BB) const; 537 MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI, 538 MachineBasicBlock *BB, 539 unsigned Opcode) const; 540 MachineBasicBlock *emitStringWrapper(MachineInstr *MI, 541 MachineBasicBlock *BB, 542 unsigned Opcode) const; 543 MachineBasicBlock *emitTransactionBegin(MachineInstr *MI, 544 MachineBasicBlock *MBB, 545 unsigned Opcode, 546 bool NoFloat) const; 547 MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr *MI, 548 MachineBasicBlock *MBB, 549 unsigned Opcode) const; 550 551}; 552} // end namespace llvm 553 554#endif 555