1251607Sdim//===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===// 2251607Sdim// 3251607Sdim// The LLVM Compiler Infrastructure 4251607Sdim// 5251607Sdim// This file is distributed under the University of Illinois Open Source 6251607Sdim// License. See LICENSE.TXT for details. 7251607Sdim// 8251607Sdim//===----------------------------------------------------------------------===// 9251607Sdim// 10251607Sdim// This file defines the interfaces that SystemZ uses to lower LLVM code into a 11251607Sdim// selection DAG. 12251607Sdim// 13251607Sdim//===----------------------------------------------------------------------===// 14251607Sdim 15280031Sdim#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H 16280031Sdim#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H 17251607Sdim 18251607Sdim#include "SystemZ.h" 19261991Sdim#include "llvm/CodeGen/MachineBasicBlock.h" 20251607Sdim#include "llvm/CodeGen/SelectionDAG.h" 21251607Sdim#include "llvm/Target/TargetLowering.h" 22251607Sdim 23251607Sdimnamespace llvm { 24251607Sdimnamespace SystemZISD { 25288943Sdimenum NodeType : unsigned { 26276479Sdim FIRST_NUMBER = ISD::BUILTIN_OP_END, 27251607Sdim 28276479Sdim // Return with a flag operand. Operand 0 is the chain operand. 29276479Sdim RET_FLAG, 30251607Sdim 31276479Sdim // Calls a function. Operand 0 is the chain operand and operand 1 32276479Sdim // is the target address. The arguments start at operand 2. 33276479Sdim // There is an optional glue operand at the end. 34276479Sdim CALL, 35276479Sdim SIBCALL, 36251607Sdim 37288943Sdim // TLS calls. Like regular calls, except operand 1 is the TLS symbol. 38288943Sdim // (The call target is implicitly __tls_get_offset.) 39288943Sdim TLS_GDCALL, 40288943Sdim TLS_LDCALL, 41288943Sdim 42276479Sdim // Wraps a TargetGlobalAddress that should be loaded using PC-relative 43276479Sdim // accesses (LARL). Operand 0 is the address. 44276479Sdim PCREL_WRAPPER, 45251607Sdim 46276479Sdim // Used in cases where an offset is applied to a TargetGlobalAddress. 47276479Sdim // Operand 0 is the full TargetGlobalAddress and operand 1 is a 48276479Sdim // PCREL_WRAPPER for an anchor point. This is used so that we can 49276479Sdim // cheaply refer to either the full address or the anchor point 50276479Sdim // as a register base. 51276479Sdim PCREL_OFFSET, 52251607Sdim 53276479Sdim // Integer absolute. 54276479Sdim IABS, 55251607Sdim 56276479Sdim // Integer comparisons. There are three operands: the two values 57276479Sdim // to compare, and an integer of type SystemZICMP. 58276479Sdim ICMP, 59261991Sdim 60276479Sdim // Floating-point comparisons. The two operands are the values to compare. 61276479Sdim FCMP, 62261991Sdim 63276479Sdim // Test under mask. The first operand is ANDed with the second operand 64276479Sdim // and the condition codes are set on the result. The third operand is 65276479Sdim // a boolean that is true if the condition codes need to distinguish 66276479Sdim // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the 67276479Sdim // register forms do but the memory forms don't). 68276479Sdim TM, 69251607Sdim 70276479Sdim // Branches if a condition is true. Operand 0 is the chain operand; 71276479Sdim // operand 1 is the 4-bit condition-code mask, with bit N in 72276479Sdim // big-endian order meaning "branch if CC=N"; operand 2 is the 73276479Sdim // target block and operand 3 is the flag operand. 74276479Sdim BR_CCMASK, 75251607Sdim 76276479Sdim // Selects between operand 0 and operand 1. Operand 2 is the 77276479Sdim // mask of condition-code values for which operand 0 should be 78276479Sdim // chosen over operand 1; it has the same form as BR_CCMASK. 79276479Sdim // Operand 3 is the flag operand. 80276479Sdim SELECT_CCMASK, 81251607Sdim 82276479Sdim // Evaluates to the gap between the stack pointer and the 83276479Sdim // base of the dynamically-allocatable area. 84276479Sdim ADJDYNALLOC, 85251607Sdim 86276479Sdim // Extracts the value of a 32-bit access register. Operand 0 is 87276479Sdim // the number of the register. 88276479Sdim EXTRACT_ACCESS, 89251607Sdim 90288943Sdim // Count number of bits set in operand 0 per byte. 91288943Sdim POPCNT, 92288943Sdim 93276479Sdim // Wrappers around the ISD opcodes of the same name. The output and 94276479Sdim // first input operands are GR128s. The trailing numbers are the 95276479Sdim // widths of the second operand in bits. 96276479Sdim UMUL_LOHI64, 97276479Sdim SDIVREM32, 98276479Sdim SDIVREM64, 99276479Sdim UDIVREM32, 100276479Sdim UDIVREM64, 101261991Sdim 102276479Sdim // Use a series of MVCs to copy bytes from one memory location to another. 103276479Sdim // The operands are: 104276479Sdim // - the target address 105276479Sdim // - the source address 106276479Sdim // - the constant length 107276479Sdim // 108276479Sdim // This isn't a memory opcode because we'd need to attach two 109276479Sdim // MachineMemOperands rather than one. 110276479Sdim MVC, 111261991Sdim 112276479Sdim // Like MVC, but implemented as a loop that handles X*256 bytes 113276479Sdim // followed by straight-line code to handle the rest (if any). 114276479Sdim // The value of X is passed as an additional operand. 115276479Sdim MVC_LOOP, 116261991Sdim 117276479Sdim // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR). 118276479Sdim NC, 119276479Sdim NC_LOOP, 120276479Sdim OC, 121276479Sdim OC_LOOP, 122276479Sdim XC, 123276479Sdim XC_LOOP, 124261991Sdim 125276479Sdim // Use CLC to compare two blocks of memory, with the same comments 126276479Sdim // as for MVC and MVC_LOOP. 127276479Sdim CLC, 128276479Sdim CLC_LOOP, 129261991Sdim 130276479Sdim // Use an MVST-based sequence to implement stpcpy(). 131276479Sdim STPCPY, 132261991Sdim 133276479Sdim // Use a CLST-based sequence to implement strcmp(). The two input operands 134276479Sdim // are the addresses of the strings to compare. 135276479Sdim STRCMP, 136261991Sdim 137276479Sdim // Use an SRST-based sequence to search a block of memory. The first 138276479Sdim // operand is the end address, the second is the start, and the third 139276479Sdim // is the character to search for. CC is set to 1 on success and 2 140276479Sdim // on failure. 141276479Sdim SEARCH_STRING, 142261991Sdim 143276479Sdim // Store the CC value in bits 29 and 28 of an integer. 144276479Sdim IPM, 145251607Sdim 146276479Sdim // Perform a serialization operation. (BCR 15,0 or BCR 14,0.) 147276479Sdim SERIALIZE, 148261991Sdim 149288943Sdim // Transaction begin. The first operand is the chain, the second 150288943Sdim // the TDB pointer, and the third the immediate control field. 151288943Sdim // Returns chain and glue. 152288943Sdim TBEGIN, 153288943Sdim TBEGIN_NOFLOAT, 154288943Sdim 155288943Sdim // Transaction end. Just the chain operand. Returns chain and glue. 156288943Sdim TEND, 157288943Sdim 158288943Sdim // Create a vector constant by filling byte N of the result with bit 159288943Sdim // 15-N of the single operand. 160288943Sdim BYTE_MASK, 161288943Sdim 162288943Sdim // Create a vector constant by replicating an element-sized RISBG-style mask. 163288943Sdim // The first operand specifies the starting set bit and the second operand 164288943Sdim // specifies the ending set bit. Both operands count from the MSB of the 165288943Sdim // element. 166288943Sdim ROTATE_MASK, 167288943Sdim 168288943Sdim // Replicate a GPR scalar value into all elements of a vector. 169288943Sdim REPLICATE, 170288943Sdim 171288943Sdim // Create a vector from two i64 GPRs. 172288943Sdim JOIN_DWORDS, 173288943Sdim 174288943Sdim // Replicate one element of a vector into all elements. The first operand 175288943Sdim // is the vector and the second is the index of the element to replicate. 176288943Sdim SPLAT, 177288943Sdim 178288943Sdim // Interleave elements from the high half of operand 0 and the high half 179288943Sdim // of operand 1. 180288943Sdim MERGE_HIGH, 181288943Sdim 182288943Sdim // Likewise for the low halves. 183288943Sdim MERGE_LOW, 184288943Sdim 185288943Sdim // Concatenate the vectors in the first two operands, shift them left 186288943Sdim // by the third operand, and take the first half of the result. 187288943Sdim SHL_DOUBLE, 188288943Sdim 189288943Sdim // Take one element of the first v2i64 operand and the one element of 190288943Sdim // the second v2i64 operand and concatenate them to form a v2i64 result. 191288943Sdim // The third operand is a 4-bit value of the form 0A0B, where A and B 192288943Sdim // are the element selectors for the first operand and second operands 193288943Sdim // respectively. 194288943Sdim PERMUTE_DWORDS, 195288943Sdim 196288943Sdim // Perform a general vector permute on vector operands 0 and 1. 197288943Sdim // Each byte of operand 2 controls the corresponding byte of the result, 198288943Sdim // in the same way as a byte-level VECTOR_SHUFFLE mask. 199288943Sdim PERMUTE, 200288943Sdim 201288943Sdim // Pack vector operands 0 and 1 into a single vector with half-sized elements. 202288943Sdim PACK, 203288943Sdim 204288943Sdim // Likewise, but saturate the result and set CC. PACKS_CC does signed 205288943Sdim // saturation and PACKLS_CC does unsigned saturation. 206288943Sdim PACKS_CC, 207288943Sdim PACKLS_CC, 208288943Sdim 209288943Sdim // Unpack the first half of vector operand 0 into double-sized elements. 210288943Sdim // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends. 211288943Sdim UNPACK_HIGH, 212288943Sdim UNPACKL_HIGH, 213288943Sdim 214288943Sdim // Likewise for the second half. 215288943Sdim UNPACK_LOW, 216288943Sdim UNPACKL_LOW, 217288943Sdim 218288943Sdim // Shift each element of vector operand 0 by the number of bits specified 219288943Sdim // by scalar operand 1. 220288943Sdim VSHL_BY_SCALAR, 221288943Sdim VSRL_BY_SCALAR, 222288943Sdim VSRA_BY_SCALAR, 223288943Sdim 224288943Sdim // For each element of the output type, sum across all sub-elements of 225288943Sdim // operand 0 belonging to the corresponding element, and add in the 226288943Sdim // rightmost sub-element of the corresponding element of operand 1. 227288943Sdim VSUM, 228288943Sdim 229288943Sdim // Compare integer vector operands 0 and 1 to produce the usual 0/-1 230288943Sdim // vector result. VICMPE is for equality, VICMPH for "signed greater than" 231288943Sdim // and VICMPHL for "unsigned greater than". 232288943Sdim VICMPE, 233288943Sdim VICMPH, 234288943Sdim VICMPHL, 235288943Sdim 236288943Sdim // Likewise, but also set the condition codes on the result. 237288943Sdim VICMPES, 238288943Sdim VICMPHS, 239288943Sdim VICMPHLS, 240288943Sdim 241288943Sdim // Compare floating-point vector operands 0 and 1 to preoduce the usual 0/-1 242288943Sdim // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and 243288943Sdim // greater than" and VFCMPHE for "ordered and greater than or equal to". 244288943Sdim VFCMPE, 245288943Sdim VFCMPH, 246288943Sdim VFCMPHE, 247288943Sdim 248288943Sdim // Likewise, but also set the condition codes on the result. 249288943Sdim VFCMPES, 250288943Sdim VFCMPHS, 251288943Sdim VFCMPHES, 252288943Sdim 253288943Sdim // Test floating-point data class for vectors. 254288943Sdim VFTCI, 255288943Sdim 256288943Sdim // Extend the even f32 elements of vector operand 0 to produce a vector 257288943Sdim // of f64 elements. 258288943Sdim VEXTEND, 259288943Sdim 260288943Sdim // Round the f64 elements of vector operand 0 to f32s and store them in the 261288943Sdim // even elements of the result. 262288943Sdim VROUND, 263288943Sdim 264288943Sdim // AND the two vector operands together and set CC based on the result. 265288943Sdim VTM, 266288943Sdim 267288943Sdim // String operations that set CC as a side-effect. 268288943Sdim VFAE_CC, 269288943Sdim VFAEZ_CC, 270288943Sdim VFEE_CC, 271288943Sdim VFEEZ_CC, 272288943Sdim VFENE_CC, 273288943Sdim VFENEZ_CC, 274288943Sdim VISTR_CC, 275288943Sdim VSTRC_CC, 276288943Sdim VSTRCZ_CC, 277288943Sdim 278276479Sdim // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or 279276479Sdim // ATOMIC_LOAD_<op>. 280276479Sdim // 281276479Sdim // Operand 0: the address of the containing 32-bit-aligned field 282276479Sdim // Operand 1: the second operand of <op>, in the high bits of an i32 283276479Sdim // for everything except ATOMIC_SWAPW 284276479Sdim // Operand 2: how many bits to rotate the i32 left to bring the first 285276479Sdim // operand into the high bits 286276479Sdim // Operand 3: the negative of operand 2, for rotating the other way 287276479Sdim // Operand 4: the width of the field in bits (8 or 16) 288276479Sdim ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE, 289276479Sdim ATOMIC_LOADW_ADD, 290276479Sdim ATOMIC_LOADW_SUB, 291276479Sdim ATOMIC_LOADW_AND, 292276479Sdim ATOMIC_LOADW_OR, 293276479Sdim ATOMIC_LOADW_XOR, 294276479Sdim ATOMIC_LOADW_NAND, 295276479Sdim ATOMIC_LOADW_MIN, 296276479Sdim ATOMIC_LOADW_MAX, 297276479Sdim ATOMIC_LOADW_UMIN, 298276479Sdim ATOMIC_LOADW_UMAX, 299261991Sdim 300276479Sdim // A wrapper around the inner loop of an ATOMIC_CMP_SWAP. 301276479Sdim // 302276479Sdim // Operand 0: the address of the containing 32-bit-aligned field 303276479Sdim // Operand 1: the compare value, in the low bits of an i32 304276479Sdim // Operand 2: the swap value, in the low bits of an i32 305276479Sdim // Operand 3: how many bits to rotate the i32 left to bring the first 306276479Sdim // operand into the high bits 307276479Sdim // Operand 4: the negative of operand 2, for rotating the other way 308276479Sdim // Operand 5: the width of the field in bits (8 or 16) 309276479Sdim ATOMIC_CMP_SWAPW, 310276479Sdim 311276479Sdim // Prefetch from the second operand using the 4-bit control code in 312276479Sdim // the first operand. The code is 1 for a load prefetch and 2 for 313276479Sdim // a store prefetch. 314276479Sdim PREFETCH 315276479Sdim}; 316276479Sdim 317276479Sdim// Return true if OPCODE is some kind of PC-relative address. 318276479Sdiminline bool isPCREL(unsigned Opcode) { 319276479Sdim return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET; 320251607Sdim} 321276479Sdim} // end namespace SystemZISD 322251607Sdim 323261991Sdimnamespace SystemZICMP { 324276479Sdim// Describes whether an integer comparison needs to be signed or unsigned, 325276479Sdim// or whether either type is OK. 326276479Sdimenum { 327276479Sdim Any, 328276479Sdim UnsignedOnly, 329276479Sdim SignedOnly 330276479Sdim}; 331276479Sdim} // end namespace SystemZICMP 332261991Sdim 333251607Sdimclass SystemZSubtarget; 334251607Sdimclass SystemZTargetMachine; 335251607Sdim 336251607Sdimclass SystemZTargetLowering : public TargetLowering { 337251607Sdimpublic: 338288943Sdim explicit SystemZTargetLowering(const TargetMachine &TM, 339288943Sdim const SystemZSubtarget &STI); 340251607Sdim 341251607Sdim // Override TargetLowering. 342288943Sdim MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 343251607Sdim return MVT::i32; 344251607Sdim } 345288943Sdim MVT getVectorIdxTy(const DataLayout &DL) const override { 346288943Sdim // Only the lower 12 bits of an element index are used, so we don't 347288943Sdim // want to clobber the upper 32 bits of a GPR unnecessarily. 348288943Sdim return MVT::i32; 349288943Sdim } 350288943Sdim TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) 351288943Sdim const override { 352288943Sdim // Widen subvectors to the full width rather than promoting integer 353288943Sdim // elements. This is better because: 354288943Sdim // 355288943Sdim // (a) it means that we can handle the ABI for passing and returning 356288943Sdim // sub-128 vectors without having to handle them as legal types. 357288943Sdim // 358288943Sdim // (b) we don't have instructions to extend on load and truncate on store, 359288943Sdim // so promoting the integers is less efficient. 360288943Sdim // 361288943Sdim // (c) there are no multiplication instructions for the widest integer 362288943Sdim // type (v2i64). 363288943Sdim if (VT.getVectorElementType().getSizeInBits() % 8 == 0) 364288943Sdim return TypeWidenVector; 365288943Sdim return TargetLoweringBase::getPreferredVectorAction(VT); 366288943Sdim } 367288943Sdim EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, 368288943Sdim EVT) const override; 369276479Sdim bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 370276479Sdim bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 371288943Sdim bool isLegalICmpImmediate(int64_t Imm) const override; 372288943Sdim bool isLegalAddImmediate(int64_t Imm) const override; 373288943Sdim bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 374288943Sdim unsigned AS) const override; 375280031Sdim bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, 376280031Sdim unsigned Align, 377280031Sdim bool *Fast) const override; 378276479Sdim bool isTruncateFree(Type *, Type *) const override; 379276479Sdim bool isTruncateFree(EVT, EVT) const override; 380276479Sdim const char *getTargetNodeName(unsigned Opcode) const override; 381276479Sdim std::pair<unsigned, const TargetRegisterClass *> 382288943Sdim getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 383288943Sdim StringRef Constraint, MVT VT) const override; 384276479Sdim TargetLowering::ConstraintType 385288943Sdim getConstraintType(StringRef Constraint) const override; 386276479Sdim TargetLowering::ConstraintWeight 387251607Sdim getSingleConstraintMatchWeight(AsmOperandInfo &info, 388276479Sdim const char *constraint) const override; 389276479Sdim void LowerAsmOperandForConstraint(SDValue Op, 390276479Sdim std::string &Constraint, 391276479Sdim std::vector<SDValue> &Ops, 392276479Sdim SelectionDAG &DAG) const override; 393288943Sdim 394288943Sdim unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 395288943Sdim if (ConstraintCode.size() == 1) { 396288943Sdim switch(ConstraintCode[0]) { 397288943Sdim default: 398288943Sdim break; 399288943Sdim case 'Q': 400288943Sdim return InlineAsm::Constraint_Q; 401288943Sdim case 'R': 402288943Sdim return InlineAsm::Constraint_R; 403288943Sdim case 'S': 404288943Sdim return InlineAsm::Constraint_S; 405288943Sdim case 'T': 406288943Sdim return InlineAsm::Constraint_T; 407288943Sdim } 408288943Sdim } 409288943Sdim return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 410288943Sdim } 411288943Sdim 412296417Sdim /// If a physical register, this returns the register that receives the 413296417Sdim /// exception address on entry to an EH pad. 414296417Sdim unsigned 415296417Sdim getExceptionPointerRegister(const Constant *PersonalityFn) const override { 416296417Sdim return SystemZ::R6D; 417296417Sdim } 418296417Sdim 419296417Sdim /// If a physical register, this returns the register that receives the 420296417Sdim /// exception typeid on entry to a landing pad. 421296417Sdim unsigned 422296417Sdim getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 423296417Sdim return SystemZ::R7D; 424296417Sdim } 425296417Sdim 426276479Sdim MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 427276479Sdim MachineBasicBlock *BB) const 428276479Sdim override; 429276479Sdim SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 430276479Sdim bool allowTruncateForTailCall(Type *, Type *) const override; 431276479Sdim bool mayBeEmittedAsTailCall(CallInst *CI) const override; 432276479Sdim SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 433276479Sdim bool isVarArg, 434276479Sdim const SmallVectorImpl<ISD::InputArg> &Ins, 435276479Sdim SDLoc DL, SelectionDAG &DAG, 436276479Sdim SmallVectorImpl<SDValue> &InVals) const override; 437276479Sdim SDValue LowerCall(CallLoweringInfo &CLI, 438276479Sdim SmallVectorImpl<SDValue> &InVals) const override; 439251607Sdim 440288943Sdim bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 441288943Sdim bool isVarArg, 442288943Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 443288943Sdim LLVMContext &Context) const override; 444276479Sdim SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 445276479Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 446276479Sdim const SmallVectorImpl<SDValue> &OutVals, 447276479Sdim SDLoc DL, SelectionDAG &DAG) const override; 448276479Sdim SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, 449276479Sdim SelectionDAG &DAG) const override; 450276479Sdim SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 451251607Sdim 452251607Sdimprivate: 453251607Sdim const SystemZSubtarget &Subtarget; 454251607Sdim 455251607Sdim // Implement LowerOperation for individual opcodes. 456261991Sdim SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 457251607Sdim SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 458251607Sdim SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 459251607Sdim SDValue lowerGlobalAddress(GlobalAddressSDNode *Node, 460251607Sdim SelectionDAG &DAG) const; 461288943Sdim SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node, 462288943Sdim SelectionDAG &DAG, unsigned Opcode, 463288943Sdim SDValue GOTOffset) const; 464251607Sdim SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node, 465251607Sdim SelectionDAG &DAG) const; 466251607Sdim SDValue lowerBlockAddress(BlockAddressSDNode *Node, 467251607Sdim SelectionDAG &DAG) const; 468251607Sdim SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const; 469251607Sdim SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const; 470251607Sdim SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 471251607Sdim SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 472251607Sdim SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 473261991Sdim SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 474251607Sdim SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 475251607Sdim SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const; 476251607Sdim SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 477251607Sdim SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 478251607Sdim SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const; 479288943Sdim SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const; 480276479Sdim SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const; 481276479Sdim SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const; 482276479Sdim SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG, 483276479Sdim unsigned Opcode) const; 484276479Sdim SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const; 485251607Sdim SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 486276479Sdim SDValue lowerLOAD_SEQUENCE_POINT(SDValue Op, SelectionDAG &DAG) const; 487251607Sdim SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; 488251607Sdim SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; 489261991Sdim SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const; 490288943Sdim SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 491288943Sdim SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 492288943Sdim SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 493288943Sdim SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 494288943Sdim SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 495288943Sdim SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 496288943Sdim SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 497288943Sdim SDValue lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG, 498296417Sdim unsigned UnpackHigh) const; 499288943Sdim SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const; 500251607Sdim 501288943Sdim SDValue combineExtract(SDLoc DL, EVT ElemVT, EVT VecVT, SDValue OrigOp, 502288943Sdim unsigned Index, DAGCombinerInfo &DCI, 503288943Sdim bool Force) const; 504288943Sdim SDValue combineTruncateExtract(SDLoc DL, EVT TruncVT, SDValue Op, 505288943Sdim DAGCombinerInfo &DCI) const; 506288943Sdim 507261991Sdim // If the last instruction before MBBI in MBB was some form of COMPARE, 508261991Sdim // try to replace it with a COMPARE AND BRANCH just before MBBI. 509261991Sdim // CCMask and Target are the BRC-like operands for the branch. 510261991Sdim // Return true if the change was made. 511261991Sdim bool convertPrevCompareToBranch(MachineBasicBlock *MBB, 512261991Sdim MachineBasicBlock::iterator MBBI, 513261991Sdim unsigned CCMask, 514261991Sdim MachineBasicBlock *Target) const; 515261991Sdim 516251607Sdim // Implement EmitInstrWithCustomInserter for individual operation types. 517251607Sdim MachineBasicBlock *emitSelect(MachineInstr *MI, 518251607Sdim MachineBasicBlock *BB) const; 519261991Sdim MachineBasicBlock *emitCondStore(MachineInstr *MI, 520261991Sdim MachineBasicBlock *BB, 521261991Sdim unsigned StoreOpcode, unsigned STOCOpcode, 522261991Sdim bool Invert) const; 523251607Sdim MachineBasicBlock *emitExt128(MachineInstr *MI, 524251607Sdim MachineBasicBlock *MBB, 525251607Sdim bool ClearEven, unsigned SubReg) const; 526251607Sdim MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI, 527251607Sdim MachineBasicBlock *BB, 528251607Sdim unsigned BinOpcode, unsigned BitSize, 529251607Sdim bool Invert = false) const; 530251607Sdim MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI, 531251607Sdim MachineBasicBlock *MBB, 532251607Sdim unsigned CompareOpcode, 533251607Sdim unsigned KeepOldMask, 534251607Sdim unsigned BitSize) const; 535251607Sdim MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI, 536251607Sdim MachineBasicBlock *BB) const; 537261991Sdim MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI, 538261991Sdim MachineBasicBlock *BB, 539261991Sdim unsigned Opcode) const; 540261991Sdim MachineBasicBlock *emitStringWrapper(MachineInstr *MI, 541261991Sdim MachineBasicBlock *BB, 542261991Sdim unsigned Opcode) const; 543288943Sdim MachineBasicBlock *emitTransactionBegin(MachineInstr *MI, 544288943Sdim MachineBasicBlock *MBB, 545288943Sdim unsigned Opcode, 546288943Sdim bool NoFloat) const; 547296417Sdim MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr *MI, 548296417Sdim MachineBasicBlock *MBB, 549296417Sdim unsigned Opcode) const; 550296417Sdim 551251607Sdim}; 552251607Sdim} // end namespace llvm 553251607Sdim 554280031Sdim#endif 555