SparcRegisterInfo.cpp revision 251662 
1//===-- SparcRegisterInfo.cpp - SPARC Register Information ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SPARC implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcRegisterInfo.h"
15#include "Sparc.h"
16#include "SparcSubtarget.h"
17#include "llvm/ADT/BitVector.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/IR/Type.h"
23#include "llvm/Support/ErrorHandling.h"
24#include "llvm/Target/TargetInstrInfo.h"
25
26#define GET_REGINFO_TARGET_DESC
27#include "SparcGenRegisterInfo.inc"
28
29using namespace llvm;
30
31SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
32                                     const TargetInstrInfo &tii)
33  : SparcGenRegisterInfo(SP::I7), Subtarget(st), TII(tii) {
34}
35
36const uint16_t* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
37                                                                         const {
38  static const uint16_t CalleeSavedRegs[] = { 0 };
39  return CalleeSavedRegs;
40}
41
42BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
43  BitVector Reserved(getNumRegs());
44  // FIXME: G1 reserved for now for large imm generation by frame code.
45  Reserved.set(SP::G1);
46  Reserved.set(SP::G2);
47  Reserved.set(SP::G3);
48  Reserved.set(SP::G4);
49  Reserved.set(SP::O6);
50  Reserved.set(SP::I6);
51  Reserved.set(SP::I7);
52  Reserved.set(SP::G0);
53  Reserved.set(SP::G5);
54  Reserved.set(SP::G6);
55  Reserved.set(SP::G7);
56  return Reserved;
57}
58
59const TargetRegisterClass*
60SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF,
61                                      unsigned Kind) const {
62  return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
63}
64
65void
66SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
67                                       int SPAdj, unsigned FIOperandNum,
68                                       RegScavenger *RS) const {
69  assert(SPAdj == 0 && "Unexpected");
70
71  MachineInstr &MI = *II;
72  DebugLoc dl = MI.getDebugLoc();
73  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
74
75  // Addressable stack objects are accessed using neg. offsets from %fp
76  MachineFunction &MF = *MI.getParent()->getParent();
77  int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
78                   MI.getOperand(FIOperandNum + 1).getImm() +
79                   Subtarget.getStackPointerBias();
80
81  // Replace frame index with a frame pointer reference.
82  if (Offset >= -4096 && Offset <= 4095) {
83    // If the offset is small enough to fit in the immediate field, directly
84    // encode it.
85    MI.getOperand(FIOperandNum).ChangeToRegister(SP::I6, false);
86    MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
87  } else {
88    // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
89    // scavenge a register here instead of reserving G1 all of the time.
90    unsigned OffHi = (unsigned)Offset >> 10U;
91    BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
92    // Emit G1 = G1 + I6
93    BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
94      .addReg(SP::I6);
95    // Insert: G1+%lo(offset) into the user.
96    MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
97    MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset & ((1 << 10)-1));
98  }
99}
100
101unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
102  return SP::I6;
103}
104
105unsigned SparcRegisterInfo::getEHExceptionRegister() const {
106  llvm_unreachable("What is the exception register");
107}
108
109unsigned SparcRegisterInfo::getEHHandlerRegister() const {
110  llvm_unreachable("What is the exception handler register");
111}
112