SparcRegisterInfo.cpp revision 224145
1285101Semaste//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===// 2285101Semaste// 3285101Semaste// The LLVM Compiler Infrastructure 4285101Semaste// 5285101Semaste// This file is distributed under the University of Illinois Open Source 6285101Semaste// License. See LICENSE.TXT for details. 7285101Semaste// 8285101Semaste//===----------------------------------------------------------------------===// 9285101Semaste// 10285101Semaste// This file contains the SPARC implementation of the TargetRegisterInfo class. 11285101Semaste// 12285101Semaste//===----------------------------------------------------------------------===// 13285101Semaste 14285101Semaste#include "Sparc.h" 15285101Semaste#include "SparcRegisterInfo.h" 16285101Semaste#include "SparcSubtarget.h" 17285101Semaste#include "llvm/CodeGen/MachineInstrBuilder.h" 18285101Semaste#include "llvm/CodeGen/MachineFunction.h" 19285101Semaste#include "llvm/CodeGen/MachineFrameInfo.h" 20285101Semaste#include "llvm/CodeGen/MachineLocation.h" 21296417Sdim#include "llvm/Support/ErrorHandling.h" 22285101Semaste#include "llvm/Target/TargetInstrInfo.h" 23285101Semaste#include "llvm/Type.h" 24285101Semaste#include "llvm/ADT/BitVector.h" 25285101Semaste#include "llvm/ADT/STLExtras.h" 26285101Semaste 27285101Semaste#define GET_REGINFO_TARGET_DESC 28285101Semaste#include "SparcGenRegisterInfo.inc" 29285101Semaste 30285101Semasteusing namespace llvm; 31285101Semaste 32285101SemasteSparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st, 33285101Semaste const TargetInstrInfo &tii) 34285101Semaste : SparcGenRegisterInfo(), Subtarget(st), TII(tii) { 35285101Semaste} 36285101Semaste 37285101Semasteconst unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) 38285101Semaste const { 39285101Semaste static const unsigned CalleeSavedRegs[] = { 0 }; 40285101Semaste return CalleeSavedRegs; 41285101Semaste} 42285101Semaste 43285101SemasteBitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 44285101Semaste BitVector Reserved(getNumRegs()); 45285101Semaste // FIXME: G1 reserved for now for large imm generation by frame code. 46285101Semaste Reserved.set(SP::G1); 47285101Semaste Reserved.set(SP::G2); 48296417Sdim Reserved.set(SP::G3); 49285101Semaste Reserved.set(SP::G4); 50285101Semaste Reserved.set(SP::O6); 51285101Semaste Reserved.set(SP::I6); 52285101Semaste Reserved.set(SP::I7); 53285101Semaste Reserved.set(SP::G0); 54285101Semaste Reserved.set(SP::G5); 55285101Semaste Reserved.set(SP::G6); 56285101Semaste Reserved.set(SP::G7); 57285101Semaste return Reserved; 58285101Semaste} 59285101Semaste 60285101Semastevoid SparcRegisterInfo:: 61285101SemasteeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 62285101Semaste MachineBasicBlock::iterator I) const { 63285101Semaste MachineInstr &MI = *I; 64285101Semaste DebugLoc dl = MI.getDebugLoc(); 65285101Semaste int Size = MI.getOperand(0).getImm(); 66285101Semaste if (MI.getOpcode() == SP::ADJCALLSTACKDOWN) 67285101Semaste Size = -Size; 68285101Semaste if (Size) 69285101Semaste BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size); 70285101Semaste MBB.erase(I); 71285101Semaste} 72285101Semaste 73285101Semastevoid 74285101SemasteSparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 75285101Semaste int SPAdj, RegScavenger *RS) const { 76285101Semaste assert(SPAdj == 0 && "Unexpected"); 77285101Semaste 78285101Semaste unsigned i = 0; 79285101Semaste MachineInstr &MI = *II; 80285101Semaste DebugLoc dl = MI.getDebugLoc(); 81285101Semaste while (!MI.getOperand(i).isFI()) { 82285101Semaste ++i; 83285101Semaste assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 84285101Semaste } 85285101Semaste 86285101Semaste int FrameIndex = MI.getOperand(i).getIndex(); 87285101Semaste 88285101Semaste // Addressable stack objects are accessed using neg. offsets from %fp 89285101Semaste MachineFunction &MF = *MI.getParent()->getParent(); 90285101Semaste int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 91285101Semaste MI.getOperand(i+1).getImm(); 92285101Semaste 93285101Semaste // Replace frame index with a frame pointer reference. 94285101Semaste if (Offset >= -4096 && Offset <= 4095) { 95285101Semaste // If the offset is small enough to fit in the immediate field, directly 96285101Semaste // encode it. 97285101Semaste MI.getOperand(i).ChangeToRegister(SP::I6, false); 98285101Semaste MI.getOperand(i+1).ChangeToImmediate(Offset); 99285101Semaste } else { 100285101Semaste // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to 101285101Semaste // scavenge a register here instead of reserving G1 all of the time. 102285101Semaste unsigned OffHi = (unsigned)Offset >> 10U; 103285101Semaste BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); 104285101Semaste // Emit G1 = G1 + I6 105285101Semaste BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) 106285101Semaste .addReg(SP::I6); 107285101Semaste // Insert: G1+%lo(offset) into the user. 108285101Semaste MI.getOperand(i).ChangeToRegister(SP::G1, false); 109285101Semaste MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1)); 110285101Semaste } 111285101Semaste} 112285101Semaste 113285101Semastevoid SparcRegisterInfo:: 114285101SemasteprocessFunctionBeforeFrameFinalized(MachineFunction &MF) const {} 115285101Semaste 116285101Semasteunsigned SparcRegisterInfo::getRARegister() const { 117285101Semaste return SP::I7; 118285101Semaste} 119285101Semaste 120285101Semasteunsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 121285101Semaste return SP::I6; 122285101Semaste} 123285101Semaste 124285101Semasteunsigned SparcRegisterInfo::getEHExceptionRegister() const { 125285101Semaste llvm_unreachable("What is the exception register"); 126296417Sdim return 0; 127285101Semaste} 128285101Semaste 129285101Semasteunsigned SparcRegisterInfo::getEHHandlerRegister() const { 130 llvm_unreachable("What is the exception handler register"); 131 return 0; 132} 133 134int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 135 return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 136} 137 138int SparcRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { 139 return SparcGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); 140} 141