SparcRegisterInfo.cpp revision 218893
1//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the SPARC implementation of the TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "Sparc.h" 15#include "SparcRegisterInfo.h" 16#include "SparcSubtarget.h" 17#include "llvm/CodeGen/MachineInstrBuilder.h" 18#include "llvm/CodeGen/MachineFunction.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineLocation.h" 21#include "llvm/Support/ErrorHandling.h" 22#include "llvm/Target/TargetInstrInfo.h" 23#include "llvm/Type.h" 24#include "llvm/ADT/BitVector.h" 25#include "llvm/ADT/STLExtras.h" 26using namespace llvm; 27 28SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st, 29 const TargetInstrInfo &tii) 30 : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), 31 Subtarget(st), TII(tii) { 32} 33 34const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) 35 const { 36 static const unsigned CalleeSavedRegs[] = { 0 }; 37 return CalleeSavedRegs; 38} 39 40BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 41 BitVector Reserved(getNumRegs()); 42 Reserved.set(SP::G2); 43 Reserved.set(SP::G3); 44 Reserved.set(SP::G4); 45 Reserved.set(SP::O6); 46 Reserved.set(SP::I6); 47 Reserved.set(SP::I7); 48 Reserved.set(SP::G0); 49 Reserved.set(SP::G5); 50 Reserved.set(SP::G6); 51 Reserved.set(SP::G7); 52 return Reserved; 53} 54 55void SparcRegisterInfo:: 56eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 57 MachineBasicBlock::iterator I) const { 58 MachineInstr &MI = *I; 59 DebugLoc dl = MI.getDebugLoc(); 60 int Size = MI.getOperand(0).getImm(); 61 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN) 62 Size = -Size; 63 if (Size) 64 BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size); 65 MBB.erase(I); 66} 67 68void 69SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 70 int SPAdj, RegScavenger *RS) const { 71 assert(SPAdj == 0 && "Unexpected"); 72 73 unsigned i = 0; 74 MachineInstr &MI = *II; 75 DebugLoc dl = MI.getDebugLoc(); 76 while (!MI.getOperand(i).isFI()) { 77 ++i; 78 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 79 } 80 81 int FrameIndex = MI.getOperand(i).getIndex(); 82 83 // Addressable stack objects are accessed using neg. offsets from %fp 84 MachineFunction &MF = *MI.getParent()->getParent(); 85 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 86 MI.getOperand(i+1).getImm(); 87 88 // Replace frame index with a frame pointer reference. 89 if (Offset >= -4096 && Offset <= 4095) { 90 // If the offset is small enough to fit in the immediate field, directly 91 // encode it. 92 MI.getOperand(i).ChangeToRegister(SP::I6, false); 93 MI.getOperand(i+1).ChangeToImmediate(Offset); 94 } else { 95 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to 96 // scavenge a register here instead of reserving G1 all of the time. 97 unsigned OffHi = (unsigned)Offset >> 10U; 98 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); 99 // Emit G1 = G1 + I6 100 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) 101 .addReg(SP::I6); 102 // Insert: G1+%lo(offset) into the user. 103 MI.getOperand(i).ChangeToRegister(SP::G1, false); 104 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1)); 105 } 106} 107 108void SparcRegisterInfo:: 109processFunctionBeforeFrameFinalized(MachineFunction &MF) const {} 110 111unsigned SparcRegisterInfo::getRARegister() const { 112 return SP::I7; 113} 114 115unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 116 return SP::I6; 117} 118 119unsigned SparcRegisterInfo::getEHExceptionRegister() const { 120 llvm_unreachable("What is the exception register"); 121 return 0; 122} 123 124unsigned SparcRegisterInfo::getEHHandlerRegister() const { 125 llvm_unreachable("What is the exception handler register"); 126 return 0; 127} 128 129int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 130 return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 131} 132 133#include "SparcGenRegisterInfo.inc" 134 135