SparcInstrInfo.td revision 212904
1//===- SparcInstrInfo.td - Target Description for Sparc Target ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Sparc instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// HasV9 - This predicate is true when the target processor supports V9 25// instructions. Note that the machine may be running in 32-bit mode. 26def HasV9 : Predicate<"Subtarget.isV9()">; 27 28// HasNoV9 - This predicate is true when the target doesn't have V9 29// instructions. Use of this is just a hack for the isel not having proper 30// costs for V8 instructions that are more expensive than their V9 ones. 31def HasNoV9 : Predicate<"!Subtarget.isV9()">; 32 33// HasVIS - This is true when the target processor has VIS extensions. 34def HasVIS : Predicate<"Subtarget.isVIS()">; 35 36// UseDeprecatedInsts - This predicate is true when the target processor is a 37// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 38// to use when appropriate. In either of these cases, the instruction selector 39// will pick deprecated instructions. 40def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 41 42//===----------------------------------------------------------------------===// 43// Instruction Pattern Stuff 44//===----------------------------------------------------------------------===// 45 46def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>; 47 48def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>; 49 50def LO10 : SDNodeXForm<imm, [{ 51 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, 52 MVT::i32); 53}]>; 54 55def HI22 : SDNodeXForm<imm, [{ 56 // Transformation function: shift the immediate value down into the low bits. 57 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32); 58}]>; 59 60def SETHIimm : PatLeaf<(imm), [{ 61 return (((unsigned)N->getZExtValue() >> 10) << 10) == 62 (unsigned)N->getZExtValue(); 63}], HI22>; 64 65// Addressing modes. 66def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>; 67def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>; 68 69// Address operands 70def MEMrr : Operand<i32> { 71 let PrintMethod = "printMemOperand"; 72 let MIOperandInfo = (ops IntRegs, IntRegs); 73} 74def MEMri : Operand<i32> { 75 let PrintMethod = "printMemOperand"; 76 let MIOperandInfo = (ops IntRegs, i32imm); 77} 78 79// Branch targets have OtherVT type. 80def brtarget : Operand<OtherVT>; 81def calltarget : Operand<i32>; 82 83// Operand for printing out a condition code. 84let PrintMethod = "printCCOperand" in 85 def CCOp : Operand<i32>; 86 87def SDTSPcmpfcc : 88SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 89def SDTSPbrcc : 90SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 91def SDTSPselectcc : 92SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 93def SDTSPFTOI : 94SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 95def SDTSPITOF : 96SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 97 98def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>; 99def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutFlag]>; 100def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>; 101def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>; 102 103def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 104def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 105 106def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 107def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 108 109def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInFlag]>; 110def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>; 111 112// These are target-independent nodes, but have target-specific formats. 113def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 114def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 115 SDTCisVT<1, i32> ]>; 116 117def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 118 [SDNPHasChain, SDNPOutFlag]>; 119def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 120 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 121 122def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 123def call : SDNode<"SPISD::CALL", SDT_SPCall, 124 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 125 126def retflag : SDNode<"SPISD::RET_FLAG", SDTNone, 127 [SDNPHasChain, SDNPOptInFlag]>; 128 129def getPCX : Operand<i32> { 130 let PrintMethod = "printGetPCX"; 131} 132 133//===----------------------------------------------------------------------===// 134// SPARC Flag Conditions 135//===----------------------------------------------------------------------===// 136 137// Note that these values must be kept in sync with the CCOp::CondCode enum 138// values. 139class ICC_VAL<int N> : PatLeaf<(i32 N)>; 140def ICC_NE : ICC_VAL< 9>; // Not Equal 141def ICC_E : ICC_VAL< 1>; // Equal 142def ICC_G : ICC_VAL<10>; // Greater 143def ICC_LE : ICC_VAL< 2>; // Less or Equal 144def ICC_GE : ICC_VAL<11>; // Greater or Equal 145def ICC_L : ICC_VAL< 3>; // Less 146def ICC_GU : ICC_VAL<12>; // Greater Unsigned 147def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 148def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 149def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 150def ICC_POS : ICC_VAL<14>; // Positive 151def ICC_NEG : ICC_VAL< 6>; // Negative 152def ICC_VC : ICC_VAL<15>; // Overflow Clear 153def ICC_VS : ICC_VAL< 7>; // Overflow Set 154 155class FCC_VAL<int N> : PatLeaf<(i32 N)>; 156def FCC_U : FCC_VAL<23>; // Unordered 157def FCC_G : FCC_VAL<22>; // Greater 158def FCC_UG : FCC_VAL<21>; // Unordered or Greater 159def FCC_L : FCC_VAL<20>; // Less 160def FCC_UL : FCC_VAL<19>; // Unordered or Less 161def FCC_LG : FCC_VAL<18>; // Less or Greater 162def FCC_NE : FCC_VAL<17>; // Not Equal 163def FCC_E : FCC_VAL<25>; // Equal 164def FCC_UE : FCC_VAL<24>; // Unordered or Equal 165def FCC_GE : FCC_VAL<25>; // Greater or Equal 166def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 167def FCC_LE : FCC_VAL<27>; // Less or Equal 168def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 169def FCC_O : FCC_VAL<29>; // Ordered 170 171//===----------------------------------------------------------------------===// 172// Instruction Class Templates 173//===----------------------------------------------------------------------===// 174 175/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 176multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { 177 def rr : F3_1<2, Op3Val, 178 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 179 !strconcat(OpcStr, " $b, $c, $dst"), 180 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>; 181 def ri : F3_2<2, Op3Val, 182 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 183 !strconcat(OpcStr, " $b, $c, $dst"), 184 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>; 185} 186 187/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 188/// pattern. 189multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 190 def rr : F3_1<2, Op3Val, 191 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 192 !strconcat(OpcStr, " $b, $c, $dst"), []>; 193 def ri : F3_2<2, Op3Val, 194 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 195 !strconcat(OpcStr, " $b, $c, $dst"), []>; 196} 197 198//===----------------------------------------------------------------------===// 199// Instructions 200//===----------------------------------------------------------------------===// 201 202// Pseudo instructions. 203class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 204 : InstSP<outs, ins, asmstr, pattern>; 205 206// GETPCX for PIC 207let Defs = [O7], Uses = [O7] in { 208 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >; 209} 210 211let Defs = [O6], Uses = [O6] in { 212def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 213 "!ADJCALLSTACKDOWN $amt", 214 [(callseq_start timm:$amt)]>; 215def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 216 "!ADJCALLSTACKUP $amt1", 217 [(callseq_end timm:$amt1, timm:$amt2)]>; 218} 219 220// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 221// fpmover pass. 222let Predicates = [HasNoV9] in { // Only emit these in V8 mode. 223 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 224 "!FpMOVD $src, $dst", []>; 225 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 226 "!FpNEGD $src, $dst", 227 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 228 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 229 "!FpABSD $src, $dst", 230 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 231} 232 233// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 234// instruction selection into a branch sequence. This has to handle all 235// permutations of selection between i32/f32/f64 on ICC and FCC. 236let usesCustomInserter = 1 in { // Expanded after instruction selection. 237 def SELECT_CC_Int_ICC 238 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 239 "; SELECT_CC_Int_ICC PSEUDO!", 240 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F, 241 imm:$Cond))]>; 242 def SELECT_CC_Int_FCC 243 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 244 "; SELECT_CC_Int_FCC PSEUDO!", 245 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F, 246 imm:$Cond))]>; 247 def SELECT_CC_FP_ICC 248 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 249 "; SELECT_CC_FP_ICC PSEUDO!", 250 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F, 251 imm:$Cond))]>; 252 def SELECT_CC_FP_FCC 253 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 254 "; SELECT_CC_FP_FCC PSEUDO!", 255 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F, 256 imm:$Cond))]>; 257 def SELECT_CC_DFP_ICC 258 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 259 "; SELECT_CC_DFP_ICC PSEUDO!", 260 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F, 261 imm:$Cond))]>; 262 def SELECT_CC_DFP_FCC 263 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 264 "; SELECT_CC_DFP_FCC PSEUDO!", 265 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F, 266 imm:$Cond))]>; 267} 268 269 270// Section A.3 - Synthetic Instructions, p. 85 271// special cases of JMPL: 272let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in { 273 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 274 def RETL: F3_2<2, 0b111000, (outs), (ins), "retl", [(retflag)]>; 275} 276 277// Section B.1 - Load Integer Instructions, p. 90 278def LDSBrr : F3_1<3, 0b001001, 279 (outs IntRegs:$dst), (ins MEMrr:$addr), 280 "ldsb [$addr], $dst", 281 [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>; 282def LDSBri : F3_2<3, 0b001001, 283 (outs IntRegs:$dst), (ins MEMri:$addr), 284 "ldsb [$addr], $dst", 285 [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>; 286def LDSHrr : F3_1<3, 0b001010, 287 (outs IntRegs:$dst), (ins MEMrr:$addr), 288 "ldsh [$addr], $dst", 289 [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>; 290def LDSHri : F3_2<3, 0b001010, 291 (outs IntRegs:$dst), (ins MEMri:$addr), 292 "ldsh [$addr], $dst", 293 [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>; 294def LDUBrr : F3_1<3, 0b000001, 295 (outs IntRegs:$dst), (ins MEMrr:$addr), 296 "ldub [$addr], $dst", 297 [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>; 298def LDUBri : F3_2<3, 0b000001, 299 (outs IntRegs:$dst), (ins MEMri:$addr), 300 "ldub [$addr], $dst", 301 [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>; 302def LDUHrr : F3_1<3, 0b000010, 303 (outs IntRegs:$dst), (ins MEMrr:$addr), 304 "lduh [$addr], $dst", 305 [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>; 306def LDUHri : F3_2<3, 0b000010, 307 (outs IntRegs:$dst), (ins MEMri:$addr), 308 "lduh [$addr], $dst", 309 [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>; 310def LDrr : F3_1<3, 0b000000, 311 (outs IntRegs:$dst), (ins MEMrr:$addr), 312 "ld [$addr], $dst", 313 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 314def LDri : F3_2<3, 0b000000, 315 (outs IntRegs:$dst), (ins MEMri:$addr), 316 "ld [$addr], $dst", 317 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 318 319// Section B.2 - Load Floating-point Instructions, p. 92 320def LDFrr : F3_1<3, 0b100000, 321 (outs FPRegs:$dst), (ins MEMrr:$addr), 322 "ld [$addr], $dst", 323 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 324def LDFri : F3_2<3, 0b100000, 325 (outs FPRegs:$dst), (ins MEMri:$addr), 326 "ld [$addr], $dst", 327 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 328def LDDFrr : F3_1<3, 0b100011, 329 (outs DFPRegs:$dst), (ins MEMrr:$addr), 330 "ldd [$addr], $dst", 331 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 332def LDDFri : F3_2<3, 0b100011, 333 (outs DFPRegs:$dst), (ins MEMri:$addr), 334 "ldd [$addr], $dst", 335 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 336 337// Section B.4 - Store Integer Instructions, p. 95 338def STBrr : F3_1<3, 0b000101, 339 (outs), (ins MEMrr:$addr, IntRegs:$src), 340 "stb $src, [$addr]", 341 [(truncstorei8 IntRegs:$src, ADDRrr:$addr)]>; 342def STBri : F3_2<3, 0b000101, 343 (outs), (ins MEMri:$addr, IntRegs:$src), 344 "stb $src, [$addr]", 345 [(truncstorei8 IntRegs:$src, ADDRri:$addr)]>; 346def STHrr : F3_1<3, 0b000110, 347 (outs), (ins MEMrr:$addr, IntRegs:$src), 348 "sth $src, [$addr]", 349 [(truncstorei16 IntRegs:$src, ADDRrr:$addr)]>; 350def STHri : F3_2<3, 0b000110, 351 (outs), (ins MEMri:$addr, IntRegs:$src), 352 "sth $src, [$addr]", 353 [(truncstorei16 IntRegs:$src, ADDRri:$addr)]>; 354def STrr : F3_1<3, 0b000100, 355 (outs), (ins MEMrr:$addr, IntRegs:$src), 356 "st $src, [$addr]", 357 [(store IntRegs:$src, ADDRrr:$addr)]>; 358def STri : F3_2<3, 0b000100, 359 (outs), (ins MEMri:$addr, IntRegs:$src), 360 "st $src, [$addr]", 361 [(store IntRegs:$src, ADDRri:$addr)]>; 362 363// Section B.5 - Store Floating-point Instructions, p. 97 364def STFrr : F3_1<3, 0b100100, 365 (outs), (ins MEMrr:$addr, FPRegs:$src), 366 "st $src, [$addr]", 367 [(store FPRegs:$src, ADDRrr:$addr)]>; 368def STFri : F3_2<3, 0b100100, 369 (outs), (ins MEMri:$addr, FPRegs:$src), 370 "st $src, [$addr]", 371 [(store FPRegs:$src, ADDRri:$addr)]>; 372def STDFrr : F3_1<3, 0b100111, 373 (outs), (ins MEMrr:$addr, DFPRegs:$src), 374 "std $src, [$addr]", 375 [(store DFPRegs:$src, ADDRrr:$addr)]>; 376def STDFri : F3_2<3, 0b100111, 377 (outs), (ins MEMri:$addr, DFPRegs:$src), 378 "std $src, [$addr]", 379 [(store DFPRegs:$src, ADDRri:$addr)]>; 380 381// Section B.9 - SETHI Instruction, p. 104 382def SETHIi: F2_1<0b100, 383 (outs IntRegs:$dst), (ins i32imm:$src), 384 "sethi $src, $dst", 385 [(set IntRegs:$dst, SETHIimm:$src)]>; 386 387// Section B.10 - NOP Instruction, p. 105 388// (It's a special case of SETHI) 389let rd = 0, imm22 = 0 in 390 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 391 392// Section B.11 - Logical Instructions, p. 106 393defm AND : F3_12<"and", 0b000001, and>; 394 395def ANDNrr : F3_1<2, 0b000101, 396 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 397 "andn $b, $c, $dst", 398 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 399def ANDNri : F3_2<2, 0b000101, 400 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 401 "andn $b, $c, $dst", []>; 402 403defm OR : F3_12<"or", 0b000010, or>; 404 405def ORNrr : F3_1<2, 0b000110, 406 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 407 "orn $b, $c, $dst", 408 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 409def ORNri : F3_2<2, 0b000110, 410 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 411 "orn $b, $c, $dst", []>; 412defm XOR : F3_12<"xor", 0b000011, xor>; 413 414def XNORrr : F3_1<2, 0b000111, 415 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 416 "xnor $b, $c, $dst", 417 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>; 418def XNORri : F3_2<2, 0b000111, 419 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 420 "xnor $b, $c, $dst", []>; 421 422// Section B.12 - Shift Instructions, p. 107 423defm SLL : F3_12<"sll", 0b100101, shl>; 424defm SRL : F3_12<"srl", 0b100110, srl>; 425defm SRA : F3_12<"sra", 0b100111, sra>; 426 427// Section B.13 - Add Instructions, p. 108 428defm ADD : F3_12<"add", 0b000000, add>; 429 430// "LEA" forms of add (patterns to make tblgen happy) 431def LEA_ADDri : F3_2<2, 0b000000, 432 (outs IntRegs:$dst), (ins MEMri:$addr), 433 "add ${addr:arith}, $dst", 434 [(set IntRegs:$dst, ADDRri:$addr)]>; 435 436let Defs = [ICC] in 437 defm ADDCC : F3_12<"addcc", 0b010000, addc>; 438 439defm ADDX : F3_12<"addx", 0b001000, adde>; 440 441// Section B.15 - Subtract Instructions, p. 110 442defm SUB : F3_12 <"sub" , 0b000100, sub>; 443defm SUBX : F3_12 <"subx" , 0b001100, sube>; 444 445let Defs = [ICC] in { 446 defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>; 447 448 def SUBXCCrr: F3_1<2, 0b011100, 449 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 450 "subxcc $b, $c, $dst", []>; 451} 452 453// Section B.18 - Multiply Instructions, p. 113 454defm UMUL : F3_12np<"umul", 0b001010>; 455defm SMUL : F3_12 <"smul", 0b001011, mul>; 456 457 458// Section B.19 - Divide Instructions, p. 115 459defm UDIV : F3_12np<"udiv", 0b001110>; 460defm SDIV : F3_12np<"sdiv", 0b001111>; 461 462// Section B.20 - SAVE and RESTORE, p. 117 463defm SAVE : F3_12np<"save" , 0b111100>; 464defm RESTORE : F3_12np<"restore", 0b111101>; 465 466// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 467 468// conditional branch class: 469class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 470 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> { 471 let isBranch = 1; 472 let isTerminator = 1; 473 let hasDelaySlot = 1; 474} 475 476let isBarrier = 1 in 477 def BA : BranchSP<0b1000, (ins brtarget:$dst), 478 "ba $dst", 479 [(br bb:$dst)]>; 480 481// FIXME: the encoding for the JIT should look at the condition field. 482let Uses = [ICC] in 483 def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc), 484 "b$cc $dst", 485 [(SPbricc bb:$dst, imm:$cc)]>; 486 487 488// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 489 490// floating-point conditional branch class: 491class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 492 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> { 493 let isBranch = 1; 494 let isTerminator = 1; 495 let hasDelaySlot = 1; 496} 497 498// FIXME: the encoding for the JIT should look at the condition field. 499let Uses = [FCC] in 500 def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc), 501 "fb$cc $dst", 502 [(SPbrfcc bb:$dst, imm:$cc)]>; 503 504 505// Section B.24 - Call and Link Instruction, p. 125 506// This is the only Format 1 instruction 507let Uses = [O0, O1, O2, O3, O4, O5], 508 hasDelaySlot = 1, isCall = 1, 509 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 510 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { 511 def CALL : InstSP<(outs), (ins calltarget:$dst), 512 "call $dst", []> { 513 bits<30> disp; 514 let op = 1; 515 let Inst{29-0} = disp; 516 } 517 518 // indirect calls 519 def JMPLrr : F3_1<2, 0b111000, 520 (outs), (ins MEMrr:$ptr), 521 "call $ptr", 522 [(call ADDRrr:$ptr)]>; 523 def JMPLri : F3_2<2, 0b111000, 524 (outs), (ins MEMri:$ptr), 525 "call $ptr", 526 [(call ADDRri:$ptr)]>; 527} 528 529// Section B.28 - Read State Register Instructions 530def RDY : F3_1<2, 0b101000, 531 (outs IntRegs:$dst), (ins), 532 "rd %y, $dst", []>; 533 534// Section B.29 - Write State Register Instructions 535def WRYrr : F3_1<2, 0b110000, 536 (outs), (ins IntRegs:$b, IntRegs:$c), 537 "wr $b, $c, %y", []>; 538def WRYri : F3_2<2, 0b110000, 539 (outs), (ins IntRegs:$b, i32imm:$c), 540 "wr $b, $c, %y", []>; 541 542// Convert Integer to Floating-point Instructions, p. 141 543def FITOS : F3_3<2, 0b110100, 0b011000100, 544 (outs FPRegs:$dst), (ins FPRegs:$src), 545 "fitos $src, $dst", 546 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 547def FITOD : F3_3<2, 0b110100, 0b011001000, 548 (outs DFPRegs:$dst), (ins FPRegs:$src), 549 "fitod $src, $dst", 550 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 551 552// Convert Floating-point to Integer Instructions, p. 142 553def FSTOI : F3_3<2, 0b110100, 0b011010001, 554 (outs FPRegs:$dst), (ins FPRegs:$src), 555 "fstoi $src, $dst", 556 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 557def FDTOI : F3_3<2, 0b110100, 0b011010010, 558 (outs FPRegs:$dst), (ins DFPRegs:$src), 559 "fdtoi $src, $dst", 560 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 561 562// Convert between Floating-point Formats Instructions, p. 143 563def FSTOD : F3_3<2, 0b110100, 0b011001001, 564 (outs DFPRegs:$dst), (ins FPRegs:$src), 565 "fstod $src, $dst", 566 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 567def FDTOS : F3_3<2, 0b110100, 0b011000110, 568 (outs FPRegs:$dst), (ins DFPRegs:$src), 569 "fdtos $src, $dst", 570 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 571 572// Floating-point Move Instructions, p. 144 573def FMOVS : F3_3<2, 0b110100, 0b000000001, 574 (outs FPRegs:$dst), (ins FPRegs:$src), 575 "fmovs $src, $dst", []>; 576def FNEGS : F3_3<2, 0b110100, 0b000000101, 577 (outs FPRegs:$dst), (ins FPRegs:$src), 578 "fnegs $src, $dst", 579 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 580def FABSS : F3_3<2, 0b110100, 0b000001001, 581 (outs FPRegs:$dst), (ins FPRegs:$src), 582 "fabss $src, $dst", 583 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 584 585 586// Floating-point Square Root Instructions, p.145 587def FSQRTS : F3_3<2, 0b110100, 0b000101001, 588 (outs FPRegs:$dst), (ins FPRegs:$src), 589 "fsqrts $src, $dst", 590 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 591def FSQRTD : F3_3<2, 0b110100, 0b000101010, 592 (outs DFPRegs:$dst), (ins DFPRegs:$src), 593 "fsqrtd $src, $dst", 594 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 595 596 597 598// Floating-point Add and Subtract Instructions, p. 146 599def FADDS : F3_3<2, 0b110100, 0b001000001, 600 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 601 "fadds $src1, $src2, $dst", 602 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 603def FADDD : F3_3<2, 0b110100, 0b001000010, 604 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 605 "faddd $src1, $src2, $dst", 606 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 607def FSUBS : F3_3<2, 0b110100, 0b001000101, 608 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 609 "fsubs $src1, $src2, $dst", 610 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 611def FSUBD : F3_3<2, 0b110100, 0b001000110, 612 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 613 "fsubd $src1, $src2, $dst", 614 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 615 616// Floating-point Multiply and Divide Instructions, p. 147 617def FMULS : F3_3<2, 0b110100, 0b001001001, 618 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 619 "fmuls $src1, $src2, $dst", 620 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 621def FMULD : F3_3<2, 0b110100, 0b001001010, 622 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 623 "fmuld $src1, $src2, $dst", 624 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 625def FSMULD : F3_3<2, 0b110100, 0b001101001, 626 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 627 "fsmuld $src1, $src2, $dst", 628 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 629 (fextend FPRegs:$src2)))]>; 630def FDIVS : F3_3<2, 0b110100, 0b001001101, 631 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 632 "fdivs $src1, $src2, $dst", 633 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 634def FDIVD : F3_3<2, 0b110100, 0b001001110, 635 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 636 "fdivd $src1, $src2, $dst", 637 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 638 639// Floating-point Compare Instructions, p. 148 640// Note: the 2nd template arg is different for these guys. 641// Note 2: the result of a FCMP is not available until the 2nd cycle 642// after the instr is retired, but there is no interlock. This behavior 643// is modelled with a forced noop after the instruction. 644let Defs = [FCC] in { 645 def FCMPS : F3_3<2, 0b110101, 0b001010001, 646 (outs), (ins FPRegs:$src1, FPRegs:$src2), 647 "fcmps $src1, $src2\n\tnop", 648 [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>; 649 def FCMPD : F3_3<2, 0b110101, 0b001010010, 650 (outs), (ins DFPRegs:$src1, DFPRegs:$src2), 651 "fcmpd $src1, $src2\n\tnop", 652 [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>; 653} 654 655//===----------------------------------------------------------------------===// 656// V9 Instructions 657//===----------------------------------------------------------------------===// 658 659// V9 Conditional Moves. 660let Predicates = [HasV9], Constraints = "$T = $dst" in { 661 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 662 // FIXME: Add instruction encodings for the JIT some day. 663 def MOVICCrr 664 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 665 "mov$cc %icc, $F, $dst", 666 [(set IntRegs:$dst, 667 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 668 def MOVICCri 669 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 670 "mov$cc %icc, $F, $dst", 671 [(set IntRegs:$dst, 672 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>; 673 674 def MOVFCCrr 675 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 676 "mov$cc %fcc0, $F, $dst", 677 [(set IntRegs:$dst, 678 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 679 def MOVFCCri 680 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 681 "mov$cc %fcc0, $F, $dst", 682 [(set IntRegs:$dst, 683 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>; 684 685 def FMOVS_ICC 686 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 687 "fmovs$cc %icc, $F, $dst", 688 [(set FPRegs:$dst, 689 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 690 def FMOVD_ICC 691 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 692 "fmovd$cc %icc, $F, $dst", 693 [(set DFPRegs:$dst, 694 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 695 def FMOVS_FCC 696 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 697 "fmovs$cc %fcc0, $F, $dst", 698 [(set FPRegs:$dst, 699 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 700 def FMOVD_FCC 701 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 702 "fmovd$cc %fcc0, $F, $dst", 703 [(set DFPRegs:$dst, 704 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 705 706} 707 708// Floating-Point Move Instructions, p. 164 of the V9 manual. 709let Predicates = [HasV9] in { 710 def FMOVD : F3_3<2, 0b110100, 0b000000010, 711 (outs DFPRegs:$dst), (ins DFPRegs:$src), 712 "fmovd $src, $dst", []>; 713 def FNEGD : F3_3<2, 0b110100, 0b000000110, 714 (outs DFPRegs:$dst), (ins DFPRegs:$src), 715 "fnegd $src, $dst", 716 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 717 def FABSD : F3_3<2, 0b110100, 0b000001010, 718 (outs DFPRegs:$dst), (ins DFPRegs:$src), 719 "fabsd $src, $dst", 720 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 721} 722 723// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 724// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 725def POPCrr : F3_1<2, 0b101110, 726 (outs IntRegs:$dst), (ins IntRegs:$src), 727 "popc $src, $dst", []>, Requires<[HasV9]>; 728def : Pat<(ctpop IntRegs:$src), 729 (POPCrr (SLLri IntRegs:$src, 0))>; 730 731//===----------------------------------------------------------------------===// 732// Non-Instruction Patterns 733//===----------------------------------------------------------------------===// 734 735// Small immediates. 736def : Pat<(i32 simm13:$val), 737 (ORri G0, imm:$val)>; 738// Arbitrary immediates. 739def : Pat<(i32 imm:$val), 740 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 741 742// subc 743def : Pat<(subc IntRegs:$b, IntRegs:$c), 744 (SUBCCrr IntRegs:$b, IntRegs:$c)>; 745def : Pat<(subc IntRegs:$b, simm13:$val), 746 (SUBCCri IntRegs:$b, imm:$val)>; 747 748// Global addresses, constant pool entries 749def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 750def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; 751def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 752def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>; 753 754// Add reg, lo. This is used when taking the addr of a global/constpool entry. 755def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)), 756 (ADDri IntRegs:$r, tglobaladdr:$in)>; 757def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)), 758 (ADDri IntRegs:$r, tconstpool:$in)>; 759 760// Calls: 761def : Pat<(call tglobaladdr:$dst), 762 (CALL tglobaladdr:$dst)>; 763def : Pat<(call texternalsym:$dst), 764 (CALL texternalsym:$dst)>; 765 766// Map integer extload's to zextloads. 767def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 768def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 769def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 770def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 771def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 772def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 773 774// zextload bool -> zextload byte 775def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 776def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 777