SparcInstrInfo.h revision 218893
1//===- SparcInstrInfo.h - Sparc Instruction Information ---------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Sparc implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef SPARCINSTRUCTIONINFO_H 15#define SPARCINSTRUCTIONINFO_H 16 17#include "llvm/Target/TargetInstrInfo.h" 18#include "SparcRegisterInfo.h" 19 20namespace llvm { 21 22/// SPII - This namespace holds all of the target specific flags that 23/// instruction info tracks. 24/// 25namespace SPII { 26 enum { 27 Pseudo = (1<<0), 28 Load = (1<<1), 29 Store = (1<<2), 30 DelaySlot = (1<<3) 31 }; 32} 33 34class SparcInstrInfo : public TargetInstrInfoImpl { 35 const SparcRegisterInfo RI; 36 const SparcSubtarget& Subtarget; 37public: 38 explicit SparcInstrInfo(SparcSubtarget &ST); 39 40 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 41 /// such, whenever a client has an instance of instruction info, it should 42 /// always be able to get register info as well (through this method). 43 /// 44 virtual const SparcRegisterInfo &getRegisterInfo() const { return RI; } 45 46 /// isLoadFromStackSlot - If the specified machine instruction is a direct 47 /// load from a stack slot, return the virtual or physical register number of 48 /// the destination along with the FrameIndex of the loaded stack slot. If 49 /// not, return 0. This predicate must return 0 if the instruction has 50 /// any side effects other than loading from the stack slot. 51 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 52 int &FrameIndex) const; 53 54 /// isStoreToStackSlot - If the specified machine instruction is a direct 55 /// store to a stack slot, return the virtual or physical register number of 56 /// the source reg along with the FrameIndex of the loaded stack slot. If 57 /// not, return 0. This predicate must return 0 if the instruction has 58 /// any side effects other than storing to the stack slot. 59 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 60 int &FrameIndex) const; 61 62 63 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 64 MachineBasicBlock *&FBB, 65 SmallVectorImpl<MachineOperand> &Cond, 66 bool AllowModify = false) const ; 67 68 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 69 70 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 71 MachineBasicBlock *FBB, 72 const SmallVectorImpl<MachineOperand> &Cond, 73 DebugLoc DL) const; 74 75 virtual void copyPhysReg(MachineBasicBlock &MBB, 76 MachineBasicBlock::iterator I, DebugLoc DL, 77 unsigned DestReg, unsigned SrcReg, 78 bool KillSrc) const; 79 80 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 81 MachineBasicBlock::iterator MBBI, 82 unsigned SrcReg, bool isKill, int FrameIndex, 83 const TargetRegisterClass *RC, 84 const TargetRegisterInfo *TRI) const; 85 86 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 87 MachineBasicBlock::iterator MBBI, 88 unsigned DestReg, int FrameIndex, 89 const TargetRegisterClass *RC, 90 const TargetRegisterInfo *TRI) const; 91 92 unsigned getGlobalBaseReg(MachineFunction *MF) const; 93}; 94 95} 96 97#endif 98