SparcInstrFormats.td revision 208954 
1//===- SparcInstrFormats.td - Sparc Instruction Formats ----*- tablegen -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9
10class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
11  field bits<32> Inst;
12
13  let Namespace = "SP";
14
15  bits<2> op;
16  let Inst{31-30} = op;               // Top two bits are the 'op' field
17  
18  dag OutOperandList = outs;
19  dag InOperandList = ins;
20  let AsmString   = asmstr;
21  let Pattern = pattern;
22}
23
24//===----------------------------------------------------------------------===//
25// Format #2 instruction classes in the Sparc
26//===----------------------------------------------------------------------===//
27
28// Format 2 instructions
29class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
30   : InstSP<outs, ins, asmstr, pattern> {
31  bits<3>  op2;
32  bits<22> imm22;
33  let op          = 0;    // op = 0
34  let Inst{24-22} = op2;
35  let Inst{21-0}  = imm22;
36}
37
38// Specific F2 classes: SparcV8 manual, page 44
39//
40class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
41   : F2<outs, ins, asmstr, pattern> {
42  bits<5>  rd;
43
44  let op2         = op2Val;
45
46  let Inst{29-25} = rd;
47}
48
49class F2_2<bits<4> condVal, bits<3> op2Val, dag outs, dag ins, string asmstr, 
50           list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
51  bits<4>   cond;
52  bit       annul = 0;     // currently unused
53
54  let cond        = condVal;
55  let op2         = op2Val;
56
57  let Inst{29}    = annul;
58  let Inst{28-25} = cond;
59}
60
61//===----------------------------------------------------------------------===//
62// Format #3 instruction classes in the Sparc
63//===----------------------------------------------------------------------===//
64
65class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
66    : InstSP<outs, ins, asmstr, pattern> {
67  bits<5> rd;
68  bits<6> op3;
69  bits<5> rs1;
70  let op{1} = 1;   // Op = 2 or 3
71  let Inst{29-25} = rd;
72  let Inst{24-19} = op3;
73  let Inst{18-14} = rs1;
74}
75
76// Specific F3 classes: SparcV8 manual, page 44
77//
78class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
79           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
80  bits<8> asi = 0; // asi not currently used
81  bits<5> rs2;
82
83  let op         = opVal;
84  let op3        = op3val;
85
86  let Inst{13}   = 0;     // i field = 0
87  let Inst{12-5} = asi;   // address space identifier
88  let Inst{4-0}  = rs2;
89}
90
91class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 
92           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
93  bits<13> simm13;
94
95  let op         = opVal;
96  let op3        = op3val;
97
98  let Inst{13}   = 1;     // i field = 1
99  let Inst{12-0} = simm13;
100}
101
102// floating-point
103class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
104           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
105  bits<5> rs2;
106
107  let op         = opVal;
108  let op3        = op3val;
109
110  let Inst{13-5} = opfval;   // fp opcode
111  let Inst{4-0}  = rs2;
112}
113
114
115