SparcInstrFormats.td revision 249423
1234353Sdim//===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===// 2234353Sdim// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7234353Sdim// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sedclass InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { 11193323Sed field bits<32> Inst; 12193323Sed 13193323Sed let Namespace = "SP"; 14193323Sed 15193323Sed bits<2> op; 16193323Sed let Inst{31-30} = op; // Top two bits are the 'op' field 17193323Sed 18193323Sed dag OutOperandList = outs; 19193323Sed dag InOperandList = ins; 20193323Sed let AsmString = asmstr; 21193323Sed let Pattern = pattern; 22193323Sed} 23193323Sed 24193323Sed//===----------------------------------------------------------------------===// 25193323Sed// Format #2 instruction classes in the Sparc 26193323Sed//===----------------------------------------------------------------------===// 27193323Sed 28193323Sed// Format 2 instructions 29193323Sedclass F2<dag outs, dag ins, string asmstr, list<dag> pattern> 30193323Sed : InstSP<outs, ins, asmstr, pattern> { 31193323Sed bits<3> op2; 32193323Sed bits<22> imm22; 33193323Sed let op = 0; // op = 0 34193323Sed let Inst{24-22} = op2; 35193323Sed let Inst{21-0} = imm22; 36193323Sed} 37193323Sed 38193323Sed// Specific F2 classes: SparcV8 manual, page 44 39193323Sed// 40193323Sedclass F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern> 41193323Sed : F2<outs, ins, asmstr, pattern> { 42193323Sed bits<5> rd; 43193323Sed 44193323Sed let op2 = op2Val; 45193323Sed 46193323Sed let Inst{29-25} = rd; 47193323Sed} 48193323Sed 49193323Sedclass F2_2<bits<4> condVal, bits<3> op2Val, dag outs, dag ins, string asmstr, 50193323Sed list<dag> pattern> : F2<outs, ins, asmstr, pattern> { 51193323Sed bits<4> cond; 52193323Sed bit annul = 0; // currently unused 53193323Sed 54193323Sed let cond = condVal; 55193323Sed let op2 = op2Val; 56193323Sed 57193323Sed let Inst{29} = annul; 58193323Sed let Inst{28-25} = cond; 59193323Sed} 60193323Sed 61193323Sed//===----------------------------------------------------------------------===// 62193323Sed// Format #3 instruction classes in the Sparc 63193323Sed//===----------------------------------------------------------------------===// 64193323Sed 65193323Sedclass F3<dag outs, dag ins, string asmstr, list<dag> pattern> 66193323Sed : InstSP<outs, ins, asmstr, pattern> { 67193323Sed bits<5> rd; 68193323Sed bits<6> op3; 69193323Sed bits<5> rs1; 70193323Sed let op{1} = 1; // Op = 2 or 3 71193323Sed let Inst{29-25} = rd; 72193323Sed let Inst{24-19} = op3; 73193323Sed let Inst{18-14} = rs1; 74193323Sed} 75193323Sed 76193323Sed// Specific F3 classes: SparcV8 manual, page 44 77193323Sed// 78193323Sedclass F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 79193323Sed string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 80193323Sed bits<8> asi = 0; // asi not currently used 81193323Sed bits<5> rs2; 82193323Sed 83193323Sed let op = opVal; 84193323Sed let op3 = op3val; 85193323Sed 86193323Sed let Inst{13} = 0; // i field = 0 87193323Sed let Inst{12-5} = asi; // address space identifier 88193323Sed let Inst{4-0} = rs2; 89193323Sed} 90193323Sed 91193323Sedclass F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 92193323Sed string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 93193323Sed bits<13> simm13; 94193323Sed 95193323Sed let op = opVal; 96193323Sed let op3 = op3val; 97193323Sed 98193323Sed let Inst{13} = 1; // i field = 1 99193323Sed let Inst{12-0} = simm13; 100193323Sed} 101193323Sed 102193323Sed// floating-point 103193323Sedclass F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 104193323Sed string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 105193323Sed bits<5> rs2; 106193323Sed 107193323Sed let op = opVal; 108193323Sed let op3 = op3val; 109193323Sed 110193323Sed let Inst{13-5} = opfval; // fp opcode 111193323Sed let Inst{4-0} = rs2; 112193323Sed} 113193323Sed 114249423Sdim// Shift by register rs2. 115249423Sdimclass F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, 116249423Sdim string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 117249423Sdim bit x = xVal; // 1 for 64-bit shifts. 118249423Sdim bits<5> rs2; 119193323Sed 120249423Sdim let op = opVal; 121249423Sdim let op3 = op3val; 122249423Sdim 123249423Sdim let Inst{13} = 0; // i field = 0 124249423Sdim let Inst{12} = x; // extended registers. 125249423Sdim let Inst{4-0} = rs2; 126249423Sdim} 127249423Sdim 128249423Sdim// Shift by immediate. 129249423Sdimclass F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, 130249423Sdim string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 131249423Sdim bit x = xVal; // 1 for 64-bit shifts. 132249423Sdim bits<6> shcnt; // shcnt32 / shcnt64. 133249423Sdim 134249423Sdim let op = opVal; 135249423Sdim let op3 = op3val; 136249423Sdim 137249423Sdim let Inst{13} = 1; // i field = 1 138249423Sdim let Inst{12} = x; // extended registers. 139249423Sdim let Inst{5-0} = shcnt; 140249423Sdim} 141249423Sdim 142249423Sdim// Define rr and ri shift instructions with patterns. 143249423Sdimmulticlass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode, 144249423Sdim ValueType VT, RegisterClass RC> { 145249423Sdim def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, RC:$rs2), 146249423Sdim !strconcat(OpcStr, " $rs, $rs2, $rd"), 147249423Sdim [(set VT:$rd, (OpNode VT:$rs, VT:$rs2))]>; 148249423Sdim def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, unknown:$shcnt), 149249423Sdim !strconcat(OpcStr, " $rs, $shcnt, $rd"), 150249423Sdim [(set VT:$rd, (OpNode VT:$rs, (VT imm:$shcnt)))]>; 151249423Sdim} 152