1234353Sdim//===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===// 2234353Sdim// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7234353Sdim// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10261991Sdimclass InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> 11261991Sdim : Instruction { 12193323Sed field bits<32> Inst; 13193323Sed 14193323Sed let Namespace = "SP"; 15262613Sdim let Size = 4; 16193323Sed 17193323Sed bits<2> op; 18193323Sed let Inst{31-30} = op; // Top two bits are the 'op' field 19261991Sdim 20193323Sed dag OutOperandList = outs; 21193323Sed dag InOperandList = ins; 22193323Sed let AsmString = asmstr; 23193323Sed let Pattern = pattern; 24262613Sdim 25262613Sdim let DecoderNamespace = "Sparc"; 26262613Sdim field bits<32> SoftFail = 0; 27193323Sed} 28193323Sed 29193323Sed//===----------------------------------------------------------------------===// 30193323Sed// Format #2 instruction classes in the Sparc 31193323Sed//===----------------------------------------------------------------------===// 32193323Sed 33193323Sed// Format 2 instructions 34193323Sedclass F2<dag outs, dag ins, string asmstr, list<dag> pattern> 35193323Sed : InstSP<outs, ins, asmstr, pattern> { 36193323Sed bits<3> op2; 37193323Sed bits<22> imm22; 38193323Sed let op = 0; // op = 0 39193323Sed let Inst{24-22} = op2; 40193323Sed let Inst{21-0} = imm22; 41193323Sed} 42193323Sed 43193323Sed// Specific F2 classes: SparcV8 manual, page 44 44193323Sed// 45193323Sedclass F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern> 46193323Sed : F2<outs, ins, asmstr, pattern> { 47193323Sed bits<5> rd; 48193323Sed 49193323Sed let op2 = op2Val; 50193323Sed 51193323Sed let Inst{29-25} = rd; 52193323Sed} 53193323Sed 54276479Sdimclass F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr, 55193323Sed list<dag> pattern> : F2<outs, ins, asmstr, pattern> { 56193323Sed bits<4> cond; 57193323Sed let op2 = op2Val; 58193323Sed 59193323Sed let Inst{29} = annul; 60193323Sed let Inst{28-25} = cond; 61193323Sed} 62193323Sed 63276479Sdimclass F2_3<bits<3> op2Val, bit annul, bit pred, 64276479Sdim dag outs, dag ins, string asmstr, list<dag> pattern> 65276479Sdim : InstSP<outs, ins, asmstr, pattern> { 66276479Sdim bits<2> cc; 67262613Sdim bits<4> cond; 68262613Sdim bits<19> imm19; 69262613Sdim 70262613Sdim let op = 0; // op = 0 71262613Sdim 72262613Sdim let Inst{29} = annul; 73262613Sdim let Inst{28-25} = cond; 74262613Sdim let Inst{24-22} = op2Val; 75276479Sdim let Inst{21-20} = cc; 76262613Sdim let Inst{19} = pred; 77262613Sdim let Inst{18-0} = imm19; 78262613Sdim} 79262613Sdim 80276479Sdimclass F2_4<bits<3> cond, bit annul, bit pred, 81276479Sdim dag outs, dag ins, string asmstr, list<dag> pattern> 82276479Sdim : InstSP<outs, ins, asmstr, pattern> { 83276479Sdim bits<16> imm16; 84276479Sdim bits<5> rs1; 85276479Sdim 86276479Sdim let op = 0; // op = 0 87276479Sdim 88276479Sdim let Inst{29} = annul; 89276479Sdim let Inst{28} = 0; 90276479Sdim let Inst{27-25} = cond; 91276479Sdim let Inst{24-22} = 0b011; 92276479Sdim let Inst{21-20} = imm16{15-14}; 93276479Sdim let Inst{19} = pred; 94276479Sdim let Inst{18-14} = rs1; 95276479Sdim let Inst{13-0} = imm16{13-0}; 96276479Sdim} 97276479Sdim 98276479Sdim 99193323Sed//===----------------------------------------------------------------------===// 100193323Sed// Format #3 instruction classes in the Sparc 101193323Sed//===----------------------------------------------------------------------===// 102193323Sed 103193323Sedclass F3<dag outs, dag ins, string asmstr, list<dag> pattern> 104193323Sed : InstSP<outs, ins, asmstr, pattern> { 105193323Sed bits<5> rd; 106193323Sed bits<6> op3; 107193323Sed bits<5> rs1; 108193323Sed let op{1} = 1; // Op = 2 or 3 109193323Sed let Inst{29-25} = rd; 110193323Sed let Inst{24-19} = op3; 111193323Sed let Inst{18-14} = rs1; 112193323Sed} 113193323Sed 114193323Sed// Specific F3 classes: SparcV8 manual, page 44 115193323Sed// 116288943Sdimclass F3_1_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 117193323Sed string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 118288943Sdim bits<8> asi; 119193323Sed bits<5> rs2; 120193323Sed 121193323Sed let op = opVal; 122193323Sed let op3 = op3val; 123193323Sed 124193323Sed let Inst{13} = 0; // i field = 0 125193323Sed let Inst{12-5} = asi; // address space identifier 126193323Sed let Inst{4-0} = rs2; 127193323Sed} 128193323Sed 129262613Sdimclass F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr, 130288943Sdim list<dag> pattern> : F3_1_asi<opVal, op3val, outs, ins, 131288943Sdim asmstr, pattern> { 132288943Sdim let asi = 0; 133288943Sdim} 134262613Sdim 135261991Sdimclass F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 136193323Sed string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 137193323Sed bits<13> simm13; 138193323Sed 139193323Sed let op = opVal; 140193323Sed let op3 = op3val; 141193323Sed 142193323Sed let Inst{13} = 1; // i field = 1 143193323Sed let Inst{12-0} = simm13; 144193323Sed} 145193323Sed 146193323Sed// floating-point 147193323Sedclass F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 148193323Sed string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 149193323Sed bits<5> rs2; 150193323Sed 151193323Sed let op = opVal; 152193323Sed let op3 = op3val; 153193323Sed 154193323Sed let Inst{13-5} = opfval; // fp opcode 155193323Sed let Inst{4-0} = rs2; 156193323Sed} 157193323Sed 158261991Sdim// floating-point unary operations. 159261991Sdimclass F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 160261991Sdim string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 161261991Sdim bits<5> rs2; 162261991Sdim 163261991Sdim let op = opVal; 164261991Sdim let op3 = op3val; 165261991Sdim let rs1 = 0; 166261991Sdim 167261991Sdim let Inst{13-5} = opfval; // fp opcode 168261991Sdim let Inst{4-0} = rs2; 169261991Sdim} 170261991Sdim 171261991Sdim// floating-point compares. 172261991Sdimclass F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 173261991Sdim string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 174261991Sdim bits<5> rs2; 175261991Sdim 176261991Sdim let op = opVal; 177261991Sdim let op3 = op3val; 178261991Sdim 179261991Sdim let Inst{13-5} = opfval; // fp opcode 180261991Sdim let Inst{4-0} = rs2; 181261991Sdim} 182261991Sdim 183249423Sdim// Shift by register rs2. 184249423Sdimclass F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, 185249423Sdim string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 186249423Sdim bit x = xVal; // 1 for 64-bit shifts. 187249423Sdim bits<5> rs2; 188193323Sed 189249423Sdim let op = opVal; 190249423Sdim let op3 = op3val; 191249423Sdim 192249423Sdim let Inst{13} = 0; // i field = 0 193249423Sdim let Inst{12} = x; // extended registers. 194249423Sdim let Inst{4-0} = rs2; 195249423Sdim} 196249423Sdim 197249423Sdim// Shift by immediate. 198249423Sdimclass F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, 199249423Sdim string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 200249423Sdim bit x = xVal; // 1 for 64-bit shifts. 201249423Sdim bits<6> shcnt; // shcnt32 / shcnt64. 202249423Sdim 203249423Sdim let op = opVal; 204249423Sdim let op3 = op3val; 205249423Sdim 206249423Sdim let Inst{13} = 1; // i field = 1 207249423Sdim let Inst{12} = x; // extended registers. 208249423Sdim let Inst{5-0} = shcnt; 209249423Sdim} 210249423Sdim 211249423Sdim// Define rr and ri shift instructions with patterns. 212249423Sdimmulticlass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode, 213249423Sdim ValueType VT, RegisterClass RC> { 214262613Sdim def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2), 215262613Sdim !strconcat(OpcStr, " $rs1, $rs2, $rd"), 216262613Sdim [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>; 217262613Sdim def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt), 218262613Sdim !strconcat(OpcStr, " $rs1, $shcnt, $rd"), 219262613Sdim [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>; 220249423Sdim} 221261991Sdim 222261991Sdimclass F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern> 223261991Sdim : InstSP<outs, ins, asmstr, pattern> { 224261991Sdim bits<5> rd; 225261991Sdim 226261991Sdim let op = 2; 227261991Sdim let Inst{29-25} = rd; 228261991Sdim let Inst{24-19} = op3; 229261991Sdim} 230261991Sdim 231261991Sdim 232261991Sdimclass F4_1<bits<6> op3, dag outs, dag ins, 233261991Sdim string asmstr, list<dag> pattern> 234261991Sdim : F4<op3, outs, ins, asmstr, pattern> { 235261991Sdim 236276479Sdim bit intcc; 237276479Sdim bits<2> cc; 238261991Sdim bits<4> cond; 239261991Sdim bits<5> rs2; 240261991Sdim 241261991Sdim let Inst{4-0} = rs2; 242276479Sdim let Inst{12-11} = cc; 243261991Sdim let Inst{13} = 0; 244261991Sdim let Inst{17-14} = cond; 245276479Sdim let Inst{18} = intcc; 246261991Sdim 247261991Sdim} 248261991Sdim 249261991Sdimclass F4_2<bits<6> op3, dag outs, dag ins, 250261991Sdim string asmstr, list<dag> pattern> 251261991Sdim : F4<op3, outs, ins, asmstr, pattern> { 252276479Sdim bit intcc; 253276479Sdim bits<2> cc; 254261991Sdim bits<4> cond; 255261991Sdim bits<11> simm11; 256261991Sdim 257261991Sdim let Inst{10-0} = simm11; 258276479Sdim let Inst{12-11} = cc; 259261991Sdim let Inst{13} = 1; 260261991Sdim let Inst{17-14} = cond; 261276479Sdim let Inst{18} = intcc; 262261991Sdim} 263261991Sdim 264261991Sdimclass F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins, 265261991Sdim string asmstr, list<dag> pattern> 266261991Sdim : F4<op3, outs, ins, asmstr, pattern> { 267261991Sdim bits<4> cond; 268276479Sdim bit intcc; 269276479Sdim bits<2> opf_cc; 270261991Sdim bits<5> rs2; 271261991Sdim 272261991Sdim let Inst{18} = 0; 273261991Sdim let Inst{17-14} = cond; 274276479Sdim let Inst{13} = intcc; 275276479Sdim let Inst{12-11} = opf_cc; 276261991Sdim let Inst{10-5} = opf_low; 277261991Sdim let Inst{4-0} = rs2; 278261991Sdim} 279276479Sdim 280276479Sdimclass F4_4r<bits<6> op3, bits<5> opf_low, bits<3> rcond, dag outs, dag ins, 281276479Sdim string asmstr, list<dag> pattern> 282276479Sdim : F4<op3, outs, ins, asmstr, pattern> { 283276479Sdim bits <5> rs1; 284276479Sdim bits <5> rs2; 285276479Sdim let Inst{18-14} = rs1; 286276479Sdim let Inst{13} = 0; // IsImm 287276479Sdim let Inst{12-10} = rcond; 288276479Sdim let Inst{9-5} = opf_low; 289276479Sdim let Inst{4-0} = rs2; 290276479Sdim} 291276479Sdim 292276479Sdim 293276479Sdimclass F4_4i<bits<6> op3, bits<3> rcond, dag outs, dag ins, 294276479Sdim string asmstr, list<dag> pattern> 295276479Sdim : F4<op3, outs, ins, asmstr, pattern> { 296276479Sdim bits<5> rs1; 297276479Sdim bits<10> simm10; 298276479Sdim let Inst{18-14} = rs1; 299276479Sdim let Inst{13} = 1; // IsImm 300276479Sdim let Inst{12-10} = rcond; 301276479Sdim let Inst{9-0} = simm10; 302276479Sdim} 303276479Sdim 304276479Sdim 305276479Sdimclass TRAPSP<bits<6> op3Val, bit isimm, dag outs, dag ins, string asmstr, 306276479Sdim list<dag> pattern>: F3<outs, ins, asmstr, pattern> { 307276479Sdim 308276479Sdim bits<4> cond; 309276479Sdim bits<2> cc; 310276479Sdim 311276479Sdim let op = 0b10; 312276479Sdim let rd{4} = 0; 313276479Sdim let rd{3-0} = cond; 314276479Sdim let op3 = op3Val; 315276479Sdim let Inst{13} = isimm; 316276479Sdim let Inst{12-11} = cc; 317276479Sdim 318276479Sdim} 319276479Sdim 320276479Sdimclass TRAPSPrr<bits<6> op3Val, dag outs, dag ins, string asmstr, 321276479Sdim list<dag> pattern>: TRAPSP<op3Val, 0, outs, ins, asmstr, pattern> { 322276479Sdim bits<5> rs2; 323276479Sdim 324276479Sdim let Inst{10-5} = 0; 325276479Sdim let Inst{4-0} = rs2; 326276479Sdim} 327276479Sdimclass TRAPSPri<bits<6> op3Val, dag outs, dag ins, string asmstr, 328276479Sdim list<dag> pattern>: TRAPSP<op3Val, 1, outs, ins, asmstr, pattern> { 329276479Sdim bits<8> imm; 330276479Sdim 331276479Sdim let Inst{10-8} = 0; 332276479Sdim let Inst{7-0} = imm; 333276479Sdim} 334288943Sdim 335288943Sdim// Pseudo-instructions for alternate assembly syntax (never used by codegen). 336288943Sdim// These are aliases that require C++ handling to convert to the target 337288943Sdim// instruction, while InstAliases can be handled directly by tblgen. 338288943Sdimclass AsmPseudoInst<dag outs, dag ins, string asm> 339288943Sdim : InstSP<outs, ins, asm, []> { 340288943Sdim let isPseudo = 1; 341288943Sdim} 342