1262261Sdim//===-- SparcInstrAliases.td - Instruction Aliases for Sparc Target -------===// 2262261Sdim// 3262261Sdim// The LLVM Compiler Infrastructure 4262261Sdim// 5262261Sdim// This file is distributed under the University of Illinois Open Source 6262261Sdim// License. See LICENSE.TXT for details. 7262261Sdim// 8262261Sdim//===----------------------------------------------------------------------===// 9262261Sdim// 10262261Sdim// This file contains instruction aliases for Sparc. 11262261Sdim//===----------------------------------------------------------------------===// 12262261Sdim 13262261Sdim// Instruction aliases for conditional moves. 14262261Sdim 15262261Sdim// mov<cond> <ccreg> rs2, rd 16276479Sdimmulticlass intcond_mov_alias<string cond, int condVal, string ccreg, 17262261Sdim Instruction movrr, Instruction movri, 18262261Sdim Instruction fmovs, Instruction fmovd> { 19262261Sdim 20276479Sdim // mov<cond> (%icc|%xcc), rs2, rd 21262261Sdim def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg), 22262261Sdim ", $rs2, $rd"), 23262261Sdim (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>; 24262261Sdim 25276479Sdim // mov<cond> (%icc|%xcc), simm11, rd 26262261Sdim def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg), 27262261Sdim ", $simm11, $rd"), 28262261Sdim (movri IntRegs:$rd, i32imm:$simm11, condVal)>; 29262261Sdim 30276479Sdim // fmovs<cond> (%icc|%xcc), $rs2, $rd 31262261Sdim def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg), 32262261Sdim ", $rs2, $rd"), 33262261Sdim (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>; 34262261Sdim 35276479Sdim // fmovd<cond> (%icc|%xcc), $rs2, $rd 36262261Sdim def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg), 37262261Sdim ", $rs2, $rd"), 38262261Sdim (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>; 39262261Sdim} 40262261Sdim 41276479Sdim// mov<cond> <ccreg> rs2, rd 42276479Sdimmulticlass fpcond_mov_alias<string cond, int condVal, 43276479Sdim Instruction movrr, Instruction movri, 44276479Sdim Instruction fmovs, Instruction fmovd> { 45262261Sdim 46276479Sdim // mov<cond> %fcc[0-3], rs2, rd 47276479Sdim def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $rs2, $rd"), 48276479Sdim (movrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, condVal)>; 49276479Sdim 50276479Sdim // mov<cond> %fcc[0-3], simm11, rd 51276479Sdim def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $simm11, $rd"), 52276479Sdim (movri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, condVal)>; 53276479Sdim 54276479Sdim // fmovs<cond> %fcc[0-3], $rs2, $rd 55276479Sdim def : InstAlias<!strconcat(!strconcat("fmovs", cond), " $cc, $rs2, $rd"), 56276479Sdim (fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>; 57276479Sdim 58276479Sdim // fmovd<cond> %fcc[0-3], $rs2, $rd 59276479Sdim def : InstAlias<!strconcat(!strconcat("fmovd", cond), " $cc, $rs2, $rd"), 60276479Sdim (fmovd DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, condVal)>; 61276479Sdim} 62276479Sdim 63262261Sdim// Instruction aliases for integer conditional branches and moves. 64262261Sdimmulticlass int_cond_alias<string cond, int condVal> { 65262261Sdim 66262261Sdim // b<cond> $imm 67262261Sdim def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"), 68262261Sdim (BCOND brtarget:$imm, condVal)>; 69262261Sdim 70276479Sdim // b<cond>,a $imm 71276479Sdim def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"), 72276479Sdim (BCONDA brtarget:$imm, condVal)>; 73276479Sdim 74276479Sdim // b<cond> %icc, $imm 75276479Sdim def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"), 76276479Sdim (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>; 77276479Sdim 78276479Sdim // b<cond>,pt %icc, $imm 79276479Sdim def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %icc, $imm"), 80276479Sdim (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>; 81276479Sdim 82276479Sdim // b<cond>,a %icc, $imm 83276479Sdim def : InstAlias<!strconcat(!strconcat("b", cond), ",a %icc, $imm"), 84276479Sdim (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>; 85276479Sdim 86276479Sdim // b<cond>,a,pt %icc, $imm 87276479Sdim def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %icc, $imm"), 88276479Sdim (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>; 89276479Sdim 90276479Sdim // b<cond>,pn %icc, $imm 91276479Sdim def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %icc, $imm"), 92276479Sdim (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>; 93276479Sdim 94276479Sdim // b<cond>,a,pn %icc, $imm 95276479Sdim def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %icc, $imm"), 96276479Sdim (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>; 97276479Sdim 98262261Sdim // b<cond> %xcc, $imm 99262261Sdim def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"), 100262261Sdim (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>; 101262261Sdim 102276479Sdim // b<cond>,pt %xcc, $imm 103276479Sdim def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %xcc, $imm"), 104276479Sdim (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>; 105276479Sdim 106276479Sdim // b<cond>,a %xcc, $imm 107276479Sdim def : InstAlias<!strconcat(!strconcat("b", cond), ",a %xcc, $imm"), 108276479Sdim (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>; 109276479Sdim 110276479Sdim // b<cond>,a,pt %xcc, $imm 111276479Sdim def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %xcc, $imm"), 112276479Sdim (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>; 113276479Sdim 114276479Sdim // b<cond>,pn %xcc, $imm 115276479Sdim def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %xcc, $imm"), 116276479Sdim (BPXCCNT brtarget:$imm, condVal)>, Requires<[Is64Bit]>; 117276479Sdim 118276479Sdim // b<cond>,a,pn %xcc, $imm 119276479Sdim def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %xcc, $imm"), 120276479Sdim (BPXCCANT brtarget:$imm, condVal)>, Requires<[Is64Bit]>; 121276479Sdim 122276479Sdim 123276479Sdim defm : intcond_mov_alias<cond, condVal, " %icc", 124262261Sdim MOVICCrr, MOVICCri, 125262261Sdim FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>; 126262261Sdim 127276479Sdim defm : intcond_mov_alias<cond, condVal, " %xcc", 128262261Sdim MOVXCCrr, MOVXCCri, 129262261Sdim FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>; 130262261Sdim 131262261Sdim // fmovq<cond> (%icc|%xcc), $rs2, $rd 132262261Sdim def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"), 133262261Sdim (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>, 134262261Sdim Requires<[HasV9, HasHardQuad]>; 135262261Sdim def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"), 136262261Sdim (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>, 137262261Sdim Requires<[Is64Bit, HasHardQuad]>; 138262261Sdim 139276479Sdim // t<cond> %icc, rs1 + rs2 140276479Sdim def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $rs2"), 141276479Sdim (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>, 142276479Sdim Requires<[HasV9]>; 143276479Sdim 144276479Sdim // t<cond> %icc, rs => t<cond> %icc, G0 + rs 145276479Sdim def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs2"), 146276479Sdim (TICCrr G0, IntRegs:$rs2, condVal)>, 147276479Sdim Requires<[HasV9]>; 148276479Sdim 149276479Sdim // t<cond> %xcc, rs1 + rs2 150276479Sdim def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $rs2"), 151276479Sdim (TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>, 152276479Sdim Requires<[HasV9]>; 153276479Sdim 154276479Sdim // t<cond> %xcc, rs => t<cond> %xcc, G0 + rs 155276479Sdim def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs2"), 156276479Sdim (TXCCrr G0, IntRegs:$rs2, condVal)>, 157276479Sdim Requires<[HasV9]>; 158276479Sdim 159276479Sdim // t<cond> rs1 + rs2 => t<cond> %icc, rs1 + rs2 160276479Sdim def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"), 161276479Sdim (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>; 162276479Sdim 163276479Sdim // t<cond> rs=> t<cond> %icc, G0 + rs2 164276479Sdim def : InstAlias<!strconcat(!strconcat("t", cond), " $rs2"), 165276479Sdim (TICCrr G0, IntRegs:$rs2, condVal)>; 166276479Sdim 167276479Sdim // t<cond> %icc, rs1 + imm 168276479Sdim def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $imm"), 169276479Sdim (TICCri IntRegs:$rs1, i32imm:$imm, condVal)>, 170276479Sdim Requires<[HasV9]>; 171276479Sdim // t<cond> %icc, imm => t<cond> %icc, G0 + imm 172276479Sdim def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $imm"), 173276479Sdim (TICCri G0, i32imm:$imm, condVal)>, 174276479Sdim Requires<[HasV9]>; 175276479Sdim // t<cond> %xcc, rs1 + imm 176276479Sdim def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $imm"), 177276479Sdim (TXCCri IntRegs:$rs1, i32imm:$imm, condVal)>, 178276479Sdim Requires<[HasV9]>; 179276479Sdim // t<cond> %xcc, imm => t<cond> %xcc, G0 + imm 180276479Sdim def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $imm"), 181276479Sdim (TXCCri G0, i32imm:$imm, condVal)>, 182276479Sdim Requires<[HasV9]>; 183276479Sdim 184276479Sdim // t<cond> rs1 + imm => t<cond> %icc, rs1 + imm 185276479Sdim def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $imm"), 186276479Sdim (TICCri IntRegs:$rs1, i32imm:$imm, condVal)>; 187276479Sdim 188276479Sdim // t<cond> imm => t<cond> %icc, G0 + imm 189276479Sdim def : InstAlias<!strconcat(!strconcat("t", cond), " $imm"), 190276479Sdim (TICCri G0, i32imm:$imm, condVal)>; 191276479Sdim 192262261Sdim} 193262261Sdim 194262261Sdim 195262261Sdim// Instruction aliases for floating point conditional branches and moves. 196262261Sdimmulticlass fp_cond_alias<string cond, int condVal> { 197262261Sdim 198262261Sdim // fb<cond> $imm 199262261Sdim def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"), 200262261Sdim (FBCOND brtarget:$imm, condVal), 0>; 201262261Sdim 202276479Sdim // fb<cond>,a $imm 203276479Sdim def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $imm"), 204276479Sdim (FBCONDA brtarget:$imm, condVal), 0>; 205262261Sdim 206276479Sdim // fb<cond> %fcc0, $imm 207276479Sdim def : InstAlias<!strconcat(!strconcat("fb", cond), " $cc, $imm"), 208276479Sdim (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>, 209276479Sdim Requires<[HasV9]>; 210276479Sdim 211276479Sdim // fb<cond>,pt %fcc0, $imm 212276479Sdim def : InstAlias<!strconcat(!strconcat("fb", cond), ",pt $cc, $imm"), 213276479Sdim (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>, 214276479Sdim Requires<[HasV9]>; 215276479Sdim 216276479Sdim // fb<cond>,a %fcc0, $imm 217276479Sdim def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $cc, $imm"), 218276479Sdim (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>, 219276479Sdim Requires<[HasV9]>; 220276479Sdim 221276479Sdim // fb<cond>,a,pt %fcc0, $imm 222276479Sdim def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pt $cc, $imm"), 223276479Sdim (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>, 224276479Sdim Requires<[HasV9]>; 225276479Sdim 226276479Sdim // fb<cond>,pn %fcc0, $imm 227276479Sdim def : InstAlias<!strconcat(!strconcat("fb", cond), ",pn $cc, $imm"), 228276479Sdim (BPFCCNT brtarget:$imm, condVal, FCCRegs:$cc)>, 229276479Sdim Requires<[HasV9]>; 230276479Sdim 231276479Sdim // fb<cond>,a,pn %fcc0, $imm 232276479Sdim def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pn $cc, $imm"), 233276479Sdim (BPFCCANT brtarget:$imm, condVal, FCCRegs:$cc)>, 234276479Sdim Requires<[HasV9]>; 235276479Sdim 236276479Sdim defm : fpcond_mov_alias<cond, condVal, 237276479Sdim V9MOVFCCrr, V9MOVFCCri, 238276479Sdim V9FMOVS_FCC, V9FMOVD_FCC>, Requires<[HasV9]>; 239276479Sdim 240262261Sdim // fmovq<cond> %fcc0, $rs2, $rd 241276479Sdim def : InstAlias<!strconcat(!strconcat("fmovq", cond), " $cc, $rs2, $rd"), 242276479Sdim (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 243276479Sdim condVal)>, 244262261Sdim Requires<[HasV9, HasHardQuad]>; 245262261Sdim} 246262261Sdim 247262261Sdimdefm : int_cond_alias<"a", 0b1000>; 248288943Sdimdefm : int_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual 249262261Sdimdefm : int_cond_alias<"n", 0b0000>; 250262261Sdimdefm : int_cond_alias<"ne", 0b1001>; 251288943Sdimdefm : int_cond_alias<"nz", 0b1001>; // same as ne 252262261Sdimdefm : int_cond_alias<"e", 0b0001>; 253296417Sdimdefm : int_cond_alias<"eq", 0b0001>; // same as e 254288943Sdimdefm : int_cond_alias<"z", 0b0001>; // same as e 255262261Sdimdefm : int_cond_alias<"g", 0b1010>; 256262261Sdimdefm : int_cond_alias<"le", 0b0010>; 257262261Sdimdefm : int_cond_alias<"ge", 0b1011>; 258262261Sdimdefm : int_cond_alias<"l", 0b0011>; 259262261Sdimdefm : int_cond_alias<"gu", 0b1100>; 260262261Sdimdefm : int_cond_alias<"leu", 0b0100>; 261262261Sdimdefm : int_cond_alias<"cc", 0b1101>; 262288943Sdimdefm : int_cond_alias<"geu", 0b1101>; // same as cc 263262261Sdimdefm : int_cond_alias<"cs", 0b0101>; 264288943Sdimdefm : int_cond_alias<"lu", 0b0101>; // same as cs 265262261Sdimdefm : int_cond_alias<"pos", 0b1110>; 266262261Sdimdefm : int_cond_alias<"neg", 0b0110>; 267262261Sdimdefm : int_cond_alias<"vc", 0b1111>; 268262261Sdimdefm : int_cond_alias<"vs", 0b0111>; 269262261Sdim 270296417Sdimdefm : fp_cond_alias<"a", 0b1000>; 271296417Sdimdefm : fp_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual 272296417Sdimdefm : fp_cond_alias<"n", 0b0000>; 273262261Sdimdefm : fp_cond_alias<"u", 0b0111>; 274262261Sdimdefm : fp_cond_alias<"g", 0b0110>; 275262261Sdimdefm : fp_cond_alias<"ug", 0b0101>; 276262261Sdimdefm : fp_cond_alias<"l", 0b0100>; 277262261Sdimdefm : fp_cond_alias<"ul", 0b0011>; 278262261Sdimdefm : fp_cond_alias<"lg", 0b0010>; 279262261Sdimdefm : fp_cond_alias<"ne", 0b0001>; 280288943Sdimdefm : fp_cond_alias<"nz", 0b0001>; // same as ne 281262261Sdimdefm : fp_cond_alias<"e", 0b1001>; 282288943Sdimdefm : fp_cond_alias<"z", 0b1001>; // same as e 283262261Sdimdefm : fp_cond_alias<"ue", 0b1010>; 284262261Sdimdefm : fp_cond_alias<"ge", 0b1011>; 285262261Sdimdefm : fp_cond_alias<"uge", 0b1100>; 286262261Sdimdefm : fp_cond_alias<"le", 0b1101>; 287262261Sdimdefm : fp_cond_alias<"ule", 0b1110>; 288262261Sdimdefm : fp_cond_alias<"o", 0b1111>; 289262261Sdim 290288943Sdim// Section A.3 Synthetic Instructions 291262261Sdim 292288943Sdim// Most are marked as Emit=0, so that they are not used for disassembly. This is 293288943Sdim// an aesthetic issue, but the chosen policy is to typically prefer using the 294288943Sdim// non-alias form, except for the most obvious and clarifying aliases: cmp, jmp, 295288943Sdim// call, tst, ret, retl. 296288943Sdim 297288943Sdim// Note: cmp is handled in SparcInstrInfo. 298288943Sdim// jmp/call/ret/retl have special case handling for output in 299288943Sdim// SparcInstPrinter.cpp 300288943Sdim 301262261Sdim// jmp addr -> jmpl addr, %g0 302276479Sdimdef : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr), 0>; 303276479Sdimdef : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr), 0>; 304262261Sdim 305262261Sdim// call addr -> jmpl addr, %o7 306276479Sdimdef : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr), 0>; 307276479Sdimdef : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr), 0>; 308262261Sdim 309288943Sdim// tst reg -> orcc %g0, reg, %g0 310288943Sdimdef : InstAlias<"tst $rs2", (ORCCrr G0, IntRegs:$rs2, G0)>; 311262261Sdim 312288943Sdim// ret -> jmpl %i7+8, %g0 (aka RET 8) 313262261Sdimdef : InstAlias<"ret", (RET 8)>; 314262261Sdim 315288943Sdim// retl -> jmpl %o7+8, %g0 (aka RETL 8) 316288943Sdimdef : InstAlias<"retl", (RETL 8)>; 317262261Sdim 318276479Sdim// restore -> restore %g0, %g0, %g0 319276479Sdimdef : InstAlias<"restore", (RESTORErr G0, G0, G0)>; 320276479Sdim 321288943Sdim// save -> restore %g0, %g0, %g0 322288943Sdimdef : InstAlias<"save", (SAVErr G0, G0, G0)>; 323288943Sdim 324288943Sdim// set value, rd 325288943Sdim// (turns into a sequence of sethi+or, depending on the value) 326288943Sdim// def : InstAlias<"set $val, $rd", (ORri IntRegs:$rd, (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 327288943Sdimdef SET : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "set $val, $rd">; 328288943Sdim 329288943Sdim// not rd -> xnor rd, %g0, rd 330288943Sdimdef : InstAlias<"not $rd", (XNORrr IntRegs:$rd, IntRegs:$rd, G0), 0>; 331288943Sdim 332288943Sdim// not reg, rd -> xnor reg, %g0, rd 333288943Sdimdef : InstAlias<"not $rs1, $rd", (XNORrr IntRegs:$rd, IntRegs:$rs1, G0), 0>; 334288943Sdim 335288943Sdim// neg rd -> sub %g0, rd, rd 336288943Sdimdef : InstAlias<"neg $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rd), 0>; 337288943Sdim 338288943Sdim// neg reg, rd -> sub %g0, reg, rd 339288943Sdimdef : InstAlias<"neg $rs2, $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rs2), 0>; 340288943Sdim 341288943Sdim// inc rd -> add rd, 1, rd 342288943Sdimdef : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>; 343288943Sdim 344288943Sdim// inc simm13, rd -> add rd, simm13, rd 345288943Sdimdef : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>; 346288943Sdim 347288943Sdim// inccc rd -> addcc rd, 1, rd 348288943Sdimdef : InstAlias<"inccc $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, 1), 0>; 349288943Sdim 350288943Sdim// inccc simm13, rd -> addcc rd, simm13, rd 351288943Sdimdef : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>; 352288943Sdim 353288943Sdim// dec rd -> sub rd, 1, rd 354288943Sdimdef : InstAlias<"dec $rd", (SUBri IntRegs:$rd, IntRegs:$rd, 1), 0>; 355288943Sdim 356288943Sdim// dec simm13, rd -> sub rd, simm13, rd 357288943Sdimdef : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>; 358288943Sdim 359288943Sdim// deccc rd -> subcc rd, 1, rd 360288943Sdimdef : InstAlias<"deccc $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, 1), 0>; 361288943Sdim 362288943Sdim// deccc simm13, rd -> subcc rd, simm13, rd 363288943Sdimdef : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>; 364288943Sdim 365288943Sdim// btst reg_or_imm, reg -> andcc reg,reg_or_imm,%g0 366288943Sdimdef : InstAlias<"btst $rs2, $rs1", (ANDCCrr G0, IntRegs:$rs1, IntRegs:$rs2), 0>; 367288943Sdimdef : InstAlias<"btst $simm13, $rs1", (ANDCCri G0, IntRegs:$rs1, i32imm:$simm13), 0>; 368288943Sdim 369288943Sdim// bset reg_or_imm, rd -> or rd,reg_or_imm,rd 370288943Sdimdef : InstAlias<"bset $rs2, $rd", (ORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>; 371288943Sdimdef : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>; 372288943Sdim 373288943Sdim// bclr reg_or_imm, rd -> andn rd,reg_or_imm,rd 374288943Sdimdef : InstAlias<"bclr $rs2, $rd", (ANDNrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>; 375288943Sdimdef : InstAlias<"bclr $simm13, $rd", (ANDNri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>; 376288943Sdim 377288943Sdim// btog reg_or_imm, rd -> xor rd,reg_or_imm,rd 378288943Sdimdef : InstAlias<"btog $rs2, $rd", (XORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>; 379288943Sdimdef : InstAlias<"btog $simm13, $rd", (XORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>; 380288943Sdim 381288943Sdim 382288943Sdim// clr rd -> or %g0, %g0, rd 383288943Sdimdef : InstAlias<"clr $rd", (ORrr IntRegs:$rd, G0, G0), 0>; 384288943Sdim 385288943Sdim// clr{b,h,} [addr] -> st{b,h,} %g0, [addr] 386288943Sdimdef : InstAlias<"clrb [$addr]", (STBrr MEMrr:$addr, G0), 0>; 387288943Sdimdef : InstAlias<"clrb [$addr]", (STBri MEMri:$addr, G0), 0>; 388288943Sdimdef : InstAlias<"clrh [$addr]", (STHrr MEMrr:$addr, G0), 0>; 389288943Sdimdef : InstAlias<"clrh [$addr]", (STHri MEMri:$addr, G0), 0>; 390288943Sdimdef : InstAlias<"clr [$addr]", (STrr MEMrr:$addr, G0), 0>; 391288943Sdimdef : InstAlias<"clr [$addr]", (STri MEMri:$addr, G0), 0>; 392288943Sdim 393288943Sdim 394288943Sdim// mov reg_or_imm, rd -> or %g0, reg_or_imm, rd 395288943Sdimdef : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>; 396288943Sdimdef : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>; 397288943Sdim 398288943Sdim// mov specialreg, rd -> rd specialreg, rd 399288943Sdimdef : InstAlias<"mov $asr, $rd", (RDASR IntRegs:$rd, ASRRegs:$asr), 0>; 400288943Sdimdef : InstAlias<"mov %psr, $rd", (RDPSR IntRegs:$rd), 0>; 401288943Sdimdef : InstAlias<"mov %wim, $rd", (RDWIM IntRegs:$rd), 0>; 402288943Sdimdef : InstAlias<"mov %tbr, $rd", (RDTBR IntRegs:$rd), 0>; 403288943Sdim 404288943Sdim// mov reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg 405288943Sdimdef : InstAlias<"mov $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>; 406288943Sdimdef : InstAlias<"mov $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>; 407288943Sdimdef : InstAlias<"mov $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>; 408288943Sdimdef : InstAlias<"mov $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>; 409288943Sdimdef : InstAlias<"mov $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>; 410288943Sdimdef : InstAlias<"mov $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>; 411288943Sdimdef : InstAlias<"mov $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>; 412288943Sdimdef : InstAlias<"mov $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>; 413288943Sdim 414288943Sdim// End of Section A.3 415288943Sdim 416288943Sdim// wr reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg 417288943Sdim// (aka: omit the first arg when it's g0. This is not in the manual, but is 418288943Sdim// supported by gnu and solaris as) 419288943Sdimdef : InstAlias<"wr $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>; 420288943Sdimdef : InstAlias<"wr $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>; 421288943Sdimdef : InstAlias<"wr $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>; 422288943Sdimdef : InstAlias<"wr $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>; 423288943Sdimdef : InstAlias<"wr $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>; 424288943Sdimdef : InstAlias<"wr $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>; 425288943Sdimdef : InstAlias<"wr $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>; 426288943Sdimdef : InstAlias<"wr $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>; 427288943Sdim 428288943Sdim 429288943Sdim// flush -> flush %g0 430288943Sdimdef : InstAlias<"flush", (FLUSH), 0>; 431288943Sdim 432288943Sdim 433296417Sdimdef : MnemonicAlias<"lduw", "ld">, Requires<[HasV9]>; 434296417Sdimdef : MnemonicAlias<"lduwa", "lda">, Requires<[HasV9]>; 435296417Sdim 436276479Sdimdef : MnemonicAlias<"return", "rett">, Requires<[HasV9]>; 437276479Sdim 438276479Sdimdef : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>; 439276479Sdimdef : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>; 440276479Sdim 441276479Sdimdef : MnemonicAlias<"subc", "subx">, Requires<[HasV9]>; 442276479Sdimdef : MnemonicAlias<"subccc", "subxcc">, Requires<[HasV9]>; 443276479Sdim 444276479Sdim 445276479Sdimdef : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>; 446276479Sdimdef : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>; 447276479Sdimdef : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>, 448276479Sdim Requires<[HasHardQuad]>; 449276479Sdim 450276479Sdimdef : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>; 451276479Sdimdef : InstAlias<"fcmped $rs1, $rs2", (V9FCMPED FCC0, DFPRegs:$rs1, 452276479Sdim DFPRegs:$rs2)>; 453276479Sdimdef : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1, 454276479Sdim QFPRegs:$rs2)>, 455276479Sdim Requires<[HasHardQuad]>; 456288943Sdim 457296417Sdim// signx rd -> sra rd, %g0, rd 458296417Sdimdef : InstAlias<"signx $rd", (SRArr IntRegs:$rd, IntRegs:$rd, G0), 0>, Requires<[HasV9]>; 459296417Sdim 460296417Sdim// signx reg, rd -> sra reg, %g0, rd 461296417Sdimdef : InstAlias<"signx $rs1, $rd", (SRArr IntRegs:$rd, IntRegs:$rs1, G0), 0>, Requires<[HasV9]>; 462