PPCTargetMachine.cpp revision 234353
1254721Semaste//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===// 2254721Semaste// 3254721Semaste// The LLVM Compiler Infrastructure 4254721Semaste// 5254721Semaste// This file is distributed under the University of Illinois Open Source 6254721Semaste// License. See LICENSE.TXT for details. 7254721Semaste// 8254721Semaste//===----------------------------------------------------------------------===// 9254721Semaste// 10254721Semaste// Top-level implementation for the PowerPC target. 11254721Semaste// 12254721Semaste//===----------------------------------------------------------------------===// 13254721Semaste 14254721Semaste#include "PPCTargetMachine.h" 15258054Semaste#include "PPC.h" 16254721Semaste#include "llvm/PassManager.h" 17254721Semaste#include "llvm/MC/MCStreamer.h" 18254721Semaste#include "llvm/CodeGen/Passes.h" 19254721Semaste#include "llvm/Target/TargetOptions.h" 20254721Semaste#include "llvm/Support/FormattedStream.h" 21254721Semaste#include "llvm/Support/TargetRegistry.h" 22254721Semasteusing namespace llvm; 23254721Semaste 24254721Semasteextern "C" void LLVMInitializePowerPCTarget() { 25254721Semaste // Register the targets 26254721Semaste RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target); 27254721Semaste RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target); 28254721Semaste} 29254721Semaste 30254721SemastePPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, 31254721Semaste StringRef CPU, StringRef FS, 32254721Semaste const TargetOptions &Options, 33254721Semaste Reloc::Model RM, CodeModel::Model CM, 34254721Semaste CodeGenOpt::Level OL, 35254721Semaste bool is64Bit) 36254721Semaste : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 37254721Semaste Subtarget(TT, CPU, FS, is64Bit), 38254721Semaste DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), 39254721Semaste FrameLowering(Subtarget), JITInfo(*this, is64Bit), 40254721Semaste TLInfo(*this), TSInfo(*this), 41254721Semaste InstrItins(Subtarget.getInstrItineraryData()) { 42254721Semaste 43254721Semaste // The binutils for the BG/P are too old for CFI. 44254721Semaste if (Subtarget.isBGP()) 45254721Semaste setMCUseCFI(false); 46254721Semaste} 47254721Semaste 48254721Semastevoid PPC32TargetMachine::anchor() { } 49254721Semaste 50254721SemastePPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, 51254721Semaste StringRef CPU, StringRef FS, 52254721Semaste const TargetOptions &Options, 53254721Semaste Reloc::Model RM, CodeModel::Model CM, 54254721Semaste CodeGenOpt::Level OL) 55254721Semaste : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { 56254721Semaste} 57254721Semaste 58254721Semastevoid PPC64TargetMachine::anchor() { } 59254721Semaste 60254721SemastePPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT, 61254721Semaste StringRef CPU, StringRef FS, 62254721Semaste const TargetOptions &Options, 63254721Semaste Reloc::Model RM, CodeModel::Model CM, 64254721Semaste CodeGenOpt::Level OL) 65254721Semaste : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { 66254721Semaste} 67254721Semaste 68254721Semaste 69254721Semaste//===----------------------------------------------------------------------===// 70254721Semaste// Pass Pipeline Configuration 71254721Semaste//===----------------------------------------------------------------------===// 72254721Semaste 73254721Semastenamespace { 74254721Semaste/// PPC Code Generator Pass Configuration Options. 75254721Semasteclass PPCPassConfig : public TargetPassConfig { 76254721Semastepublic: 77254721Semaste PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM) 78254721Semaste : TargetPassConfig(TM, PM) {} 79254721Semaste 80254721Semaste PPCTargetMachine &getPPCTargetMachine() const { 81254721Semaste return getTM<PPCTargetMachine>(); 82254721Semaste } 83254721Semaste 84254721Semaste virtual bool addInstSelector(); 85254721Semaste virtual bool addPreEmitPass(); 86254721Semaste}; 87254721Semaste} // namespace 88254721Semaste 89254721SemasteTargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) { 90254721Semaste TargetPassConfig *PassConfig = new PPCPassConfig(this, PM); 91254721Semaste 92254721Semaste // Override this for PowerPC. Tail merging happily breaks up instruction issue 93254721Semaste // groups, which typically degrades performance. 94254721Semaste PassConfig->setEnableTailMerge(false); 95254721Semaste 96254721Semaste return PassConfig; 97254721Semaste} 98254721Semaste 99254721Semastebool PPCPassConfig::addInstSelector() { 100254721Semaste // Install an instruction selector. 101254721Semaste PM.add(createPPCISelDag(getPPCTargetMachine())); 102254721Semaste return false; 103254721Semaste} 104276479Sdim 105254721Semastebool PPCPassConfig::addPreEmitPass() { 106254721Semaste // Must run branch selection immediately preceding the asm printer. 107254721Semaste PM.add(createPPCBranchSelectionPass()); 108254721Semaste return false; 109254721Semaste} 110254721Semaste 111254721Semastebool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, 112254721Semaste JITCodeEmitter &JCE) { 113254721Semaste // FIXME: This should be moved to TargetJITInfo!! 114254721Semaste if (Subtarget.isPPC64()) 115254721Semaste // Temporary workaround for the inability of PPC64 JIT to handle jump 116254721Semaste // tables. 117254721Semaste Options.DisableJumpTables = true; 118254721Semaste 119254721Semaste // Inform the subtarget that we are in JIT mode. FIXME: does this break macho 120254721Semaste // writing? 121254721Semaste Subtarget.SetJITMode(); 122254721Semaste 123254721Semaste // Machine code emitter pass for PowerPC. 124254721Semaste PM.add(createPPCJITCodeEmitterPass(*this, JCE)); 125254721Semaste 126254721Semaste return false; 127254721Semaste} 128254721Semaste