PPCInstrAltivec.td revision 243830
1//===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Altivec extension to the PowerPC instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Altivec transformation functions and pattern fragments. 16// 17 18// Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be 19// of that type. 20def vnot_ppc : PatFrag<(ops node:$in), 21 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>; 22 23def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 24 (vector_shuffle node:$lhs, node:$rhs), [{ 25 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false); 26}]>; 27def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 28 (vector_shuffle node:$lhs, node:$rhs), [{ 29 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false); 30}]>; 31def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 32 (vector_shuffle node:$lhs, node:$rhs), [{ 33 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true); 34}]>; 35def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 36 (vector_shuffle node:$lhs, node:$rhs), [{ 37 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true); 38}]>; 39 40 41def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 42 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 43 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); 44}]>; 45def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 46 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 47 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); 48}]>; 49def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 50 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 51 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); 52}]>; 53def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 54 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 55 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); 56}]>; 57def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 58 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 59 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); 60}]>; 61def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 62 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 63 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); 64}]>; 65 66 67def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 68 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 69 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); 70}]>; 71def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 72 (vector_shuffle node:$lhs, node:$rhs), [{ 73 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true); 74}]>; 75def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 76 (vector_shuffle node:$lhs, node:$rhs), [{ 77 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true); 78}]>; 79def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 80 (vector_shuffle node:$lhs, node:$rhs), [{ 81 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); 82}]>; 83def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 84 (vector_shuffle node:$lhs, node:$rhs), [{ 85 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true); 86}]>; 87def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 88 (vector_shuffle node:$lhs, node:$rhs), [{ 89 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true); 90}]>; 91 92 93def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{ 94 return getI32Imm(PPC::isVSLDOIShuffleMask(N, false)); 95}]>; 96def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 97 (vector_shuffle node:$lhs, node:$rhs), [{ 98 return PPC::isVSLDOIShuffleMask(N, false) != -1; 99}], VSLDOI_get_imm>; 100 101 102/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into 103/// vector_shuffle(X,undef,mask) by the dag combiner. 104def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{ 105 return getI32Imm(PPC::isVSLDOIShuffleMask(N, true)); 106}]>; 107def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 108 (vector_shuffle node:$lhs, node:$rhs), [{ 109 return PPC::isVSLDOIShuffleMask(N, true) != -1; 110}], VSLDOI_unary_get_imm>; 111 112 113// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. 114def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{ 115 return getI32Imm(PPC::getVSPLTImmediate(N, 1)); 116}]>; 117def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 118 (vector_shuffle node:$lhs, node:$rhs), [{ 119 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1); 120}], VSPLTB_get_imm>; 121def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{ 122 return getI32Imm(PPC::getVSPLTImmediate(N, 2)); 123}]>; 124def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 125 (vector_shuffle node:$lhs, node:$rhs), [{ 126 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2); 127}], VSPLTH_get_imm>; 128def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{ 129 return getI32Imm(PPC::getVSPLTImmediate(N, 4)); 130}]>; 131def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 132 (vector_shuffle node:$lhs, node:$rhs), [{ 133 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4); 134}], VSPLTW_get_imm>; 135 136 137// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. 138def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{ 139 return PPC::get_VSPLTI_elt(N, 1, *CurDAG); 140}]>; 141def vecspltisb : PatLeaf<(build_vector), [{ 142 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0; 143}], VSPLTISB_get_imm>; 144 145// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm. 146def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{ 147 return PPC::get_VSPLTI_elt(N, 2, *CurDAG); 148}]>; 149def vecspltish : PatLeaf<(build_vector), [{ 150 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0; 151}], VSPLTISH_get_imm>; 152 153// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm. 154def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{ 155 return PPC::get_VSPLTI_elt(N, 4, *CurDAG); 156}]>; 157def vecspltisw : PatLeaf<(build_vector), [{ 158 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0; 159}], VSPLTISW_get_imm>; 160 161def V_immneg0 : PatLeaf<(build_vector), [{ 162 return PPC::isAllNegativeZeroVector(N); 163}]>; 164 165//===----------------------------------------------------------------------===// 166// Helpers for defining instructions that directly correspond to intrinsics. 167 168// VA1a_Int - A VAForm_1a intrinsic definition. 169class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID> 170 : VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC), 171 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, 172 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>; 173 174// VX1_Int - A VXForm_1 intrinsic definition. 175class VX1_Int<bits<11> xo, string opc, Intrinsic IntID> 176 : VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 177 !strconcat(opc, " $vD, $vA, $vB"), VecFP, 178 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>; 179 180// VX2_Int - A VXForm_2 intrinsic definition. 181class VX2_Int<bits<11> xo, string opc, Intrinsic IntID> 182 : VXForm_2<xo, (outs VRRC:$vD), (ins VRRC:$vB), 183 !strconcat(opc, " $vD, $vB"), VecFP, 184 [(set VRRC:$vD, (IntID VRRC:$vB))]>; 185 186//===----------------------------------------------------------------------===// 187// Instruction Definitions. 188 189def DSS : DSS_Form<822, (outs), 190 (ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), 191 "dss $STRM", LdStLoad /*FIXME*/, []>; 192def DSSALL : DSS_Form<822, (outs), 193 (ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2), 194 "dssall", LdStLoad /*FIXME*/, []>; 195def DST : DSS_Form<342, (outs), 196 (ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 197 "dst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 198def DSTT : DSS_Form<342, (outs), 199 (ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 200 "dstt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 201def DSTST : DSS_Form<374, (outs), 202 (ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 203 "dstst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 204def DSTSTT : DSS_Form<374, (outs), 205 (ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 206 "dststt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 207 208def DST64 : DSS_Form<342, (outs), 209 (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 210 "dst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 211def DSTT64 : DSS_Form<342, (outs), 212 (ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 213 "dstt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 214def DSTST64 : DSS_Form<374, (outs), 215 (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 216 "dstst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 217def DSTSTT64 : DSS_Form<374, (outs), 218 (ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 219 "dststt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 220 221def MFVSCR : VXForm_4<1540, (outs VRRC:$vD), (ins), 222 "mfvscr $vD", LdStStore, 223 [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>; 224def MTVSCR : VXForm_5<1604, (outs), (ins VRRC:$vB), 225 "mtvscr $vB", LdStLoad, 226 [(int_ppc_altivec_mtvscr VRRC:$vB)]>; 227 228let canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads. 229def LVEBX: XForm_1<31, 7, (outs VRRC:$vD), (ins memrr:$src), 230 "lvebx $vD, $src", LdStLoad, 231 [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; 232def LVEHX: XForm_1<31, 39, (outs VRRC:$vD), (ins memrr:$src), 233 "lvehx $vD, $src", LdStLoad, 234 [(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>; 235def LVEWX: XForm_1<31, 71, (outs VRRC:$vD), (ins memrr:$src), 236 "lvewx $vD, $src", LdStLoad, 237 [(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; 238def LVX : XForm_1<31, 103, (outs VRRC:$vD), (ins memrr:$src), 239 "lvx $vD, $src", LdStLoad, 240 [(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; 241def LVXL : XForm_1<31, 359, (outs VRRC:$vD), (ins memrr:$src), 242 "lvxl $vD, $src", LdStLoad, 243 [(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; 244} 245 246def LVSL : XForm_1<31, 6, (outs VRRC:$vD), (ins memrr:$src), 247 "lvsl $vD, $src", LdStLoad, 248 [(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, 249 PPC970_Unit_LSU; 250def LVSR : XForm_1<31, 38, (outs VRRC:$vD), (ins memrr:$src), 251 "lvsr $vD, $src", LdStLoad, 252 [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, 253 PPC970_Unit_LSU; 254 255let PPC970_Unit = 2 in { // Stores. 256def STVEBX: XForm_8<31, 135, (outs), (ins VRRC:$rS, memrr:$dst), 257 "stvebx $rS, $dst", LdStStore, 258 [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>; 259def STVEHX: XForm_8<31, 167, (outs), (ins VRRC:$rS, memrr:$dst), 260 "stvehx $rS, $dst", LdStStore, 261 [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>; 262def STVEWX: XForm_8<31, 199, (outs), (ins VRRC:$rS, memrr:$dst), 263 "stvewx $rS, $dst", LdStStore, 264 [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>; 265def STVX : XForm_8<31, 231, (outs), (ins VRRC:$rS, memrr:$dst), 266 "stvx $rS, $dst", LdStStore, 267 [(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>; 268def STVXL : XForm_8<31, 487, (outs), (ins VRRC:$rS, memrr:$dst), 269 "stvxl $rS, $dst", LdStStore, 270 [(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>; 271} 272 273let PPC970_Unit = 5 in { // VALU Operations. 274// VA-Form instructions. 3-input AltiVec ops. 275def VMADDFP : VAForm_1<46, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB), 276 "vmaddfp $vD, $vA, $vC, $vB", VecFP, 277 [(set VRRC:$vD, (fma VRRC:$vA, VRRC:$vC, VRRC:$vB))]>; 278def VNMSUBFP: VAForm_1<47, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB), 279 "vnmsubfp $vD, $vA, $vC, $vB", VecFP, 280 [(set VRRC:$vD, (fneg (fma VRRC:$vA, VRRC:$vC, 281 (fneg VRRC:$vB))))]>; 282 283def VMHADDSHS : VA1a_Int<32, "vmhaddshs", int_ppc_altivec_vmhaddshs>; 284def VMHRADDSHS : VA1a_Int<33, "vmhraddshs", int_ppc_altivec_vmhraddshs>; 285def VMLADDUHM : VA1a_Int<34, "vmladduhm", int_ppc_altivec_vmladduhm>; 286def VPERM : VA1a_Int<43, "vperm", int_ppc_altivec_vperm>; 287def VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>; 288 289// Shuffles. 290def VSLDOI : VAForm_2<44, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, u5imm:$SH), 291 "vsldoi $vD, $vA, $vB, $SH", VecFP, 292 [(set VRRC:$vD, 293 (vsldoi_shuffle:$SH (v16i8 VRRC:$vA), VRRC:$vB))]>; 294 295// VX-Form instructions. AltiVec arithmetic ops. 296def VADDFP : VXForm_1<10, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 297 "vaddfp $vD, $vA, $vB", VecFP, 298 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>; 299 300def VADDUBM : VXForm_1<0, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 301 "vaddubm $vD, $vA, $vB", VecGeneral, 302 [(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>; 303def VADDUHM : VXForm_1<64, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 304 "vadduhm $vD, $vA, $vB", VecGeneral, 305 [(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>; 306def VADDUWM : VXForm_1<128, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 307 "vadduwm $vD, $vA, $vB", VecGeneral, 308 [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>; 309 310def VADDCUW : VX1_Int<384, "vaddcuw", int_ppc_altivec_vaddcuw>; 311def VADDSBS : VX1_Int<768, "vaddsbs", int_ppc_altivec_vaddsbs>; 312def VADDSHS : VX1_Int<832, "vaddshs", int_ppc_altivec_vaddshs>; 313def VADDSWS : VX1_Int<896, "vaddsws", int_ppc_altivec_vaddsws>; 314def VADDUBS : VX1_Int<512, "vaddubs", int_ppc_altivec_vaddubs>; 315def VADDUHS : VX1_Int<576, "vadduhs", int_ppc_altivec_vadduhs>; 316def VADDUWS : VX1_Int<640, "vadduws", int_ppc_altivec_vadduws>; 317 318 319def VAND : VXForm_1<1028, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 320 "vand $vD, $vA, $vB", VecFP, 321 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>; 322def VANDC : VXForm_1<1092, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 323 "vandc $vD, $vA, $vB", VecFP, 324 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), 325 (vnot_ppc VRRC:$vB)))]>; 326 327def VCFSX : VXForm_1<842, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 328 "vcfsx $vD, $vB, $UIMM", VecFP, 329 [(set VRRC:$vD, 330 (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>; 331def VCFUX : VXForm_1<778, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 332 "vcfux $vD, $vB, $UIMM", VecFP, 333 [(set VRRC:$vD, 334 (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>; 335def VCTSXS : VXForm_1<970, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 336 "vctsxs $vD, $vB, $UIMM", VecFP, 337 [(set VRRC:$vD, 338 (int_ppc_altivec_vctsxs VRRC:$vB, imm:$UIMM))]>; 339def VCTUXS : VXForm_1<906, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 340 "vctuxs $vD, $vB, $UIMM", VecFP, 341 [(set VRRC:$vD, 342 (int_ppc_altivec_vctuxs VRRC:$vB, imm:$UIMM))]>; 343 344// Defines with the UIM field set to 0 for floating-point 345// to integer (fp_to_sint/fp_to_uint) conversions and integer 346// to floating-point (sint_to_fp/uint_to_fp) conversions. 347let VA = 0 in { 348def VCFSX_0 : VXForm_1<842, (outs VRRC:$vD), (ins VRRC:$vB), 349 "vcfsx $vD, $vB, 0", VecFP, 350 [(set VRRC:$vD, 351 (int_ppc_altivec_vcfsx VRRC:$vB, 0))]>; 352def VCTUXS_0 : VXForm_1<906, (outs VRRC:$vD), (ins VRRC:$vB), 353 "vctuxs $vD, $vB, 0", VecFP, 354 [(set VRRC:$vD, 355 (int_ppc_altivec_vctuxs VRRC:$vB, 0))]>; 356def VCFUX_0 : VXForm_1<778, (outs VRRC:$vD), (ins VRRC:$vB), 357 "vcfux $vD, $vB, 0", VecFP, 358 [(set VRRC:$vD, 359 (int_ppc_altivec_vcfux VRRC:$vB, 0))]>; 360def VCTSXS_0 : VXForm_1<970, (outs VRRC:$vD), (ins VRRC:$vB), 361 "vctsxs $vD, $vB, 0", VecFP, 362 [(set VRRC:$vD, 363 (int_ppc_altivec_vctsxs VRRC:$vB, 0))]>; 364} 365def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>; 366def VLOGEFP : VX2_Int<458, "vlogefp", int_ppc_altivec_vlogefp>; 367 368def VAVGSB : VX1_Int<1282, "vavgsb", int_ppc_altivec_vavgsb>; 369def VAVGSH : VX1_Int<1346, "vavgsh", int_ppc_altivec_vavgsh>; 370def VAVGSW : VX1_Int<1410, "vavgsw", int_ppc_altivec_vavgsw>; 371def VAVGUB : VX1_Int<1026, "vavgub", int_ppc_altivec_vavgub>; 372def VAVGUH : VX1_Int<1090, "vavguh", int_ppc_altivec_vavguh>; 373def VAVGUW : VX1_Int<1154, "vavguw", int_ppc_altivec_vavguw>; 374 375def VMAXFP : VX1_Int<1034, "vmaxfp", int_ppc_altivec_vmaxfp>; 376def VMAXSB : VX1_Int< 258, "vmaxsb", int_ppc_altivec_vmaxsb>; 377def VMAXSH : VX1_Int< 322, "vmaxsh", int_ppc_altivec_vmaxsh>; 378def VMAXSW : VX1_Int< 386, "vmaxsw", int_ppc_altivec_vmaxsw>; 379def VMAXUB : VX1_Int< 2, "vmaxub", int_ppc_altivec_vmaxub>; 380def VMAXUH : VX1_Int< 66, "vmaxuh", int_ppc_altivec_vmaxuh>; 381def VMAXUW : VX1_Int< 130, "vmaxuw", int_ppc_altivec_vmaxuw>; 382def VMINFP : VX1_Int<1098, "vminfp", int_ppc_altivec_vminfp>; 383def VMINSB : VX1_Int< 770, "vminsb", int_ppc_altivec_vminsb>; 384def VMINSH : VX1_Int< 834, "vminsh", int_ppc_altivec_vminsh>; 385def VMINSW : VX1_Int< 898, "vminsw", int_ppc_altivec_vminsw>; 386def VMINUB : VX1_Int< 514, "vminub", int_ppc_altivec_vminub>; 387def VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>; 388def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>; 389 390def VMRGHB : VXForm_1< 12, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 391 "vmrghb $vD, $vA, $vB", VecFP, 392 [(set VRRC:$vD, (vmrghb_shuffle VRRC:$vA, VRRC:$vB))]>; 393def VMRGHH : VXForm_1< 76, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 394 "vmrghh $vD, $vA, $vB", VecFP, 395 [(set VRRC:$vD, (vmrghh_shuffle VRRC:$vA, VRRC:$vB))]>; 396def VMRGHW : VXForm_1<140, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 397 "vmrghw $vD, $vA, $vB", VecFP, 398 [(set VRRC:$vD, (vmrghw_shuffle VRRC:$vA, VRRC:$vB))]>; 399def VMRGLB : VXForm_1<268, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 400 "vmrglb $vD, $vA, $vB", VecFP, 401 [(set VRRC:$vD, (vmrglb_shuffle VRRC:$vA, VRRC:$vB))]>; 402def VMRGLH : VXForm_1<332, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 403 "vmrglh $vD, $vA, $vB", VecFP, 404 [(set VRRC:$vD, (vmrglh_shuffle VRRC:$vA, VRRC:$vB))]>; 405def VMRGLW : VXForm_1<396, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 406 "vmrglw $vD, $vA, $vB", VecFP, 407 [(set VRRC:$vD, (vmrglw_shuffle VRRC:$vA, VRRC:$vB))]>; 408 409def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>; 410def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>; 411def VMSUMSHS : VA1a_Int<41, "vmsumshs", int_ppc_altivec_vmsumshs>; 412def VMSUMUBM : VA1a_Int<36, "vmsumubm", int_ppc_altivec_vmsumubm>; 413def VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>; 414def VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>; 415 416def VMULESB : VX1_Int<776, "vmulesb", int_ppc_altivec_vmulesb>; 417def VMULESH : VX1_Int<840, "vmulesh", int_ppc_altivec_vmulesh>; 418def VMULEUB : VX1_Int<520, "vmuleub", int_ppc_altivec_vmuleub>; 419def VMULEUH : VX1_Int<584, "vmuleuh", int_ppc_altivec_vmuleuh>; 420def VMULOSB : VX1_Int<264, "vmulosb", int_ppc_altivec_vmulosb>; 421def VMULOSH : VX1_Int<328, "vmulosh", int_ppc_altivec_vmulosh>; 422def VMULOUB : VX1_Int< 8, "vmuloub", int_ppc_altivec_vmuloub>; 423def VMULOUH : VX1_Int< 72, "vmulouh", int_ppc_altivec_vmulouh>; 424 425def VREFP : VX2_Int<266, "vrefp", int_ppc_altivec_vrefp>; 426def VRFIM : VX2_Int<714, "vrfim", int_ppc_altivec_vrfim>; 427def VRFIN : VX2_Int<522, "vrfin", int_ppc_altivec_vrfin>; 428def VRFIP : VX2_Int<650, "vrfip", int_ppc_altivec_vrfip>; 429def VRFIZ : VX2_Int<586, "vrfiz", int_ppc_altivec_vrfiz>; 430def VRSQRTEFP : VX2_Int<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; 431 432def VSUBCUW : VX1_Int<74, "vsubcuw", int_ppc_altivec_vsubcuw>; 433 434def VSUBFP : VXForm_1<74, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 435 "vsubfp $vD, $vA, $vB", VecGeneral, 436 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>; 437def VSUBUBM : VXForm_1<1024, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 438 "vsububm $vD, $vA, $vB", VecGeneral, 439 [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>; 440def VSUBUHM : VXForm_1<1088, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 441 "vsubuhm $vD, $vA, $vB", VecGeneral, 442 [(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>; 443def VSUBUWM : VXForm_1<1152, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 444 "vsubuwm $vD, $vA, $vB", VecGeneral, 445 [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>; 446 447def VSUBSBS : VX1_Int<1792, "vsubsbs" , int_ppc_altivec_vsubsbs>; 448def VSUBSHS : VX1_Int<1856, "vsubshs" , int_ppc_altivec_vsubshs>; 449def VSUBSWS : VX1_Int<1920, "vsubsws" , int_ppc_altivec_vsubsws>; 450def VSUBUBS : VX1_Int<1536, "vsububs" , int_ppc_altivec_vsububs>; 451def VSUBUHS : VX1_Int<1600, "vsubuhs" , int_ppc_altivec_vsubuhs>; 452def VSUBUWS : VX1_Int<1664, "vsubuws" , int_ppc_altivec_vsubuws>; 453def VSUMSWS : VX1_Int<1928, "vsumsws" , int_ppc_altivec_vsumsws>; 454def VSUM2SWS: VX1_Int<1672, "vsum2sws", int_ppc_altivec_vsum2sws>; 455def VSUM4SBS: VX1_Int<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs>; 456def VSUM4SHS: VX1_Int<1608, "vsum4shs", int_ppc_altivec_vsum4shs>; 457def VSUM4UBS: VX1_Int<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs>; 458 459def VNOR : VXForm_1<1284, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 460 "vnor $vD, $vA, $vB", VecFP, 461 [(set VRRC:$vD, (vnot_ppc (or (v4i32 VRRC:$vA), 462 VRRC:$vB)))]>; 463def VOR : VXForm_1<1156, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 464 "vor $vD, $vA, $vB", VecFP, 465 [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>; 466def VXOR : VXForm_1<1220, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 467 "vxor $vD, $vA, $vB", VecFP, 468 [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>; 469 470def VRLB : VX1_Int< 4, "vrlb", int_ppc_altivec_vrlb>; 471def VRLH : VX1_Int< 68, "vrlh", int_ppc_altivec_vrlh>; 472def VRLW : VX1_Int< 132, "vrlw", int_ppc_altivec_vrlw>; 473 474def VSL : VX1_Int< 452, "vsl" , int_ppc_altivec_vsl >; 475def VSLO : VX1_Int<1036, "vslo", int_ppc_altivec_vslo>; 476def VSLB : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>; 477def VSLH : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>; 478def VSLW : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>; 479 480def VSPLTB : VXForm_1<524, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 481 "vspltb $vD, $vB, $UIMM", VecPerm, 482 [(set VRRC:$vD, 483 (vspltb_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>; 484def VSPLTH : VXForm_1<588, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 485 "vsplth $vD, $vB, $UIMM", VecPerm, 486 [(set VRRC:$vD, 487 (vsplth_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>; 488def VSPLTW : VXForm_1<652, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 489 "vspltw $vD, $vB, $UIMM", VecPerm, 490 [(set VRRC:$vD, 491 (vspltw_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>; 492 493def VSR : VX1_Int< 708, "vsr" , int_ppc_altivec_vsr>; 494def VSRO : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>; 495def VSRAB : VX1_Int< 772, "vsrab", int_ppc_altivec_vsrab>; 496def VSRAH : VX1_Int< 836, "vsrah", int_ppc_altivec_vsrah>; 497def VSRAW : VX1_Int< 900, "vsraw", int_ppc_altivec_vsraw>; 498def VSRB : VX1_Int< 516, "vsrb" , int_ppc_altivec_vsrb>; 499def VSRH : VX1_Int< 580, "vsrh" , int_ppc_altivec_vsrh>; 500def VSRW : VX1_Int< 644, "vsrw" , int_ppc_altivec_vsrw>; 501 502 503def VSPLTISB : VXForm_3<780, (outs VRRC:$vD), (ins s5imm:$SIMM), 504 "vspltisb $vD, $SIMM", VecPerm, 505 [(set VRRC:$vD, (v16i8 vecspltisb:$SIMM))]>; 506def VSPLTISH : VXForm_3<844, (outs VRRC:$vD), (ins s5imm:$SIMM), 507 "vspltish $vD, $SIMM", VecPerm, 508 [(set VRRC:$vD, (v8i16 vecspltish:$SIMM))]>; 509def VSPLTISW : VXForm_3<908, (outs VRRC:$vD), (ins s5imm:$SIMM), 510 "vspltisw $vD, $SIMM", VecPerm, 511 [(set VRRC:$vD, (v4i32 vecspltisw:$SIMM))]>; 512 513// Vector Pack. 514def VPKPX : VX1_Int<782, "vpkpx", int_ppc_altivec_vpkpx>; 515def VPKSHSS : VX1_Int<398, "vpkshss", int_ppc_altivec_vpkshss>; 516def VPKSHUS : VX1_Int<270, "vpkshus", int_ppc_altivec_vpkshus>; 517def VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>; 518def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>; 519def VPKUHUM : VXForm_1<14, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 520 "vpkuhum $vD, $vA, $vB", VecFP, 521 [(set VRRC:$vD, 522 (vpkuhum_shuffle (v16i8 VRRC:$vA), VRRC:$vB))]>; 523def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>; 524def VPKUWUM : VXForm_1<78, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 525 "vpkuwum $vD, $vA, $vB", VecFP, 526 [(set VRRC:$vD, 527 (vpkuwum_shuffle (v16i8 VRRC:$vA), VRRC:$vB))]>; 528def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>; 529 530// Vector Unpack. 531def VUPKHPX : VX2_Int<846, "vupkhpx", int_ppc_altivec_vupkhpx>; 532def VUPKHSB : VX2_Int<526, "vupkhsb", int_ppc_altivec_vupkhsb>; 533def VUPKHSH : VX2_Int<590, "vupkhsh", int_ppc_altivec_vupkhsh>; 534def VUPKLPX : VX2_Int<974, "vupklpx", int_ppc_altivec_vupklpx>; 535def VUPKLSB : VX2_Int<654, "vupklsb", int_ppc_altivec_vupklsb>; 536def VUPKLSH : VX2_Int<718, "vupklsh", int_ppc_altivec_vupklsh>; 537 538 539// Altivec Comparisons. 540 541class VCMP<bits<10> xo, string asmstr, ValueType Ty> 542 : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare, 543 [(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>; 544class VCMPo<bits<10> xo, string asmstr, ValueType Ty> 545 : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare, 546 [(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]> { 547 let Defs = [CR6]; 548 let RC = 1; 549} 550 551// f32 element comparisons.0 552def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; 553def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>; 554def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>; 555def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>; 556def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>; 557def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>; 558def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>; 559def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>; 560 561// i8 element comparisons. 562def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>; 563def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>; 564def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>; 565def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>; 566def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>; 567def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>; 568 569// i16 element comparisons. 570def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>; 571def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>; 572def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>; 573def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>; 574def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>; 575def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>; 576 577// i32 element comparisons. 578def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>; 579def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>; 580def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>; 581def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; 582def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; 583def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; 584 585def V_SET0 : VXForm_setzero<1220, (outs VRRC:$vD), (ins), 586 "vxor $vD, $vD, $vD", VecFP, 587 [(set VRRC:$vD, (v4i32 immAllZerosV))]>; 588} 589 590//===----------------------------------------------------------------------===// 591// Additional Altivec Patterns 592// 593 594// DS* intrinsics 595def : Pat<(int_ppc_altivec_dssall), (DSSALL 1, 0, 0, 0)>; 596def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>; 597 598// * 32-bit 599def : Pat<(int_ppc_altivec_dst GPRC:$rA, GPRC:$rB, imm:$STRM), 600 (DST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>; 601def : Pat<(int_ppc_altivec_dstt GPRC:$rA, GPRC:$rB, imm:$STRM), 602 (DSTT 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>; 603def : Pat<(int_ppc_altivec_dstst GPRC:$rA, GPRC:$rB, imm:$STRM), 604 (DSTST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>; 605def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM), 606 (DSTSTT 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>; 607 608// * 64-bit 609def : Pat<(int_ppc_altivec_dst G8RC:$rA, GPRC:$rB, imm:$STRM), 610 (DST64 0, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>; 611def : Pat<(int_ppc_altivec_dstt G8RC:$rA, GPRC:$rB, imm:$STRM), 612 (DSTT64 1, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>; 613def : Pat<(int_ppc_altivec_dstst G8RC:$rA, GPRC:$rB, imm:$STRM), 614 (DSTST64 0, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>; 615def : Pat<(int_ppc_altivec_dststt G8RC:$rA, GPRC:$rB, imm:$STRM), 616 (DSTSTT64 1, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>; 617 618// Loads. 619def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; 620 621// Stores. 622def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst), 623 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>; 624 625// Bit conversions. 626def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>; 627def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>; 628def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>; 629 630def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>; 631def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>; 632def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>; 633 634def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>; 635def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>; 636def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>; 637 638def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>; 639def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>; 640def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>; 641 642// Shuffles. 643 644// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x) 645def:Pat<(vsldoi_unary_shuffle:$in (v16i8 VRRC:$vA), undef), 646 (VSLDOI VRRC:$vA, VRRC:$vA, (VSLDOI_unary_get_imm VRRC:$in))>; 647def:Pat<(vpkuwum_unary_shuffle (v16i8 VRRC:$vA), undef), 648 (VPKUWUM VRRC:$vA, VRRC:$vA)>; 649def:Pat<(vpkuhum_unary_shuffle (v16i8 VRRC:$vA), undef), 650 (VPKUHUM VRRC:$vA, VRRC:$vA)>; 651 652// Match vmrg*(x,x) 653def:Pat<(vmrglb_unary_shuffle (v16i8 VRRC:$vA), undef), 654 (VMRGLB VRRC:$vA, VRRC:$vA)>; 655def:Pat<(vmrglh_unary_shuffle (v16i8 VRRC:$vA), undef), 656 (VMRGLH VRRC:$vA, VRRC:$vA)>; 657def:Pat<(vmrglw_unary_shuffle (v16i8 VRRC:$vA), undef), 658 (VMRGLW VRRC:$vA, VRRC:$vA)>; 659def:Pat<(vmrghb_unary_shuffle (v16i8 VRRC:$vA), undef), 660 (VMRGHB VRRC:$vA, VRRC:$vA)>; 661def:Pat<(vmrghh_unary_shuffle (v16i8 VRRC:$vA), undef), 662 (VMRGHH VRRC:$vA, VRRC:$vA)>; 663def:Pat<(vmrghw_unary_shuffle (v16i8 VRRC:$vA), undef), 664 (VMRGHW VRRC:$vA, VRRC:$vA)>; 665 666// Logical Operations 667def : Pat<(v4i32 (vnot_ppc VRRC:$vA)), (VNOR VRRC:$vA, VRRC:$vA)>; 668 669def : Pat<(v4i32 (vnot_ppc (or VRRC:$A, VRRC:$B))), 670 (VNOR VRRC:$A, VRRC:$B)>; 671def : Pat<(v4i32 (and VRRC:$A, (vnot_ppc VRRC:$B))), 672 (VANDC VRRC:$A, VRRC:$B)>; 673 674def : Pat<(fmul VRRC:$vA, VRRC:$vB), 675 (VMADDFP VRRC:$vA, VRRC:$vB, (v4i32 (V_SET0)))>; 676 677// Fused multiply add and multiply sub for packed float. These are represented 678// separately from the real instructions above, for operations that must have 679// the additional precision, such as Newton-Rhapson (used by divide, sqrt) 680def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C), 681 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>; 682def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C), 683 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>; 684 685def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C), 686 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>; 687def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C), 688 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>; 689 690def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC), 691 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC)>; 692 693// Vector shifts 694def : Pat<(v16i8 (shl (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))), 695 (v16i8 (VSLB VRRC:$vA, VRRC:$vB))>; 696def : Pat<(v8i16 (shl (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))), 697 (v8i16 (VSLH VRRC:$vA, VRRC:$vB))>; 698def : Pat<(v4i32 (shl (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))), 699 (v4i32 (VSLW VRRC:$vA, VRRC:$vB))>; 700 701def : Pat<(v16i8 (srl (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))), 702 (v16i8 (VSRB VRRC:$vA, VRRC:$vB))>; 703def : Pat<(v8i16 (srl (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))), 704 (v8i16 (VSRH VRRC:$vA, VRRC:$vB))>; 705def : Pat<(v4i32 (srl (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))), 706 (v4i32 (VSRW VRRC:$vA, VRRC:$vB))>; 707 708def : Pat<(v16i8 (sra (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))), 709 (v16i8 (VSRAB VRRC:$vA, VRRC:$vB))>; 710def : Pat<(v8i16 (sra (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))), 711 (v8i16 (VSRAH VRRC:$vA, VRRC:$vB))>; 712def : Pat<(v4i32 (sra (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))), 713 (v4i32 (VSRAW VRRC:$vA, VRRC:$vB))>; 714 715// Float to integer and integer to float conversions 716def : Pat<(v4i32 (fp_to_sint (v4f32 VRRC:$vA))), 717 (VCTSXS_0 VRRC:$vA)>; 718def : Pat<(v4i32 (fp_to_uint (v4f32 VRRC:$vA))), 719 (VCTUXS_0 VRRC:$vA)>; 720def : Pat<(v4f32 (sint_to_fp (v4i32 VRRC:$vA))), 721 (VCFSX_0 VRRC:$vA)>; 722def : Pat<(v4f32 (uint_to_fp (v4i32 VRRC:$vA))), 723 (VCFUX_0 VRRC:$vA)>; 724