PPCInstrAltivec.td revision 204961
1//===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Altivec extension to the PowerPC instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Altivec transformation functions and pattern fragments. 16// 17 18 19def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 20 (vector_shuffle node:$lhs, node:$rhs), [{ 21 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false); 22}]>; 23def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 24 (vector_shuffle node:$lhs, node:$rhs), [{ 25 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false); 26}]>; 27def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 28 (vector_shuffle node:$lhs, node:$rhs), [{ 29 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true); 30}]>; 31def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 32 (vector_shuffle node:$lhs, node:$rhs), [{ 33 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true); 34}]>; 35 36 37def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 38 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 39 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); 40}]>; 41def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 42 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 43 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); 44}]>; 45def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 46 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 47 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); 48}]>; 49def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 50 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 51 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); 52}]>; 53def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 54 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 55 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); 56}]>; 57def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 58 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 59 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); 60}]>; 61 62 63def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 64 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 65 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); 66}]>; 67def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 68 (vector_shuffle node:$lhs, node:$rhs), [{ 69 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true); 70}]>; 71def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 72 (vector_shuffle node:$lhs, node:$rhs), [{ 73 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true); 74}]>; 75def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 76 (vector_shuffle node:$lhs, node:$rhs), [{ 77 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); 78}]>; 79def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 80 (vector_shuffle node:$lhs, node:$rhs), [{ 81 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true); 82}]>; 83def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 84 (vector_shuffle node:$lhs, node:$rhs), [{ 85 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true); 86}]>; 87 88 89def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{ 90 return getI32Imm(PPC::isVSLDOIShuffleMask(N, false)); 91}]>; 92def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 93 (vector_shuffle node:$lhs, node:$rhs), [{ 94 return PPC::isVSLDOIShuffleMask(N, false) != -1; 95}], VSLDOI_get_imm>; 96 97 98/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into 99/// vector_shuffle(X,undef,mask) by the dag combiner. 100def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{ 101 return getI32Imm(PPC::isVSLDOIShuffleMask(N, true)); 102}]>; 103def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 104 (vector_shuffle node:$lhs, node:$rhs), [{ 105 return PPC::isVSLDOIShuffleMask(N, true) != -1; 106}], VSLDOI_unary_get_imm>; 107 108 109// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. 110def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{ 111 return getI32Imm(PPC::getVSPLTImmediate(N, 1)); 112}]>; 113def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 114 (vector_shuffle node:$lhs, node:$rhs), [{ 115 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1); 116}], VSPLTB_get_imm>; 117def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{ 118 return getI32Imm(PPC::getVSPLTImmediate(N, 2)); 119}]>; 120def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 121 (vector_shuffle node:$lhs, node:$rhs), [{ 122 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2); 123}], VSPLTH_get_imm>; 124def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{ 125 return getI32Imm(PPC::getVSPLTImmediate(N, 4)); 126}]>; 127def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 128 (vector_shuffle node:$lhs, node:$rhs), [{ 129 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4); 130}], VSPLTW_get_imm>; 131 132 133// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. 134def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{ 135 return PPC::get_VSPLTI_elt(N, 1, *CurDAG); 136}]>; 137def vecspltisb : PatLeaf<(build_vector), [{ 138 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0; 139}], VSPLTISB_get_imm>; 140 141// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm. 142def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{ 143 return PPC::get_VSPLTI_elt(N, 2, *CurDAG); 144}]>; 145def vecspltish : PatLeaf<(build_vector), [{ 146 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0; 147}], VSPLTISH_get_imm>; 148 149// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm. 150def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{ 151 return PPC::get_VSPLTI_elt(N, 4, *CurDAG); 152}]>; 153def vecspltisw : PatLeaf<(build_vector), [{ 154 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0; 155}], VSPLTISW_get_imm>; 156 157def V_immneg0 : PatLeaf<(build_vector), [{ 158 return PPC::isAllNegativeZeroVector(N); 159}]>; 160 161//===----------------------------------------------------------------------===// 162// Helpers for defining instructions that directly correspond to intrinsics. 163 164// VA1a_Int - A VAForm_1a intrinsic definition. 165class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID> 166 : VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC), 167 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, 168 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>; 169 170// VX1_Int - A VXForm_1 intrinsic definition. 171class VX1_Int<bits<11> xo, string opc, Intrinsic IntID> 172 : VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 173 !strconcat(opc, " $vD, $vA, $vB"), VecFP, 174 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>; 175 176// VX2_Int - A VXForm_2 intrinsic definition. 177class VX2_Int<bits<11> xo, string opc, Intrinsic IntID> 178 : VXForm_2<xo, (outs VRRC:$vD), (ins VRRC:$vB), 179 !strconcat(opc, " $vD, $vB"), VecFP, 180 [(set VRRC:$vD, (IntID VRRC:$vB))]>; 181 182//===----------------------------------------------------------------------===// 183// Instruction Definitions. 184 185def DSS : DSS_Form<822, (outs), 186 (ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), 187 "dss $STRM", LdStGeneral /*FIXME*/, []>; 188def DSSALL : DSS_Form<822, (outs), 189 (ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2), 190 "dssall", LdStGeneral /*FIXME*/, []>; 191def DST : DSS_Form<342, (outs), 192 (ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 193 "dst $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>; 194def DSTT : DSS_Form<342, (outs), 195 (ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 196 "dstt $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>; 197def DSTST : DSS_Form<374, (outs), 198 (ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 199 "dstst $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>; 200def DSTSTT : DSS_Form<374, (outs), 201 (ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 202 "dststt $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>; 203 204def DST64 : DSS_Form<342, (outs), 205 (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 206 "dst $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>; 207def DSTT64 : DSS_Form<342, (outs), 208 (ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 209 "dstt $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>; 210def DSTST64 : DSS_Form<374, (outs), 211 (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 212 "dstst $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>; 213def DSTSTT64 : DSS_Form<374, (outs), 214 (ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 215 "dststt $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>; 216 217def MFVSCR : VXForm_4<1540, (outs VRRC:$vD), (ins), 218 "mfvscr $vD", LdStGeneral, 219 [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>; 220def MTVSCR : VXForm_5<1604, (outs), (ins VRRC:$vB), 221 "mtvscr $vB", LdStGeneral, 222 [(int_ppc_altivec_mtvscr VRRC:$vB)]>; 223 224let canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads. 225def LVEBX: XForm_1<31, 7, (outs VRRC:$vD), (ins memrr:$src), 226 "lvebx $vD, $src", LdStGeneral, 227 [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; 228def LVEHX: XForm_1<31, 39, (outs VRRC:$vD), (ins memrr:$src), 229 "lvehx $vD, $src", LdStGeneral, 230 [(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>; 231def LVEWX: XForm_1<31, 71, (outs VRRC:$vD), (ins memrr:$src), 232 "lvewx $vD, $src", LdStGeneral, 233 [(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; 234def LVX : XForm_1<31, 103, (outs VRRC:$vD), (ins memrr:$src), 235 "lvx $vD, $src", LdStGeneral, 236 [(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; 237def LVXL : XForm_1<31, 359, (outs VRRC:$vD), (ins memrr:$src), 238 "lvxl $vD, $src", LdStGeneral, 239 [(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; 240} 241 242def LVSL : XForm_1<31, 6, (outs VRRC:$vD), (ins memrr:$src), 243 "lvsl $vD, $src", LdStGeneral, 244 [(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, 245 PPC970_Unit_LSU; 246def LVSR : XForm_1<31, 38, (outs VRRC:$vD), (ins memrr:$src), 247 "lvsr $vD, $src", LdStGeneral, 248 [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, 249 PPC970_Unit_LSU; 250 251let PPC970_Unit = 2 in { // Stores. 252def STVEBX: XForm_8<31, 135, (outs), (ins VRRC:$rS, memrr:$dst), 253 "stvebx $rS, $dst", LdStGeneral, 254 [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>; 255def STVEHX: XForm_8<31, 167, (outs), (ins VRRC:$rS, memrr:$dst), 256 "stvehx $rS, $dst", LdStGeneral, 257 [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>; 258def STVEWX: XForm_8<31, 199, (outs), (ins VRRC:$rS, memrr:$dst), 259 "stvewx $rS, $dst", LdStGeneral, 260 [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>; 261def STVX : XForm_8<31, 231, (outs), (ins VRRC:$rS, memrr:$dst), 262 "stvx $rS, $dst", LdStGeneral, 263 [(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>; 264def STVXL : XForm_8<31, 487, (outs), (ins VRRC:$rS, memrr:$dst), 265 "stvxl $rS, $dst", LdStGeneral, 266 [(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>; 267} 268 269let PPC970_Unit = 5 in { // VALU Operations. 270// VA-Form instructions. 3-input AltiVec ops. 271def VMADDFP : VAForm_1<46, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB), 272 "vmaddfp $vD, $vA, $vC, $vB", VecFP, 273 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC), 274 VRRC:$vB))]>, 275 Requires<[FPContractions]>; 276def VNMSUBFP: VAForm_1<47, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB), 277 "vnmsubfp $vD, $vA, $vC, $vB", VecFP, 278 [(set VRRC:$vD, (fsub V_immneg0, 279 (fsub (fmul VRRC:$vA, VRRC:$vC), 280 VRRC:$vB)))]>, 281 Requires<[FPContractions]>; 282 283def VMHADDSHS : VA1a_Int<32, "vmhaddshs", int_ppc_altivec_vmhaddshs>; 284def VMHRADDSHS : VA1a_Int<33, "vmhraddshs", int_ppc_altivec_vmhraddshs>; 285def VMLADDUHM : VA1a_Int<34, "vmladduhm", int_ppc_altivec_vmladduhm>; 286def VPERM : VA1a_Int<43, "vperm", int_ppc_altivec_vperm>; 287def VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>; 288 289// Shuffles. 290def VSLDOI : VAForm_2<44, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, u5imm:$SH), 291 "vsldoi $vD, $vA, $vB, $SH", VecFP, 292 [(set VRRC:$vD, 293 (vsldoi_shuffle:$SH (v16i8 VRRC:$vA), VRRC:$vB))]>; 294 295// VX-Form instructions. AltiVec arithmetic ops. 296def VADDFP : VXForm_1<10, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 297 "vaddfp $vD, $vA, $vB", VecFP, 298 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>; 299 300def VADDUBM : VXForm_1<0, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 301 "vaddubm $vD, $vA, $vB", VecGeneral, 302 [(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>; 303def VADDUHM : VXForm_1<64, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 304 "vadduhm $vD, $vA, $vB", VecGeneral, 305 [(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>; 306def VADDUWM : VXForm_1<128, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 307 "vadduwm $vD, $vA, $vB", VecGeneral, 308 [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>; 309 310def VADDCUW : VX1_Int<384, "vaddcuw", int_ppc_altivec_vaddcuw>; 311def VADDSBS : VX1_Int<768, "vaddsbs", int_ppc_altivec_vaddsbs>; 312def VADDSHS : VX1_Int<832, "vaddshs", int_ppc_altivec_vaddshs>; 313def VADDSWS : VX1_Int<896, "vaddsws", int_ppc_altivec_vaddsws>; 314def VADDUBS : VX1_Int<512, "vaddubs", int_ppc_altivec_vaddubs>; 315def VADDUHS : VX1_Int<576, "vadduhs", int_ppc_altivec_vadduhs>; 316def VADDUWS : VX1_Int<640, "vadduws", int_ppc_altivec_vadduws>; 317 318 319def VAND : VXForm_1<1028, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 320 "vand $vD, $vA, $vB", VecFP, 321 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>; 322def VANDC : VXForm_1<1092, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 323 "vandc $vD, $vA, $vB", VecFP, 324 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), (vnot VRRC:$vB)))]>; 325 326def VCFSX : VXForm_1<842, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 327 "vcfsx $vD, $vB, $UIMM", VecFP, 328 [(set VRRC:$vD, 329 (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>; 330def VCFUX : VXForm_1<778, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 331 "vcfux $vD, $vB, $UIMM", VecFP, 332 [(set VRRC:$vD, 333 (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>; 334def VCTSXS : VXForm_1<970, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 335 "vctsxs $vD, $vB, $UIMM", VecFP, 336 [(set VRRC:$vD, 337 (int_ppc_altivec_vctsxs VRRC:$vB, imm:$UIMM))]>; 338def VCTUXS : VXForm_1<906, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 339 "vctuxs $vD, $vB, $UIMM", VecFP, 340 [(set VRRC:$vD, 341 (int_ppc_altivec_vctuxs VRRC:$vB, imm:$UIMM))]>; 342def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>; 343def VLOGEFP : VX2_Int<458, "vlogefp", int_ppc_altivec_vlogefp>; 344 345def VAVGSB : VX1_Int<1282, "vavgsb", int_ppc_altivec_vavgsb>; 346def VAVGSH : VX1_Int<1346, "vavgsh", int_ppc_altivec_vavgsh>; 347def VAVGSW : VX1_Int<1410, "vavgsw", int_ppc_altivec_vavgsw>; 348def VAVGUB : VX1_Int<1026, "vavgub", int_ppc_altivec_vavgub>; 349def VAVGUH : VX1_Int<1090, "vavguh", int_ppc_altivec_vavguh>; 350def VAVGUW : VX1_Int<1154, "vavguw", int_ppc_altivec_vavguw>; 351 352def VMAXFP : VX1_Int<1034, "vmaxfp", int_ppc_altivec_vmaxfp>; 353def VMAXSB : VX1_Int< 258, "vmaxsb", int_ppc_altivec_vmaxsb>; 354def VMAXSH : VX1_Int< 322, "vmaxsh", int_ppc_altivec_vmaxsh>; 355def VMAXSW : VX1_Int< 386, "vmaxsw", int_ppc_altivec_vmaxsw>; 356def VMAXUB : VX1_Int< 2, "vmaxub", int_ppc_altivec_vmaxub>; 357def VMAXUH : VX1_Int< 66, "vmaxuh", int_ppc_altivec_vmaxuh>; 358def VMAXUW : VX1_Int< 130, "vmaxuw", int_ppc_altivec_vmaxuw>; 359def VMINFP : VX1_Int<1098, "vminfp", int_ppc_altivec_vminfp>; 360def VMINSB : VX1_Int< 770, "vminsb", int_ppc_altivec_vminsb>; 361def VMINSH : VX1_Int< 834, "vminsh", int_ppc_altivec_vminsh>; 362def VMINSW : VX1_Int< 898, "vminsw", int_ppc_altivec_vminsw>; 363def VMINUB : VX1_Int< 514, "vminub", int_ppc_altivec_vminub>; 364def VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>; 365def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>; 366 367def VMRGHB : VXForm_1< 12, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 368 "vmrghb $vD, $vA, $vB", VecFP, 369 [(set VRRC:$vD, (vmrghb_shuffle VRRC:$vA, VRRC:$vB))]>; 370def VMRGHH : VXForm_1< 76, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 371 "vmrghh $vD, $vA, $vB", VecFP, 372 [(set VRRC:$vD, (vmrghh_shuffle VRRC:$vA, VRRC:$vB))]>; 373def VMRGHW : VXForm_1<140, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 374 "vmrghw $vD, $vA, $vB", VecFP, 375 [(set VRRC:$vD, (vmrghw_shuffle VRRC:$vA, VRRC:$vB))]>; 376def VMRGLB : VXForm_1<268, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 377 "vmrglb $vD, $vA, $vB", VecFP, 378 [(set VRRC:$vD, (vmrglb_shuffle VRRC:$vA, VRRC:$vB))]>; 379def VMRGLH : VXForm_1<332, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 380 "vmrglh $vD, $vA, $vB", VecFP, 381 [(set VRRC:$vD, (vmrglh_shuffle VRRC:$vA, VRRC:$vB))]>; 382def VMRGLW : VXForm_1<396, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 383 "vmrglw $vD, $vA, $vB", VecFP, 384 [(set VRRC:$vD, (vmrglw_shuffle VRRC:$vA, VRRC:$vB))]>; 385 386def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>; 387def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>; 388def VMSUMSHS : VA1a_Int<41, "vmsumshs", int_ppc_altivec_vmsumshs>; 389def VMSUMUBM : VA1a_Int<36, "vmsumubm", int_ppc_altivec_vmsumubm>; 390def VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>; 391def VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>; 392 393def VMULESB : VX1_Int<776, "vmulesb", int_ppc_altivec_vmulesb>; 394def VMULESH : VX1_Int<840, "vmulesh", int_ppc_altivec_vmulesh>; 395def VMULEUB : VX1_Int<520, "vmuleub", int_ppc_altivec_vmuleub>; 396def VMULEUH : VX1_Int<584, "vmuleuh", int_ppc_altivec_vmuleuh>; 397def VMULOSB : VX1_Int<264, "vmulosb", int_ppc_altivec_vmulosb>; 398def VMULOSH : VX1_Int<328, "vmulosh", int_ppc_altivec_vmulosh>; 399def VMULOUB : VX1_Int< 8, "vmuloub", int_ppc_altivec_vmuloub>; 400def VMULOUH : VX1_Int< 72, "vmulouh", int_ppc_altivec_vmulouh>; 401 402def VREFP : VX2_Int<266, "vrefp", int_ppc_altivec_vrefp>; 403def VRFIM : VX2_Int<714, "vrfim", int_ppc_altivec_vrfim>; 404def VRFIN : VX2_Int<522, "vrfin", int_ppc_altivec_vrfin>; 405def VRFIP : VX2_Int<650, "vrfip", int_ppc_altivec_vrfip>; 406def VRFIZ : VX2_Int<586, "vrfiz", int_ppc_altivec_vrfiz>; 407def VRSQRTEFP : VX2_Int<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; 408 409def VSUBCUW : VX1_Int<74, "vsubcuw", int_ppc_altivec_vsubcuw>; 410 411def VSUBFP : VXForm_1<74, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 412 "vsubfp $vD, $vA, $vB", VecGeneral, 413 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>; 414def VSUBUBM : VXForm_1<1024, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 415 "vsububm $vD, $vA, $vB", VecGeneral, 416 [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>; 417def VSUBUHM : VXForm_1<1088, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 418 "vsubuhm $vD, $vA, $vB", VecGeneral, 419 [(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>; 420def VSUBUWM : VXForm_1<1152, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 421 "vsubuwm $vD, $vA, $vB", VecGeneral, 422 [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>; 423 424def VSUBSBS : VX1_Int<1792, "vsubsbs" , int_ppc_altivec_vsubsbs>; 425def VSUBSHS : VX1_Int<1856, "vsubshs" , int_ppc_altivec_vsubshs>; 426def VSUBSWS : VX1_Int<1920, "vsubsws" , int_ppc_altivec_vsubsws>; 427def VSUBUBS : VX1_Int<1536, "vsububs" , int_ppc_altivec_vsububs>; 428def VSUBUHS : VX1_Int<1600, "vsubuhs" , int_ppc_altivec_vsubuhs>; 429def VSUBUWS : VX1_Int<1664, "vsubuws" , int_ppc_altivec_vsubuws>; 430def VSUMSWS : VX1_Int<1928, "vsumsws" , int_ppc_altivec_vsumsws>; 431def VSUM2SWS: VX1_Int<1672, "vsum2sws", int_ppc_altivec_vsum2sws>; 432def VSUM4SBS: VX1_Int<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs>; 433def VSUM4SHS: VX1_Int<1608, "vsum4shs", int_ppc_altivec_vsum4shs>; 434def VSUM4UBS: VX1_Int<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs>; 435 436def VNOR : VXForm_1<1284, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 437 "vnor $vD, $vA, $vB", VecFP, 438 [(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>; 439def VOR : VXForm_1<1156, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 440 "vor $vD, $vA, $vB", VecFP, 441 [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>; 442def VXOR : VXForm_1<1220, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 443 "vxor $vD, $vA, $vB", VecFP, 444 [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>; 445 446def VRLB : VX1_Int< 4, "vrlb", int_ppc_altivec_vrlb>; 447def VRLH : VX1_Int< 68, "vrlh", int_ppc_altivec_vrlh>; 448def VRLW : VX1_Int< 132, "vrlw", int_ppc_altivec_vrlw>; 449 450def VSL : VX1_Int< 452, "vsl" , int_ppc_altivec_vsl >; 451def VSLO : VX1_Int<1036, "vslo", int_ppc_altivec_vslo>; 452def VSLB : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>; 453def VSLH : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>; 454def VSLW : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>; 455 456def VSPLTB : VXForm_1<524, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 457 "vspltb $vD, $vB, $UIMM", VecPerm, 458 [(set VRRC:$vD, 459 (vspltb_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>; 460def VSPLTH : VXForm_1<588, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 461 "vsplth $vD, $vB, $UIMM", VecPerm, 462 [(set VRRC:$vD, 463 (vsplth_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>; 464def VSPLTW : VXForm_1<652, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 465 "vspltw $vD, $vB, $UIMM", VecPerm, 466 [(set VRRC:$vD, 467 (vspltw_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>; 468 469def VSR : VX1_Int< 708, "vsr" , int_ppc_altivec_vsr>; 470def VSRO : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>; 471def VSRAB : VX1_Int< 772, "vsrab", int_ppc_altivec_vsrab>; 472def VSRAH : VX1_Int< 836, "vsrah", int_ppc_altivec_vsrah>; 473def VSRAW : VX1_Int< 900, "vsraw", int_ppc_altivec_vsraw>; 474def VSRB : VX1_Int< 516, "vsrb" , int_ppc_altivec_vsrb>; 475def VSRH : VX1_Int< 580, "vsrh" , int_ppc_altivec_vsrh>; 476def VSRW : VX1_Int< 644, "vsrw" , int_ppc_altivec_vsrw>; 477 478 479def VSPLTISB : VXForm_3<780, (outs VRRC:$vD), (ins s5imm:$SIMM), 480 "vspltisb $vD, $SIMM", VecPerm, 481 [(set VRRC:$vD, (v16i8 vecspltisb:$SIMM))]>; 482def VSPLTISH : VXForm_3<844, (outs VRRC:$vD), (ins s5imm:$SIMM), 483 "vspltish $vD, $SIMM", VecPerm, 484 [(set VRRC:$vD, (v8i16 vecspltish:$SIMM))]>; 485def VSPLTISW : VXForm_3<908, (outs VRRC:$vD), (ins s5imm:$SIMM), 486 "vspltisw $vD, $SIMM", VecPerm, 487 [(set VRRC:$vD, (v4i32 vecspltisw:$SIMM))]>; 488 489// Vector Pack. 490def VPKPX : VX1_Int<782, "vpkpx", int_ppc_altivec_vpkpx>; 491def VPKSHSS : VX1_Int<398, "vpkshss", int_ppc_altivec_vpkshss>; 492def VPKSHUS : VX1_Int<270, "vpkshus", int_ppc_altivec_vpkshus>; 493def VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>; 494def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>; 495def VPKUHUM : VXForm_1<14, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 496 "vpkuhum $vD, $vA, $vB", VecFP, 497 [(set VRRC:$vD, 498 (vpkuhum_shuffle (v16i8 VRRC:$vA), VRRC:$vB))]>; 499def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>; 500def VPKUWUM : VXForm_1<78, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 501 "vpkuwum $vD, $vA, $vB", VecFP, 502 [(set VRRC:$vD, 503 (vpkuwum_shuffle (v16i8 VRRC:$vA), VRRC:$vB))]>; 504def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>; 505 506// Vector Unpack. 507def VUPKHPX : VX2_Int<846, "vupkhpx", int_ppc_altivec_vupkhpx>; 508def VUPKHSB : VX2_Int<526, "vupkhsb", int_ppc_altivec_vupkhsb>; 509def VUPKHSH : VX2_Int<590, "vupkhsh", int_ppc_altivec_vupkhsh>; 510def VUPKLPX : VX2_Int<974, "vupklpx", int_ppc_altivec_vupklpx>; 511def VUPKLSB : VX2_Int<654, "vupklsb", int_ppc_altivec_vupklsb>; 512def VUPKLSH : VX2_Int<718, "vupklsh", int_ppc_altivec_vupklsh>; 513 514 515// Altivec Comparisons. 516 517class VCMP<bits<10> xo, string asmstr, ValueType Ty> 518 : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare, 519 [(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>; 520class VCMPo<bits<10> xo, string asmstr, ValueType Ty> 521 : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare, 522 [(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]> { 523 let Defs = [CR6]; 524 let RC = 1; 525} 526 527// f32 element comparisons.0 528def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; 529def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>; 530def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>; 531def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>; 532def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>; 533def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>; 534def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>; 535def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>; 536 537// i8 element comparisons. 538def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>; 539def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>; 540def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>; 541def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>; 542def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>; 543def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>; 544 545// i16 element comparisons. 546def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>; 547def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>; 548def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>; 549def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>; 550def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>; 551def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>; 552 553// i32 element comparisons. 554def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>; 555def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>; 556def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>; 557def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; 558def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; 559def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; 560 561def V_SET0 : VXForm_setzero<1220, (outs VRRC:$vD), (ins), 562 "vxor $vD, $vD, $vD", VecFP, 563 [(set VRRC:$vD, (v4i32 immAllZerosV))]>; 564} 565 566//===----------------------------------------------------------------------===// 567// Additional Altivec Patterns 568// 569 570// DS* intrinsics 571def : Pat<(int_ppc_altivec_dssall), (DSSALL 1, 0, 0, 0)>; 572def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>; 573 574// * 32-bit 575def : Pat<(int_ppc_altivec_dst GPRC:$rA, GPRC:$rB, imm:$STRM), 576 (DST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>; 577def : Pat<(int_ppc_altivec_dstt GPRC:$rA, GPRC:$rB, imm:$STRM), 578 (DSTT 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>; 579def : Pat<(int_ppc_altivec_dstst GPRC:$rA, GPRC:$rB, imm:$STRM), 580 (DSTST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>; 581def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM), 582 (DSTSTT 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>; 583 584// * 64-bit 585def : Pat<(int_ppc_altivec_dst G8RC:$rA, GPRC:$rB, imm:$STRM), 586 (DST64 0, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>; 587def : Pat<(int_ppc_altivec_dstt G8RC:$rA, GPRC:$rB, imm:$STRM), 588 (DSTT64 1, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>; 589def : Pat<(int_ppc_altivec_dstst G8RC:$rA, GPRC:$rB, imm:$STRM), 590 (DSTST64 0, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>; 591def : Pat<(int_ppc_altivec_dststt G8RC:$rA, GPRC:$rB, imm:$STRM), 592 (DSTSTT64 1, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>; 593 594// Loads. 595def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; 596 597// Stores. 598def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst), 599 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>; 600 601// Bit conversions. 602def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>; 603def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>; 604def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>; 605 606def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>; 607def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>; 608def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>; 609 610def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>; 611def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>; 612def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>; 613 614def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>; 615def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>; 616def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>; 617 618// Shuffles. 619 620// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x) 621def:Pat<(vsldoi_unary_shuffle:$in (v16i8 VRRC:$vA), undef), 622 (VSLDOI VRRC:$vA, VRRC:$vA, (VSLDOI_unary_get_imm VRRC:$in))>; 623def:Pat<(vpkuwum_unary_shuffle (v16i8 VRRC:$vA), undef), 624 (VPKUWUM VRRC:$vA, VRRC:$vA)>; 625def:Pat<(vpkuhum_unary_shuffle (v16i8 VRRC:$vA), undef), 626 (VPKUHUM VRRC:$vA, VRRC:$vA)>; 627 628// Match vmrg*(x,x) 629def:Pat<(vmrglb_unary_shuffle (v16i8 VRRC:$vA), undef), 630 (VMRGLB VRRC:$vA, VRRC:$vA)>; 631def:Pat<(vmrglh_unary_shuffle (v16i8 VRRC:$vA), undef), 632 (VMRGLH VRRC:$vA, VRRC:$vA)>; 633def:Pat<(vmrglw_unary_shuffle (v16i8 VRRC:$vA), undef), 634 (VMRGLW VRRC:$vA, VRRC:$vA)>; 635def:Pat<(vmrghb_unary_shuffle (v16i8 VRRC:$vA), undef), 636 (VMRGHB VRRC:$vA, VRRC:$vA)>; 637def:Pat<(vmrghh_unary_shuffle (v16i8 VRRC:$vA), undef), 638 (VMRGHH VRRC:$vA, VRRC:$vA)>; 639def:Pat<(vmrghw_unary_shuffle (v16i8 VRRC:$vA), undef), 640 (VMRGHW VRRC:$vA, VRRC:$vA)>; 641 642// Logical Operations 643def : Pat<(v4i32 (vnot VRRC:$vA)), (VNOR VRRC:$vA, VRRC:$vA)>; 644def : Pat<(v4i32 (vnot_conv VRRC:$vA)), (VNOR VRRC:$vA, VRRC:$vA)>; 645 646def : Pat<(v4i32 (vnot_conv (or VRRC:$A, VRRC:$B))), 647 (VNOR VRRC:$A, VRRC:$B)>; 648def : Pat<(v4i32 (and VRRC:$A, (vnot_conv VRRC:$B))), 649 (VANDC VRRC:$A, VRRC:$B)>; 650 651def : Pat<(fmul VRRC:$vA, VRRC:$vB), 652 (VMADDFP VRRC:$vA, VRRC:$vB, (v4i32 (V_SET0)))>; 653 654// Fused multiply add and multiply sub for packed float. These are represented 655// separately from the real instructions above, for operations that must have 656// the additional precision, such as Newton-Rhapson (used by divide, sqrt) 657def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C), 658 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>; 659def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C), 660 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>; 661 662def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C), 663 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>; 664def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C), 665 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>; 666 667def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC), 668 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC)>; 669 670// Vector shifts 671def : Pat<(v16i8 (shl (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))), 672 (v16i8 (VSLB VRRC:$vA, VRRC:$vB))>; 673def : Pat<(v8i16 (shl (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))), 674 (v8i16 (VSLH VRRC:$vA, VRRC:$vB))>; 675def : Pat<(v4i32 (shl (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))), 676 (v4i32 (VSLW VRRC:$vA, VRRC:$vB))>; 677 678def : Pat<(v16i8 (srl (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))), 679 (v16i8 (VSRB VRRC:$vA, VRRC:$vB))>; 680def : Pat<(v8i16 (srl (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))), 681 (v8i16 (VSRH VRRC:$vA, VRRC:$vB))>; 682def : Pat<(v4i32 (srl (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))), 683 (v4i32 (VSRW VRRC:$vA, VRRC:$vB))>; 684 685def : Pat<(v16i8 (sra (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))), 686 (v16i8 (VSRAB VRRC:$vA, VRRC:$vB))>; 687def : Pat<(v8i16 (sra (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))), 688 (v8i16 (VSRAH VRRC:$vA, VRRC:$vB))>; 689def : Pat<(v4i32 (sra (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))), 690 (v4i32 (VSRAW VRRC:$vA, VRRC:$vB))>; 691