PPCInstrAltivec.td revision 234353
1234353Sdim//===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===// 2234353Sdim// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7234353Sdim// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file describes the Altivec extension to the PowerPC instruction set. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed//===----------------------------------------------------------------------===// 15193323Sed// Altivec transformation functions and pattern fragments. 16193323Sed// 17193323Sed 18206083Srdivacky// Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be 19206083Srdivacky// of that type. 20206083Srdivackydef vnot_ppc : PatFrag<(ops node:$in), 21206083Srdivacky (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>; 22193323Sed 23193323Seddef vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 24193323Sed (vector_shuffle node:$lhs, node:$rhs), [{ 25193323Sed return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false); 26193323Sed}]>; 27193323Seddef vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 28193323Sed (vector_shuffle node:$lhs, node:$rhs), [{ 29193323Sed return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false); 30193323Sed}]>; 31193323Seddef vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 32193323Sed (vector_shuffle node:$lhs, node:$rhs), [{ 33193323Sed return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true); 34193323Sed}]>; 35193323Seddef vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 36193323Sed (vector_shuffle node:$lhs, node:$rhs), [{ 37193323Sed return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true); 38193323Sed}]>; 39193323Sed 40193323Sed 41193323Seddef vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 42204961Srdivacky (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 43193323Sed return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); 44193323Sed}]>; 45193323Seddef vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 46204961Srdivacky (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 47193323Sed return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); 48193323Sed}]>; 49193323Seddef vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 50204961Srdivacky (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 51193323Sed return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); 52193323Sed}]>; 53193323Seddef vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 54204961Srdivacky (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 55193323Sed return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); 56193323Sed}]>; 57193323Seddef vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 58204961Srdivacky (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 59193323Sed return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); 60193323Sed}]>; 61193323Seddef vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 62204961Srdivacky (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 63193323Sed return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); 64193323Sed}]>; 65193323Sed 66193323Sed 67193323Seddef vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 68204961Srdivacky (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 69193323Sed return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); 70193323Sed}]>; 71193323Seddef vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 72193323Sed (vector_shuffle node:$lhs, node:$rhs), [{ 73193323Sed return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true); 74193323Sed}]>; 75193323Seddef vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 76193323Sed (vector_shuffle node:$lhs, node:$rhs), [{ 77193323Sed return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true); 78193323Sed}]>; 79193323Seddef vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 80193323Sed (vector_shuffle node:$lhs, node:$rhs), [{ 81193323Sed return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); 82193323Sed}]>; 83193323Seddef vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 84193323Sed (vector_shuffle node:$lhs, node:$rhs), [{ 85193323Sed return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true); 86193323Sed}]>; 87193323Seddef vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 88193323Sed (vector_shuffle node:$lhs, node:$rhs), [{ 89193323Sed return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true); 90193323Sed}]>; 91193323Sed 92193323Sed 93193323Seddef VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{ 94193323Sed return getI32Imm(PPC::isVSLDOIShuffleMask(N, false)); 95193323Sed}]>; 96193323Seddef vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 97193323Sed (vector_shuffle node:$lhs, node:$rhs), [{ 98193323Sed return PPC::isVSLDOIShuffleMask(N, false) != -1; 99193323Sed}], VSLDOI_get_imm>; 100193323Sed 101193323Sed 102193323Sed/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into 103193323Sed/// vector_shuffle(X,undef,mask) by the dag combiner. 104193323Seddef VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{ 105193323Sed return getI32Imm(PPC::isVSLDOIShuffleMask(N, true)); 106193323Sed}]>; 107193323Seddef vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 108193323Sed (vector_shuffle node:$lhs, node:$rhs), [{ 109193323Sed return PPC::isVSLDOIShuffleMask(N, true) != -1; 110193323Sed}], VSLDOI_unary_get_imm>; 111193323Sed 112193323Sed 113193323Sed// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. 114193323Seddef VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{ 115193323Sed return getI32Imm(PPC::getVSPLTImmediate(N, 1)); 116193323Sed}]>; 117193323Seddef vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 118193323Sed (vector_shuffle node:$lhs, node:$rhs), [{ 119193323Sed return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1); 120193323Sed}], VSPLTB_get_imm>; 121193323Seddef VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{ 122193323Sed return getI32Imm(PPC::getVSPLTImmediate(N, 2)); 123193323Sed}]>; 124193323Seddef vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 125193323Sed (vector_shuffle node:$lhs, node:$rhs), [{ 126193323Sed return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2); 127193323Sed}], VSPLTH_get_imm>; 128193323Seddef VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{ 129193323Sed return getI32Imm(PPC::getVSPLTImmediate(N, 4)); 130193323Sed}]>; 131193323Seddef vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 132193323Sed (vector_shuffle node:$lhs, node:$rhs), [{ 133193323Sed return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4); 134193323Sed}], VSPLTW_get_imm>; 135193323Sed 136193323Sed 137193323Sed// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. 138193323Seddef VSPLTISB_get_imm : SDNodeXForm<build_vector, [{ 139193323Sed return PPC::get_VSPLTI_elt(N, 1, *CurDAG); 140193323Sed}]>; 141193323Seddef vecspltisb : PatLeaf<(build_vector), [{ 142193323Sed return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0; 143193323Sed}], VSPLTISB_get_imm>; 144193323Sed 145193323Sed// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm. 146193323Seddef VSPLTISH_get_imm : SDNodeXForm<build_vector, [{ 147193323Sed return PPC::get_VSPLTI_elt(N, 2, *CurDAG); 148193323Sed}]>; 149193323Seddef vecspltish : PatLeaf<(build_vector), [{ 150193323Sed return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0; 151193323Sed}], VSPLTISH_get_imm>; 152193323Sed 153193323Sed// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm. 154193323Seddef VSPLTISW_get_imm : SDNodeXForm<build_vector, [{ 155193323Sed return PPC::get_VSPLTI_elt(N, 4, *CurDAG); 156193323Sed}]>; 157193323Seddef vecspltisw : PatLeaf<(build_vector), [{ 158193323Sed return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0; 159193323Sed}], VSPLTISW_get_imm>; 160193323Sed 161193323Seddef V_immneg0 : PatLeaf<(build_vector), [{ 162193323Sed return PPC::isAllNegativeZeroVector(N); 163193323Sed}]>; 164193323Sed 165193323Sed//===----------------------------------------------------------------------===// 166193323Sed// Helpers for defining instructions that directly correspond to intrinsics. 167193323Sed 168193323Sed// VA1a_Int - A VAForm_1a intrinsic definition. 169193323Sedclass VA1a_Int<bits<6> xo, string opc, Intrinsic IntID> 170193323Sed : VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC), 171193323Sed !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, 172193323Sed [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>; 173193323Sed 174193323Sed// VX1_Int - A VXForm_1 intrinsic definition. 175193323Sedclass VX1_Int<bits<11> xo, string opc, Intrinsic IntID> 176193323Sed : VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 177193323Sed !strconcat(opc, " $vD, $vA, $vB"), VecFP, 178193323Sed [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>; 179193323Sed 180193323Sed// VX2_Int - A VXForm_2 intrinsic definition. 181193323Sedclass VX2_Int<bits<11> xo, string opc, Intrinsic IntID> 182193323Sed : VXForm_2<xo, (outs VRRC:$vD), (ins VRRC:$vB), 183193323Sed !strconcat(opc, " $vD, $vB"), VecFP, 184193323Sed [(set VRRC:$vD, (IntID VRRC:$vB))]>; 185193323Sed 186193323Sed//===----------------------------------------------------------------------===// 187193323Sed// Instruction Definitions. 188193323Sed 189193323Seddef DSS : DSS_Form<822, (outs), 190193323Sed (ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), 191234353Sdim "dss $STRM", LdStLoad /*FIXME*/, []>; 192193323Seddef DSSALL : DSS_Form<822, (outs), 193193323Sed (ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2), 194234353Sdim "dssall", LdStLoad /*FIXME*/, []>; 195193323Seddef DST : DSS_Form<342, (outs), 196193323Sed (ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 197234353Sdim "dst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 198193323Seddef DSTT : DSS_Form<342, (outs), 199193323Sed (ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 200234353Sdim "dstt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 201193323Seddef DSTST : DSS_Form<374, (outs), 202193323Sed (ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 203234353Sdim "dstst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 204193323Seddef DSTSTT : DSS_Form<374, (outs), 205193323Sed (ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 206234353Sdim "dststt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 207193323Sed 208193323Seddef DST64 : DSS_Form<342, (outs), 209193323Sed (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 210234353Sdim "dst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 211193323Seddef DSTT64 : DSS_Form<342, (outs), 212193323Sed (ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 213234353Sdim "dstt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 214193323Seddef DSTST64 : DSS_Form<374, (outs), 215193323Sed (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 216234353Sdim "dstst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 217193323Seddef DSTSTT64 : DSS_Form<374, (outs), 218193323Sed (ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 219234353Sdim "dststt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 220193323Sed 221193323Seddef MFVSCR : VXForm_4<1540, (outs VRRC:$vD), (ins), 222234353Sdim "mfvscr $vD", LdStStore, 223193323Sed [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>; 224193323Seddef MTVSCR : VXForm_5<1604, (outs), (ins VRRC:$vB), 225234353Sdim "mtvscr $vB", LdStLoad, 226193323Sed [(int_ppc_altivec_mtvscr VRRC:$vB)]>; 227193323Sed 228193323Sedlet canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads. 229193323Seddef LVEBX: XForm_1<31, 7, (outs VRRC:$vD), (ins memrr:$src), 230234353Sdim "lvebx $vD, $src", LdStLoad, 231193323Sed [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; 232193323Seddef LVEHX: XForm_1<31, 39, (outs VRRC:$vD), (ins memrr:$src), 233234353Sdim "lvehx $vD, $src", LdStLoad, 234193323Sed [(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>; 235193323Seddef LVEWX: XForm_1<31, 71, (outs VRRC:$vD), (ins memrr:$src), 236234353Sdim "lvewx $vD, $src", LdStLoad, 237193323Sed [(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; 238193323Seddef LVX : XForm_1<31, 103, (outs VRRC:$vD), (ins memrr:$src), 239234353Sdim "lvx $vD, $src", LdStLoad, 240193323Sed [(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; 241193323Seddef LVXL : XForm_1<31, 359, (outs VRRC:$vD), (ins memrr:$src), 242234353Sdim "lvxl $vD, $src", LdStLoad, 243193323Sed [(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; 244193323Sed} 245193323Sed 246193323Seddef LVSL : XForm_1<31, 6, (outs VRRC:$vD), (ins memrr:$src), 247234353Sdim "lvsl $vD, $src", LdStLoad, 248193323Sed [(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, 249193323Sed PPC970_Unit_LSU; 250193323Seddef LVSR : XForm_1<31, 38, (outs VRRC:$vD), (ins memrr:$src), 251234353Sdim "lvsr $vD, $src", LdStLoad, 252193323Sed [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, 253193323Sed PPC970_Unit_LSU; 254193323Sed 255193323Sedlet PPC970_Unit = 2 in { // Stores. 256193323Seddef STVEBX: XForm_8<31, 135, (outs), (ins VRRC:$rS, memrr:$dst), 257234353Sdim "stvebx $rS, $dst", LdStStore, 258193323Sed [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>; 259193323Seddef STVEHX: XForm_8<31, 167, (outs), (ins VRRC:$rS, memrr:$dst), 260234353Sdim "stvehx $rS, $dst", LdStStore, 261193323Sed [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>; 262193323Seddef STVEWX: XForm_8<31, 199, (outs), (ins VRRC:$rS, memrr:$dst), 263234353Sdim "stvewx $rS, $dst", LdStStore, 264193323Sed [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>; 265193323Seddef STVX : XForm_8<31, 231, (outs), (ins VRRC:$rS, memrr:$dst), 266234353Sdim "stvx $rS, $dst", LdStStore, 267193323Sed [(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>; 268193323Seddef STVXL : XForm_8<31, 487, (outs), (ins VRRC:$rS, memrr:$dst), 269234353Sdim "stvxl $rS, $dst", LdStStore, 270193323Sed [(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>; 271193323Sed} 272193323Sed 273193323Sedlet PPC970_Unit = 5 in { // VALU Operations. 274193323Sed// VA-Form instructions. 3-input AltiVec ops. 275193323Seddef VMADDFP : VAForm_1<46, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB), 276193323Sed "vmaddfp $vD, $vA, $vC, $vB", VecFP, 277193323Sed [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC), 278193323Sed VRRC:$vB))]>, 279193323Sed Requires<[FPContractions]>; 280193323Seddef VNMSUBFP: VAForm_1<47, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB), 281193323Sed "vnmsubfp $vD, $vA, $vC, $vB", VecFP, 282193323Sed [(set VRRC:$vD, (fsub V_immneg0, 283193323Sed (fsub (fmul VRRC:$vA, VRRC:$vC), 284193323Sed VRRC:$vB)))]>, 285193323Sed Requires<[FPContractions]>; 286193323Sed 287193323Seddef VMHADDSHS : VA1a_Int<32, "vmhaddshs", int_ppc_altivec_vmhaddshs>; 288193323Seddef VMHRADDSHS : VA1a_Int<33, "vmhraddshs", int_ppc_altivec_vmhraddshs>; 289193323Seddef VMLADDUHM : VA1a_Int<34, "vmladduhm", int_ppc_altivec_vmladduhm>; 290193323Seddef VPERM : VA1a_Int<43, "vperm", int_ppc_altivec_vperm>; 291193323Seddef VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>; 292193323Sed 293193323Sed// Shuffles. 294193323Seddef VSLDOI : VAForm_2<44, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, u5imm:$SH), 295193323Sed "vsldoi $vD, $vA, $vB, $SH", VecFP, 296193323Sed [(set VRRC:$vD, 297193323Sed (vsldoi_shuffle:$SH (v16i8 VRRC:$vA), VRRC:$vB))]>; 298193323Sed 299193323Sed// VX-Form instructions. AltiVec arithmetic ops. 300193323Seddef VADDFP : VXForm_1<10, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 301193323Sed "vaddfp $vD, $vA, $vB", VecFP, 302193323Sed [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>; 303193323Sed 304193323Seddef VADDUBM : VXForm_1<0, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 305193323Sed "vaddubm $vD, $vA, $vB", VecGeneral, 306193323Sed [(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>; 307193323Seddef VADDUHM : VXForm_1<64, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 308193323Sed "vadduhm $vD, $vA, $vB", VecGeneral, 309193323Sed [(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>; 310193323Seddef VADDUWM : VXForm_1<128, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 311193323Sed "vadduwm $vD, $vA, $vB", VecGeneral, 312193323Sed [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>; 313193323Sed 314193323Seddef VADDCUW : VX1_Int<384, "vaddcuw", int_ppc_altivec_vaddcuw>; 315193323Seddef VADDSBS : VX1_Int<768, "vaddsbs", int_ppc_altivec_vaddsbs>; 316193323Seddef VADDSHS : VX1_Int<832, "vaddshs", int_ppc_altivec_vaddshs>; 317193323Seddef VADDSWS : VX1_Int<896, "vaddsws", int_ppc_altivec_vaddsws>; 318193323Seddef VADDUBS : VX1_Int<512, "vaddubs", int_ppc_altivec_vaddubs>; 319193323Seddef VADDUHS : VX1_Int<576, "vadduhs", int_ppc_altivec_vadduhs>; 320193323Seddef VADDUWS : VX1_Int<640, "vadduws", int_ppc_altivec_vadduws>; 321193323Sed 322193323Sed 323193323Seddef VAND : VXForm_1<1028, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 324193323Sed "vand $vD, $vA, $vB", VecFP, 325193323Sed [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>; 326193323Seddef VANDC : VXForm_1<1092, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 327193323Sed "vandc $vD, $vA, $vB", VecFP, 328206083Srdivacky [(set VRRC:$vD, (and (v4i32 VRRC:$vA), 329206083Srdivacky (vnot_ppc VRRC:$vB)))]>; 330193323Sed 331193323Seddef VCFSX : VXForm_1<842, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 332193323Sed "vcfsx $vD, $vB, $UIMM", VecFP, 333193323Sed [(set VRRC:$vD, 334193323Sed (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>; 335193323Seddef VCFUX : VXForm_1<778, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 336193323Sed "vcfux $vD, $vB, $UIMM", VecFP, 337193323Sed [(set VRRC:$vD, 338193323Sed (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>; 339193323Seddef VCTSXS : VXForm_1<970, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 340193323Sed "vctsxs $vD, $vB, $UIMM", VecFP, 341193323Sed [(set VRRC:$vD, 342193323Sed (int_ppc_altivec_vctsxs VRRC:$vB, imm:$UIMM))]>; 343193323Seddef VCTUXS : VXForm_1<906, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 344193323Sed "vctuxs $vD, $vB, $UIMM", VecFP, 345193323Sed [(set VRRC:$vD, 346193323Sed (int_ppc_altivec_vctuxs VRRC:$vB, imm:$UIMM))]>; 347193323Seddef VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>; 348193323Seddef VLOGEFP : VX2_Int<458, "vlogefp", int_ppc_altivec_vlogefp>; 349193323Sed 350193323Seddef VAVGSB : VX1_Int<1282, "vavgsb", int_ppc_altivec_vavgsb>; 351193323Seddef VAVGSH : VX1_Int<1346, "vavgsh", int_ppc_altivec_vavgsh>; 352193323Seddef VAVGSW : VX1_Int<1410, "vavgsw", int_ppc_altivec_vavgsw>; 353193323Seddef VAVGUB : VX1_Int<1026, "vavgub", int_ppc_altivec_vavgub>; 354193323Seddef VAVGUH : VX1_Int<1090, "vavguh", int_ppc_altivec_vavguh>; 355193323Seddef VAVGUW : VX1_Int<1154, "vavguw", int_ppc_altivec_vavguw>; 356193323Sed 357193323Seddef VMAXFP : VX1_Int<1034, "vmaxfp", int_ppc_altivec_vmaxfp>; 358193323Seddef VMAXSB : VX1_Int< 258, "vmaxsb", int_ppc_altivec_vmaxsb>; 359193323Seddef VMAXSH : VX1_Int< 322, "vmaxsh", int_ppc_altivec_vmaxsh>; 360193323Seddef VMAXSW : VX1_Int< 386, "vmaxsw", int_ppc_altivec_vmaxsw>; 361193323Seddef VMAXUB : VX1_Int< 2, "vmaxub", int_ppc_altivec_vmaxub>; 362193323Seddef VMAXUH : VX1_Int< 66, "vmaxuh", int_ppc_altivec_vmaxuh>; 363193323Seddef VMAXUW : VX1_Int< 130, "vmaxuw", int_ppc_altivec_vmaxuw>; 364193323Seddef VMINFP : VX1_Int<1098, "vminfp", int_ppc_altivec_vminfp>; 365193323Seddef VMINSB : VX1_Int< 770, "vminsb", int_ppc_altivec_vminsb>; 366193323Seddef VMINSH : VX1_Int< 834, "vminsh", int_ppc_altivec_vminsh>; 367193323Seddef VMINSW : VX1_Int< 898, "vminsw", int_ppc_altivec_vminsw>; 368193323Seddef VMINUB : VX1_Int< 514, "vminub", int_ppc_altivec_vminub>; 369193323Seddef VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>; 370193323Seddef VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>; 371193323Sed 372193323Seddef VMRGHB : VXForm_1< 12, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 373193323Sed "vmrghb $vD, $vA, $vB", VecFP, 374193323Sed [(set VRRC:$vD, (vmrghb_shuffle VRRC:$vA, VRRC:$vB))]>; 375193323Seddef VMRGHH : VXForm_1< 76, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 376193323Sed "vmrghh $vD, $vA, $vB", VecFP, 377193323Sed [(set VRRC:$vD, (vmrghh_shuffle VRRC:$vA, VRRC:$vB))]>; 378193323Seddef VMRGHW : VXForm_1<140, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 379193323Sed "vmrghw $vD, $vA, $vB", VecFP, 380193323Sed [(set VRRC:$vD, (vmrghw_shuffle VRRC:$vA, VRRC:$vB))]>; 381193323Seddef VMRGLB : VXForm_1<268, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 382193323Sed "vmrglb $vD, $vA, $vB", VecFP, 383193323Sed [(set VRRC:$vD, (vmrglb_shuffle VRRC:$vA, VRRC:$vB))]>; 384193323Seddef VMRGLH : VXForm_1<332, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 385193323Sed "vmrglh $vD, $vA, $vB", VecFP, 386193323Sed [(set VRRC:$vD, (vmrglh_shuffle VRRC:$vA, VRRC:$vB))]>; 387193323Seddef VMRGLW : VXForm_1<396, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 388193323Sed "vmrglw $vD, $vA, $vB", VecFP, 389193323Sed [(set VRRC:$vD, (vmrglw_shuffle VRRC:$vA, VRRC:$vB))]>; 390193323Sed 391193323Seddef VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>; 392193323Seddef VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>; 393193323Seddef VMSUMSHS : VA1a_Int<41, "vmsumshs", int_ppc_altivec_vmsumshs>; 394193323Seddef VMSUMUBM : VA1a_Int<36, "vmsumubm", int_ppc_altivec_vmsumubm>; 395193323Seddef VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>; 396193323Seddef VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>; 397193323Sed 398193323Seddef VMULESB : VX1_Int<776, "vmulesb", int_ppc_altivec_vmulesb>; 399193323Seddef VMULESH : VX1_Int<840, "vmulesh", int_ppc_altivec_vmulesh>; 400193323Seddef VMULEUB : VX1_Int<520, "vmuleub", int_ppc_altivec_vmuleub>; 401193323Seddef VMULEUH : VX1_Int<584, "vmuleuh", int_ppc_altivec_vmuleuh>; 402193323Seddef VMULOSB : VX1_Int<264, "vmulosb", int_ppc_altivec_vmulosb>; 403193323Seddef VMULOSH : VX1_Int<328, "vmulosh", int_ppc_altivec_vmulosh>; 404193323Seddef VMULOUB : VX1_Int< 8, "vmuloub", int_ppc_altivec_vmuloub>; 405193323Seddef VMULOUH : VX1_Int< 72, "vmulouh", int_ppc_altivec_vmulouh>; 406193323Sed 407193323Seddef VREFP : VX2_Int<266, "vrefp", int_ppc_altivec_vrefp>; 408193323Seddef VRFIM : VX2_Int<714, "vrfim", int_ppc_altivec_vrfim>; 409193323Seddef VRFIN : VX2_Int<522, "vrfin", int_ppc_altivec_vrfin>; 410193323Seddef VRFIP : VX2_Int<650, "vrfip", int_ppc_altivec_vrfip>; 411193323Seddef VRFIZ : VX2_Int<586, "vrfiz", int_ppc_altivec_vrfiz>; 412193323Seddef VRSQRTEFP : VX2_Int<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; 413193323Sed 414193323Seddef VSUBCUW : VX1_Int<74, "vsubcuw", int_ppc_altivec_vsubcuw>; 415193323Sed 416193323Seddef VSUBFP : VXForm_1<74, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 417193323Sed "vsubfp $vD, $vA, $vB", VecGeneral, 418193323Sed [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>; 419193323Seddef VSUBUBM : VXForm_1<1024, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 420193323Sed "vsububm $vD, $vA, $vB", VecGeneral, 421193323Sed [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>; 422193323Seddef VSUBUHM : VXForm_1<1088, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 423193323Sed "vsubuhm $vD, $vA, $vB", VecGeneral, 424193323Sed [(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>; 425193323Seddef VSUBUWM : VXForm_1<1152, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 426193323Sed "vsubuwm $vD, $vA, $vB", VecGeneral, 427193323Sed [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>; 428193323Sed 429193323Seddef VSUBSBS : VX1_Int<1792, "vsubsbs" , int_ppc_altivec_vsubsbs>; 430193323Seddef VSUBSHS : VX1_Int<1856, "vsubshs" , int_ppc_altivec_vsubshs>; 431193323Seddef VSUBSWS : VX1_Int<1920, "vsubsws" , int_ppc_altivec_vsubsws>; 432193323Seddef VSUBUBS : VX1_Int<1536, "vsububs" , int_ppc_altivec_vsububs>; 433193323Seddef VSUBUHS : VX1_Int<1600, "vsubuhs" , int_ppc_altivec_vsubuhs>; 434193323Seddef VSUBUWS : VX1_Int<1664, "vsubuws" , int_ppc_altivec_vsubuws>; 435193323Seddef VSUMSWS : VX1_Int<1928, "vsumsws" , int_ppc_altivec_vsumsws>; 436193323Seddef VSUM2SWS: VX1_Int<1672, "vsum2sws", int_ppc_altivec_vsum2sws>; 437193323Seddef VSUM4SBS: VX1_Int<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs>; 438193323Seddef VSUM4SHS: VX1_Int<1608, "vsum4shs", int_ppc_altivec_vsum4shs>; 439193323Seddef VSUM4UBS: VX1_Int<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs>; 440193323Sed 441193323Seddef VNOR : VXForm_1<1284, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 442193323Sed "vnor $vD, $vA, $vB", VecFP, 443206083Srdivacky [(set VRRC:$vD, (vnot_ppc (or (v4i32 VRRC:$vA), 444206083Srdivacky VRRC:$vB)))]>; 445193323Seddef VOR : VXForm_1<1156, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 446193323Sed "vor $vD, $vA, $vB", VecFP, 447193323Sed [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>; 448193323Seddef VXOR : VXForm_1<1220, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 449193323Sed "vxor $vD, $vA, $vB", VecFP, 450193323Sed [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>; 451193323Sed 452193323Seddef VRLB : VX1_Int< 4, "vrlb", int_ppc_altivec_vrlb>; 453193323Seddef VRLH : VX1_Int< 68, "vrlh", int_ppc_altivec_vrlh>; 454193323Seddef VRLW : VX1_Int< 132, "vrlw", int_ppc_altivec_vrlw>; 455193323Sed 456193323Seddef VSL : VX1_Int< 452, "vsl" , int_ppc_altivec_vsl >; 457193323Seddef VSLO : VX1_Int<1036, "vslo", int_ppc_altivec_vslo>; 458193323Seddef VSLB : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>; 459193323Seddef VSLH : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>; 460193323Seddef VSLW : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>; 461193323Sed 462193323Seddef VSPLTB : VXForm_1<524, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 463193323Sed "vspltb $vD, $vB, $UIMM", VecPerm, 464193323Sed [(set VRRC:$vD, 465193323Sed (vspltb_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>; 466193323Seddef VSPLTH : VXForm_1<588, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 467193323Sed "vsplth $vD, $vB, $UIMM", VecPerm, 468193323Sed [(set VRRC:$vD, 469193323Sed (vsplth_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>; 470193323Seddef VSPLTW : VXForm_1<652, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 471193323Sed "vspltw $vD, $vB, $UIMM", VecPerm, 472193323Sed [(set VRRC:$vD, 473193323Sed (vspltw_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>; 474193323Sed 475193323Seddef VSR : VX1_Int< 708, "vsr" , int_ppc_altivec_vsr>; 476193323Seddef VSRO : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>; 477193323Seddef VSRAB : VX1_Int< 772, "vsrab", int_ppc_altivec_vsrab>; 478193323Seddef VSRAH : VX1_Int< 836, "vsrah", int_ppc_altivec_vsrah>; 479193323Seddef VSRAW : VX1_Int< 900, "vsraw", int_ppc_altivec_vsraw>; 480193323Seddef VSRB : VX1_Int< 516, "vsrb" , int_ppc_altivec_vsrb>; 481193323Seddef VSRH : VX1_Int< 580, "vsrh" , int_ppc_altivec_vsrh>; 482193323Seddef VSRW : VX1_Int< 644, "vsrw" , int_ppc_altivec_vsrw>; 483193323Sed 484193323Sed 485193323Seddef VSPLTISB : VXForm_3<780, (outs VRRC:$vD), (ins s5imm:$SIMM), 486193323Sed "vspltisb $vD, $SIMM", VecPerm, 487193323Sed [(set VRRC:$vD, (v16i8 vecspltisb:$SIMM))]>; 488193323Seddef VSPLTISH : VXForm_3<844, (outs VRRC:$vD), (ins s5imm:$SIMM), 489193323Sed "vspltish $vD, $SIMM", VecPerm, 490193323Sed [(set VRRC:$vD, (v8i16 vecspltish:$SIMM))]>; 491193323Seddef VSPLTISW : VXForm_3<908, (outs VRRC:$vD), (ins s5imm:$SIMM), 492193323Sed "vspltisw $vD, $SIMM", VecPerm, 493193323Sed [(set VRRC:$vD, (v4i32 vecspltisw:$SIMM))]>; 494193323Sed 495193323Sed// Vector Pack. 496193323Seddef VPKPX : VX1_Int<782, "vpkpx", int_ppc_altivec_vpkpx>; 497193323Seddef VPKSHSS : VX1_Int<398, "vpkshss", int_ppc_altivec_vpkshss>; 498193323Seddef VPKSHUS : VX1_Int<270, "vpkshus", int_ppc_altivec_vpkshus>; 499193323Seddef VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>; 500193323Seddef VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>; 501193323Seddef VPKUHUM : VXForm_1<14, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 502193323Sed "vpkuhum $vD, $vA, $vB", VecFP, 503193323Sed [(set VRRC:$vD, 504193323Sed (vpkuhum_shuffle (v16i8 VRRC:$vA), VRRC:$vB))]>; 505193323Seddef VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>; 506193323Seddef VPKUWUM : VXForm_1<78, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 507193323Sed "vpkuwum $vD, $vA, $vB", VecFP, 508193323Sed [(set VRRC:$vD, 509193323Sed (vpkuwum_shuffle (v16i8 VRRC:$vA), VRRC:$vB))]>; 510193323Seddef VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>; 511193323Sed 512193323Sed// Vector Unpack. 513193323Seddef VUPKHPX : VX2_Int<846, "vupkhpx", int_ppc_altivec_vupkhpx>; 514193323Seddef VUPKHSB : VX2_Int<526, "vupkhsb", int_ppc_altivec_vupkhsb>; 515193323Seddef VUPKHSH : VX2_Int<590, "vupkhsh", int_ppc_altivec_vupkhsh>; 516193323Seddef VUPKLPX : VX2_Int<974, "vupklpx", int_ppc_altivec_vupklpx>; 517193323Seddef VUPKLSB : VX2_Int<654, "vupklsb", int_ppc_altivec_vupklsb>; 518193323Seddef VUPKLSH : VX2_Int<718, "vupklsh", int_ppc_altivec_vupklsh>; 519193323Sed 520193323Sed 521193323Sed// Altivec Comparisons. 522193323Sed 523193323Sedclass VCMP<bits<10> xo, string asmstr, ValueType Ty> 524193323Sed : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare, 525193323Sed [(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>; 526193323Sedclass VCMPo<bits<10> xo, string asmstr, ValueType Ty> 527193323Sed : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare, 528193323Sed [(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]> { 529193323Sed let Defs = [CR6]; 530193323Sed let RC = 1; 531193323Sed} 532193323Sed 533193323Sed// f32 element comparisons.0 534193323Seddef VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; 535193323Seddef VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>; 536193323Seddef VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>; 537193323Seddef VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>; 538193323Seddef VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>; 539193323Seddef VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>; 540193323Seddef VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>; 541193323Seddef VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>; 542193323Sed 543193323Sed// i8 element comparisons. 544193323Seddef VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>; 545193323Seddef VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>; 546193323Seddef VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>; 547193323Seddef VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>; 548193323Seddef VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>; 549193323Seddef VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>; 550193323Sed 551193323Sed// i16 element comparisons. 552193323Seddef VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>; 553193323Seddef VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>; 554193323Seddef VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>; 555193323Seddef VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>; 556193323Seddef VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>; 557193323Seddef VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>; 558193323Sed 559193323Sed// i32 element comparisons. 560193323Seddef VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>; 561193323Seddef VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>; 562193323Seddef VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>; 563193323Seddef VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; 564193323Seddef VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; 565193323Seddef VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; 566193323Sed 567193323Seddef V_SET0 : VXForm_setzero<1220, (outs VRRC:$vD), (ins), 568193323Sed "vxor $vD, $vD, $vD", VecFP, 569193323Sed [(set VRRC:$vD, (v4i32 immAllZerosV))]>; 570193323Sed} 571193323Sed 572193323Sed//===----------------------------------------------------------------------===// 573193323Sed// Additional Altivec Patterns 574193323Sed// 575193323Sed 576193323Sed// DS* intrinsics 577193323Seddef : Pat<(int_ppc_altivec_dssall), (DSSALL 1, 0, 0, 0)>; 578193323Seddef : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>; 579193323Sed 580193323Sed// * 32-bit 581193323Seddef : Pat<(int_ppc_altivec_dst GPRC:$rA, GPRC:$rB, imm:$STRM), 582193323Sed (DST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>; 583193323Seddef : Pat<(int_ppc_altivec_dstt GPRC:$rA, GPRC:$rB, imm:$STRM), 584193323Sed (DSTT 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>; 585193323Seddef : Pat<(int_ppc_altivec_dstst GPRC:$rA, GPRC:$rB, imm:$STRM), 586193323Sed (DSTST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>; 587193323Seddef : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM), 588193323Sed (DSTSTT 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>; 589193323Sed 590193323Sed// * 64-bit 591193323Seddef : Pat<(int_ppc_altivec_dst G8RC:$rA, GPRC:$rB, imm:$STRM), 592193323Sed (DST64 0, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>; 593193323Seddef : Pat<(int_ppc_altivec_dstt G8RC:$rA, GPRC:$rB, imm:$STRM), 594193323Sed (DSTT64 1, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>; 595193323Seddef : Pat<(int_ppc_altivec_dstst G8RC:$rA, GPRC:$rB, imm:$STRM), 596193323Sed (DSTST64 0, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>; 597193323Seddef : Pat<(int_ppc_altivec_dststt G8RC:$rA, GPRC:$rB, imm:$STRM), 598193323Sed (DSTSTT64 1, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>; 599193323Sed 600193323Sed// Loads. 601193323Seddef : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; 602193323Sed 603193323Sed// Stores. 604193323Seddef : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst), 605193323Sed (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>; 606193323Sed 607193323Sed// Bit conversions. 608193323Seddef : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>; 609193323Seddef : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>; 610193323Seddef : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>; 611193323Sed 612193323Seddef : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>; 613193323Seddef : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>; 614193323Seddef : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>; 615193323Sed 616193323Seddef : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>; 617193323Seddef : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>; 618193323Seddef : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>; 619193323Sed 620193323Seddef : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>; 621193323Seddef : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>; 622193323Seddef : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>; 623193323Sed 624193323Sed// Shuffles. 625193323Sed 626193323Sed// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x) 627193323Seddef:Pat<(vsldoi_unary_shuffle:$in (v16i8 VRRC:$vA), undef), 628193323Sed (VSLDOI VRRC:$vA, VRRC:$vA, (VSLDOI_unary_get_imm VRRC:$in))>; 629193323Seddef:Pat<(vpkuwum_unary_shuffle (v16i8 VRRC:$vA), undef), 630193323Sed (VPKUWUM VRRC:$vA, VRRC:$vA)>; 631193323Seddef:Pat<(vpkuhum_unary_shuffle (v16i8 VRRC:$vA), undef), 632193323Sed (VPKUHUM VRRC:$vA, VRRC:$vA)>; 633193323Sed 634193323Sed// Match vmrg*(x,x) 635193323Seddef:Pat<(vmrglb_unary_shuffle (v16i8 VRRC:$vA), undef), 636193323Sed (VMRGLB VRRC:$vA, VRRC:$vA)>; 637193323Seddef:Pat<(vmrglh_unary_shuffle (v16i8 VRRC:$vA), undef), 638193323Sed (VMRGLH VRRC:$vA, VRRC:$vA)>; 639193323Seddef:Pat<(vmrglw_unary_shuffle (v16i8 VRRC:$vA), undef), 640193323Sed (VMRGLW VRRC:$vA, VRRC:$vA)>; 641193323Seddef:Pat<(vmrghb_unary_shuffle (v16i8 VRRC:$vA), undef), 642193323Sed (VMRGHB VRRC:$vA, VRRC:$vA)>; 643193323Seddef:Pat<(vmrghh_unary_shuffle (v16i8 VRRC:$vA), undef), 644193323Sed (VMRGHH VRRC:$vA, VRRC:$vA)>; 645193323Seddef:Pat<(vmrghw_unary_shuffle (v16i8 VRRC:$vA), undef), 646193323Sed (VMRGHW VRRC:$vA, VRRC:$vA)>; 647193323Sed 648193323Sed// Logical Operations 649206083Srdivackydef : Pat<(v4i32 (vnot_ppc VRRC:$vA)), (VNOR VRRC:$vA, VRRC:$vA)>; 650193323Sed 651206083Srdivackydef : Pat<(v4i32 (vnot_ppc (or VRRC:$A, VRRC:$B))), 652193323Sed (VNOR VRRC:$A, VRRC:$B)>; 653206083Srdivackydef : Pat<(v4i32 (and VRRC:$A, (vnot_ppc VRRC:$B))), 654193323Sed (VANDC VRRC:$A, VRRC:$B)>; 655193323Sed 656193323Seddef : Pat<(fmul VRRC:$vA, VRRC:$vB), 657193323Sed (VMADDFP VRRC:$vA, VRRC:$vB, (v4i32 (V_SET0)))>; 658193323Sed 659193323Sed// Fused multiply add and multiply sub for packed float. These are represented 660193323Sed// separately from the real instructions above, for operations that must have 661193323Sed// the additional precision, such as Newton-Rhapson (used by divide, sqrt) 662193323Seddef : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C), 663193323Sed (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>; 664193323Seddef : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C), 665193323Sed (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>; 666193323Sed 667193323Seddef : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C), 668193323Sed (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>; 669193323Seddef : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C), 670193323Sed (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>; 671193323Sed 672193323Seddef : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC), 673193323Sed (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC)>; 674193630Sed 675193630Sed// Vector shifts 676193630Seddef : Pat<(v16i8 (shl (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))), 677193630Sed (v16i8 (VSLB VRRC:$vA, VRRC:$vB))>; 678193630Seddef : Pat<(v8i16 (shl (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))), 679193630Sed (v8i16 (VSLH VRRC:$vA, VRRC:$vB))>; 680193630Seddef : Pat<(v4i32 (shl (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))), 681193630Sed (v4i32 (VSLW VRRC:$vA, VRRC:$vB))>; 682193630Sed 683193630Seddef : Pat<(v16i8 (srl (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))), 684193630Sed (v16i8 (VSRB VRRC:$vA, VRRC:$vB))>; 685193630Seddef : Pat<(v8i16 (srl (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))), 686193630Sed (v8i16 (VSRH VRRC:$vA, VRRC:$vB))>; 687193630Seddef : Pat<(v4i32 (srl (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))), 688193630Sed (v4i32 (VSRW VRRC:$vA, VRRC:$vB))>; 689193630Sed 690193630Seddef : Pat<(v16i8 (sra (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))), 691193630Sed (v16i8 (VSRAB VRRC:$vA, VRRC:$vB))>; 692193630Seddef : Pat<(v8i16 (sra (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))), 693193630Sed (v8i16 (VSRAH VRRC:$vA, VRRC:$vB))>; 694193630Seddef : Pat<(v4i32 (sra (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))), 695193630Sed (v4i32 (VSRAW VRRC:$vA, VRRC:$vB))>; 696