PPCFrameLowering.cpp revision 277320
1//===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the PPC implementation of TargetFrameLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCFrameLowering.h" 15#include "PPCInstrBuilder.h" 16#include "PPCInstrInfo.h" 17#include "PPCMachineFunctionInfo.h" 18#include "PPCSubtarget.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineModuleInfo.h" 23#include "llvm/CodeGen/MachineRegisterInfo.h" 24#include "llvm/CodeGen/RegisterScavenging.h" 25#include "llvm/IR/Function.h" 26#include "llvm/Target/TargetOptions.h" 27 28using namespace llvm; 29 30/// VRRegNo - Map from a numbered VR register to its enum value. 31/// 32static const uint16_t VRRegNo[] = { 33 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 34 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 35 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 36 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 37}; 38 39PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI) 40 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 41 (STI.hasQPX() || STI.isBGQ()) ? 32 : 16, 0), 42 Subtarget(STI) {} 43 44// With the SVR4 ABI, callee-saved registers have fixed offsets on the stack. 45const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots( 46 unsigned &NumEntries) const { 47 if (Subtarget.isDarwinABI()) { 48 NumEntries = 1; 49 if (Subtarget.isPPC64()) { 50 static const SpillSlot darwin64Offsets = {PPC::X31, -8}; 51 return &darwin64Offsets; 52 } else { 53 static const SpillSlot darwinOffsets = {PPC::R31, -4}; 54 return &darwinOffsets; 55 } 56 } 57 58 // Early exit if not using the SVR4 ABI. 59 if (!Subtarget.isSVR4ABI()) { 60 NumEntries = 0; 61 return nullptr; 62 } 63 64 // Note that the offsets here overlap, but this is fixed up in 65 // processFunctionBeforeFrameFinalized. 66 67 static const SpillSlot Offsets[] = { 68 // Floating-point register save area offsets. 69 {PPC::F31, -8}, 70 {PPC::F30, -16}, 71 {PPC::F29, -24}, 72 {PPC::F28, -32}, 73 {PPC::F27, -40}, 74 {PPC::F26, -48}, 75 {PPC::F25, -56}, 76 {PPC::F24, -64}, 77 {PPC::F23, -72}, 78 {PPC::F22, -80}, 79 {PPC::F21, -88}, 80 {PPC::F20, -96}, 81 {PPC::F19, -104}, 82 {PPC::F18, -112}, 83 {PPC::F17, -120}, 84 {PPC::F16, -128}, 85 {PPC::F15, -136}, 86 {PPC::F14, -144}, 87 88 // General register save area offsets. 89 {PPC::R31, -4}, 90 {PPC::R30, -8}, 91 {PPC::R29, -12}, 92 {PPC::R28, -16}, 93 {PPC::R27, -20}, 94 {PPC::R26, -24}, 95 {PPC::R25, -28}, 96 {PPC::R24, -32}, 97 {PPC::R23, -36}, 98 {PPC::R22, -40}, 99 {PPC::R21, -44}, 100 {PPC::R20, -48}, 101 {PPC::R19, -52}, 102 {PPC::R18, -56}, 103 {PPC::R17, -60}, 104 {PPC::R16, -64}, 105 {PPC::R15, -68}, 106 {PPC::R14, -72}, 107 108 // CR save area offset. We map each of the nonvolatile CR fields 109 // to the slot for CR2, which is the first of the nonvolatile CR 110 // fields to be assigned, so that we only allocate one save slot. 111 // See PPCRegisterInfo::hasReservedSpillSlot() for more information. 112 {PPC::CR2, -4}, 113 114 // VRSAVE save area offset. 115 {PPC::VRSAVE, -4}, 116 117 // Vector register save area 118 {PPC::V31, -16}, 119 {PPC::V30, -32}, 120 {PPC::V29, -48}, 121 {PPC::V28, -64}, 122 {PPC::V27, -80}, 123 {PPC::V26, -96}, 124 {PPC::V25, -112}, 125 {PPC::V24, -128}, 126 {PPC::V23, -144}, 127 {PPC::V22, -160}, 128 {PPC::V21, -176}, 129 {PPC::V20, -192}}; 130 131 static const SpillSlot Offsets64[] = { 132 // Floating-point register save area offsets. 133 {PPC::F31, -8}, 134 {PPC::F30, -16}, 135 {PPC::F29, -24}, 136 {PPC::F28, -32}, 137 {PPC::F27, -40}, 138 {PPC::F26, -48}, 139 {PPC::F25, -56}, 140 {PPC::F24, -64}, 141 {PPC::F23, -72}, 142 {PPC::F22, -80}, 143 {PPC::F21, -88}, 144 {PPC::F20, -96}, 145 {PPC::F19, -104}, 146 {PPC::F18, -112}, 147 {PPC::F17, -120}, 148 {PPC::F16, -128}, 149 {PPC::F15, -136}, 150 {PPC::F14, -144}, 151 152 // General register save area offsets. 153 {PPC::X31, -8}, 154 {PPC::X30, -16}, 155 {PPC::X29, -24}, 156 {PPC::X28, -32}, 157 {PPC::X27, -40}, 158 {PPC::X26, -48}, 159 {PPC::X25, -56}, 160 {PPC::X24, -64}, 161 {PPC::X23, -72}, 162 {PPC::X22, -80}, 163 {PPC::X21, -88}, 164 {PPC::X20, -96}, 165 {PPC::X19, -104}, 166 {PPC::X18, -112}, 167 {PPC::X17, -120}, 168 {PPC::X16, -128}, 169 {PPC::X15, -136}, 170 {PPC::X14, -144}, 171 172 // VRSAVE save area offset. 173 {PPC::VRSAVE, -4}, 174 175 // Vector register save area 176 {PPC::V31, -16}, 177 {PPC::V30, -32}, 178 {PPC::V29, -48}, 179 {PPC::V28, -64}, 180 {PPC::V27, -80}, 181 {PPC::V26, -96}, 182 {PPC::V25, -112}, 183 {PPC::V24, -128}, 184 {PPC::V23, -144}, 185 {PPC::V22, -160}, 186 {PPC::V21, -176}, 187 {PPC::V20, -192}}; 188 189 if (Subtarget.isPPC64()) { 190 NumEntries = array_lengthof(Offsets64); 191 192 return Offsets64; 193 } else { 194 NumEntries = array_lengthof(Offsets); 195 196 return Offsets; 197 } 198} 199 200/// RemoveVRSaveCode - We have found that this function does not need any code 201/// to manipulate the VRSAVE register, even though it uses vector registers. 202/// This can happen when the only registers used are known to be live in or out 203/// of the function. Remove all of the VRSAVE related code from the function. 204/// FIXME: The removal of the code results in a compile failure at -O0 when the 205/// function contains a function call, as the GPR containing original VRSAVE 206/// contents is spilled and reloaded around the call. Without the prolog code, 207/// the spill instruction refers to an undefined register. This code needs 208/// to account for all uses of that GPR. 209static void RemoveVRSaveCode(MachineInstr *MI) { 210 MachineBasicBlock *Entry = MI->getParent(); 211 MachineFunction *MF = Entry->getParent(); 212 213 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 214 MachineBasicBlock::iterator MBBI = MI; 215 ++MBBI; 216 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 217 MBBI->eraseFromParent(); 218 219 bool RemovedAllMTVRSAVEs = true; 220 // See if we can find and remove the MTVRSAVE instruction from all of the 221 // epilog blocks. 222 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 223 // If last instruction is a return instruction, add an epilogue 224 if (!I->empty() && I->back().isReturn()) { 225 bool FoundIt = false; 226 for (MBBI = I->end(); MBBI != I->begin(); ) { 227 --MBBI; 228 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 229 MBBI->eraseFromParent(); // remove it. 230 FoundIt = true; 231 break; 232 } 233 } 234 RemovedAllMTVRSAVEs &= FoundIt; 235 } 236 } 237 238 // If we found and removed all MTVRSAVE instructions, remove the read of 239 // VRSAVE as well. 240 if (RemovedAllMTVRSAVEs) { 241 MBBI = MI; 242 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 243 --MBBI; 244 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 245 MBBI->eraseFromParent(); 246 } 247 248 // Finally, nuke the UPDATE_VRSAVE. 249 MI->eraseFromParent(); 250} 251 252// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 253// instruction selector. Based on the vector registers that have been used, 254// transform this into the appropriate ORI instruction. 255static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 256 MachineFunction *MF = MI->getParent()->getParent(); 257 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 258 DebugLoc dl = MI->getDebugLoc(); 259 260 unsigned UsedRegMask = 0; 261 for (unsigned i = 0; i != 32; ++i) 262 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 263 UsedRegMask |= 1 << (31-i); 264 265 // Live in and live out values already must be in the mask, so don't bother 266 // marking them. 267 for (MachineRegisterInfo::livein_iterator 268 I = MF->getRegInfo().livein_begin(), 269 E = MF->getRegInfo().livein_end(); I != E; ++I) { 270 unsigned RegNo = TRI->getEncodingValue(I->first); 271 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 272 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 273 } 274 275 // Live out registers appear as use operands on return instructions. 276 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end(); 277 UsedRegMask != 0 && BI != BE; ++BI) { 278 const MachineBasicBlock &MBB = *BI; 279 if (MBB.empty() || !MBB.back().isReturn()) 280 continue; 281 const MachineInstr &Ret = MBB.back(); 282 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) { 283 const MachineOperand &MO = Ret.getOperand(I); 284 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg())) 285 continue; 286 unsigned RegNo = TRI->getEncodingValue(MO.getReg()); 287 UsedRegMask &= ~(1 << (31-RegNo)); 288 } 289 } 290 291 // If no registers are used, turn this into a copy. 292 if (UsedRegMask == 0) { 293 // Remove all VRSAVE code. 294 RemoveVRSaveCode(MI); 295 return; 296 } 297 298 unsigned SrcReg = MI->getOperand(1).getReg(); 299 unsigned DstReg = MI->getOperand(0).getReg(); 300 301 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 302 if (DstReg != SrcReg) 303 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 304 .addReg(SrcReg) 305 .addImm(UsedRegMask); 306 else 307 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 308 .addReg(SrcReg, RegState::Kill) 309 .addImm(UsedRegMask); 310 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 311 if (DstReg != SrcReg) 312 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 313 .addReg(SrcReg) 314 .addImm(UsedRegMask >> 16); 315 else 316 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 317 .addReg(SrcReg, RegState::Kill) 318 .addImm(UsedRegMask >> 16); 319 } else { 320 if (DstReg != SrcReg) 321 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 322 .addReg(SrcReg) 323 .addImm(UsedRegMask >> 16); 324 else 325 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 326 .addReg(SrcReg, RegState::Kill) 327 .addImm(UsedRegMask >> 16); 328 329 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 330 .addReg(DstReg, RegState::Kill) 331 .addImm(UsedRegMask & 0xFFFF); 332 } 333 334 // Remove the old UPDATE_VRSAVE instruction. 335 MI->eraseFromParent(); 336} 337 338static bool spillsCR(const MachineFunction &MF) { 339 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 340 return FuncInfo->isCRSpilled(); 341} 342 343static bool spillsVRSAVE(const MachineFunction &MF) { 344 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 345 return FuncInfo->isVRSAVESpilled(); 346} 347 348static bool hasSpills(const MachineFunction &MF) { 349 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 350 return FuncInfo->hasSpills(); 351} 352 353static bool hasNonRISpills(const MachineFunction &MF) { 354 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 355 return FuncInfo->hasNonRISpills(); 356} 357 358/// determineFrameLayout - Determine the size of the frame and maximum call 359/// frame size. 360unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF, 361 bool UpdateMF, 362 bool UseEstimate) const { 363 MachineFrameInfo *MFI = MF.getFrameInfo(); 364 365 // Get the number of bytes to allocate from the FrameInfo 366 unsigned FrameSize = 367 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize(); 368 369 // Get stack alignments. The frame must be aligned to the greatest of these: 370 unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI 371 unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame 372 unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1; 373 374 const PPCRegisterInfo *RegInfo = 375 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo()); 376 377 // If we are a leaf function, and use up to 224 bytes of stack space, 378 // don't have a frame pointer, calls, or dynamic alloca then we do not need 379 // to adjust the stack pointer (we fit in the Red Zone). 380 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate 381 // stackless code if all local vars are reg-allocated. 382 bool DisableRedZone = MF.getFunction()->getAttributes(). 383 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone); 384 if (!DisableRedZone && 385 (Subtarget.isPPC64() || // 32-bit SVR4, no stack- 386 !Subtarget.isSVR4ABI() || // allocated locals. 387 FrameSize == 0) && 388 FrameSize <= 224 && // Fits in red zone. 389 !MFI->hasVarSizedObjects() && // No dynamic alloca. 390 !MFI->adjustsStack() && // No calls. 391 !RegInfo->hasBasePointer(MF)) { // No special alignment. 392 // No need for frame 393 if (UpdateMF) 394 MFI->setStackSize(0); 395 return 0; 396 } 397 398 // Get the maximum call frame size of all the calls. 399 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 400 401 // Maximum call frame needs to be at least big enough for linkage area. 402 unsigned minCallFrameSize = getLinkageSize(Subtarget.isPPC64(), 403 Subtarget.isDarwinABI(), 404 Subtarget.isELFv2ABI()); 405 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 406 407 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 408 // that allocations will be aligned. 409 if (MFI->hasVarSizedObjects()) 410 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 411 412 // Update maximum call frame size. 413 if (UpdateMF) 414 MFI->setMaxCallFrameSize(maxCallFrameSize); 415 416 // Include call frame size in total. 417 FrameSize += maxCallFrameSize; 418 419 // Make sure the frame is aligned. 420 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 421 422 // Update frame info. 423 if (UpdateMF) 424 MFI->setStackSize(FrameSize); 425 426 return FrameSize; 427} 428 429// hasFP - Return true if the specified function actually has a dedicated frame 430// pointer register. 431bool PPCFrameLowering::hasFP(const MachineFunction &MF) const { 432 const MachineFrameInfo *MFI = MF.getFrameInfo(); 433 // FIXME: This is pretty much broken by design: hasFP() might be called really 434 // early, before the stack layout was calculated and thus hasFP() might return 435 // true or false here depending on the time of call. 436 return (MFI->getStackSize()) && needsFP(MF); 437} 438 439// needsFP - Return true if the specified function should have a dedicated frame 440// pointer register. This is true if the function has variable sized allocas or 441// if frame pointer elimination is disabled. 442bool PPCFrameLowering::needsFP(const MachineFunction &MF) const { 443 const MachineFrameInfo *MFI = MF.getFrameInfo(); 444 445 // Naked functions have no stack frame pushed, so we don't have a frame 446 // pointer. 447 if (MF.getFunction()->getAttributes().hasAttribute( 448 AttributeSet::FunctionIndex, Attribute::Naked)) 449 return false; 450 451 return MF.getTarget().Options.DisableFramePointerElim(MF) || 452 MFI->hasVarSizedObjects() || 453 (MF.getTarget().Options.GuaranteedTailCallOpt && 454 MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 455} 456 457void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const { 458 bool is31 = needsFP(MF); 459 unsigned FPReg = is31 ? PPC::R31 : PPC::R1; 460 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1; 461 462 const PPCRegisterInfo *RegInfo = 463 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo()); 464 bool HasBP = RegInfo->hasBasePointer(MF); 465 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg; 466 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg; 467 468 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); 469 BI != BE; ++BI) 470 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) { 471 --MBBI; 472 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) { 473 MachineOperand &MO = MBBI->getOperand(I); 474 if (!MO.isReg()) 475 continue; 476 477 switch (MO.getReg()) { 478 case PPC::FP: 479 MO.setReg(FPReg); 480 break; 481 case PPC::FP8: 482 MO.setReg(FP8Reg); 483 break; 484 case PPC::BP: 485 MO.setReg(BPReg); 486 break; 487 case PPC::BP8: 488 MO.setReg(BP8Reg); 489 break; 490 491 } 492 } 493 } 494} 495 496void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { 497 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 498 MachineBasicBlock::iterator MBBI = MBB.begin(); 499 MachineFrameInfo *MFI = MF.getFrameInfo(); 500 const PPCInstrInfo &TII = 501 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 502 const PPCRegisterInfo *RegInfo = 503 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo()); 504 505 MachineModuleInfo &MMI = MF.getMMI(); 506 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); 507 DebugLoc dl; 508 bool needsCFI = MMI.hasDebugInfo() || 509 MF.getFunction()->needsUnwindTableEntry(); 510 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_; 511 512 // Get processor type. 513 bool isPPC64 = Subtarget.isPPC64(); 514 // Get the ABI. 515 bool isDarwinABI = Subtarget.isDarwinABI(); 516 bool isSVR4ABI = Subtarget.isSVR4ABI(); 517 bool isELFv2ABI = Subtarget.isELFv2ABI(); 518 assert((isDarwinABI || isSVR4ABI) && 519 "Currently only Darwin and SVR4 ABIs are supported for PowerPC."); 520 521 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 522 // process it. 523 if (!isSVR4ABI) 524 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 525 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 526 HandleVRSaveUpdate(MBBI, TII); 527 break; 528 } 529 } 530 531 // Move MBBI back to the beginning of the function. 532 MBBI = MBB.begin(); 533 534 // Work out frame sizes. 535 unsigned FrameSize = determineFrameLayout(MF); 536 int NegFrameSize = -FrameSize; 537 if (!isInt<32>(NegFrameSize)) 538 llvm_unreachable("Unhandled stack size!"); 539 540 if (MFI->isFrameAddressTaken()) 541 replaceFPWithRealFP(MF); 542 543 // Check if the link register (LR) must be saved. 544 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 545 bool MustSaveLR = FI->mustSaveLR(); 546 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs(); 547 // Do we have a frame pointer and/or base pointer for this function? 548 bool HasFP = hasFP(MF); 549 bool HasBP = RegInfo->hasBasePointer(MF); 550 551 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1; 552 unsigned BPReg = RegInfo->getBaseRegister(MF); 553 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 554 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR; 555 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0; 556 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg 557 // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.) 558 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8 559 : PPC::MFLR ); 560 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD 561 : PPC::STW ); 562 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU 563 : PPC::STWU ); 564 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX 565 : PPC::STWUX); 566 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8 567 : PPC::LIS ); 568 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8 569 : PPC::ORI ); 570 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 571 : PPC::OR ); 572 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8 573 : PPC::SUBFC); 574 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8 575 : PPC::SUBFIC); 576 577 // Regarding this assert: Even though LR is saved in the caller's frame (i.e., 578 // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no 579 // Red Zone, an asynchronous event (a form of "callee") could claim a frame & 580 // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR. 581 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) && 582 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4."); 583 584 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 585 586 int FPOffset = 0; 587 if (HasFP) { 588 if (isSVR4ABI) { 589 MachineFrameInfo *FFI = MF.getFrameInfo(); 590 int FPIndex = FI->getFramePointerSaveIndex(); 591 assert(FPIndex && "No Frame Pointer Save Slot!"); 592 FPOffset = FFI->getObjectOffset(FPIndex); 593 } else { 594 FPOffset = 595 PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 596 } 597 } 598 599 int BPOffset = 0; 600 if (HasBP) { 601 if (isSVR4ABI) { 602 MachineFrameInfo *FFI = MF.getFrameInfo(); 603 int BPIndex = FI->getBasePointerSaveIndex(); 604 assert(BPIndex && "No Base Pointer Save Slot!"); 605 BPOffset = FFI->getObjectOffset(BPIndex); 606 } else { 607 BPOffset = 608 PPCFrameLowering::getBasePointerSaveOffset(isPPC64, 609 isDarwinABI, 610 isPIC); 611 } 612 } 613 614 // Get stack alignments. 615 unsigned MaxAlign = MFI->getMaxAlignment(); 616 if (HasBP && MaxAlign > 1) 617 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 618 "Invalid alignment!"); 619 620 // Frames of 32KB & larger require special handling because they cannot be 621 // indexed into with a simple STDU/STWU/STD/STW immediate offset operand. 622 bool isLargeFrame = !isInt<16>(NegFrameSize); 623 624 if (MustSaveLR) 625 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg); 626 627 assert((isPPC64 || MustSaveCRs.empty()) && 628 "Prologue CR saving supported only in 64-bit mode"); 629 630 if (!MustSaveCRs.empty()) { // will only occur for PPC64 631 // FIXME: In the ELFv2 ABI, we are not required to save all CR fields. 632 // If only one or two CR fields are clobbered, it could be more 633 // efficient to use mfocrf to selectively save just those fields. 634 MachineInstrBuilder MIB = 635 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg); 636 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 637 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); 638 } 639 640 if (HasFP) 641 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 642 BuildMI(MBB, MBBI, dl, StoreInst) 643 .addReg(FPReg) 644 .addImm(FPOffset) 645 .addReg(SPReg); 646 647 if (HasBP) 648 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 649 BuildMI(MBB, MBBI, dl, StoreInst) 650 .addReg(BPReg) 651 .addImm(BPOffset) 652 .addReg(SPReg); 653 654 if (MustSaveLR) 655 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 656 BuildMI(MBB, MBBI, dl, StoreInst) 657 .addReg(ScratchReg) 658 .addImm(LROffset) 659 .addReg(SPReg); 660 661 if (!MustSaveCRs.empty()) // will only occur for PPC64 662 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) 663 .addReg(TempReg, getKillRegState(true)) 664 .addImm(8) 665 .addReg(SPReg); 666 667 // Skip the rest if this is a leaf function & all spills fit in the Red Zone. 668 if (!FrameSize) return; 669 670 // Adjust stack pointer: r1 += NegFrameSize. 671 // If there is a preferred stack alignment, align R1 now 672 673 if (HasBP) { 674 // Save a copy of r1 as the base pointer. 675 BuildMI(MBB, MBBI, dl, OrInst, BPReg) 676 .addReg(SPReg) 677 .addReg(SPReg); 678 } 679 680 if (HasBP && MaxAlign > 1) { 681 if (isPPC64) 682 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg) 683 .addReg(SPReg) 684 .addImm(0) 685 .addImm(64 - Log2_32(MaxAlign)); 686 else // PPC32... 687 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg) 688 .addReg(SPReg) 689 .addImm(0) 690 .addImm(32 - Log2_32(MaxAlign)) 691 .addImm(31); 692 if (!isLargeFrame) { 693 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg) 694 .addReg(ScratchReg, RegState::Kill) 695 .addImm(NegFrameSize); 696 } else { 697 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg) 698 .addImm(NegFrameSize >> 16); 699 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg) 700 .addReg(TempReg, RegState::Kill) 701 .addImm(NegFrameSize & 0xFFFF); 702 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg) 703 .addReg(ScratchReg, RegState::Kill) 704 .addReg(TempReg, RegState::Kill); 705 } 706 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg) 707 .addReg(SPReg, RegState::Kill) 708 .addReg(SPReg) 709 .addReg(ScratchReg); 710 711 } else if (!isLargeFrame) { 712 BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg) 713 .addReg(SPReg) 714 .addImm(NegFrameSize) 715 .addReg(SPReg); 716 717 } else { 718 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 719 .addImm(NegFrameSize >> 16); 720 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 721 .addReg(ScratchReg, RegState::Kill) 722 .addImm(NegFrameSize & 0xFFFF); 723 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg) 724 .addReg(SPReg, RegState::Kill) 725 .addReg(SPReg) 726 .addReg(ScratchReg); 727 } 728 729 // Add Call Frame Information for the instructions we generated above. 730 if (needsCFI) { 731 unsigned CFIIndex; 732 733 if (HasBP) { 734 // Define CFA in terms of BP. Do this in preference to using FP/SP, 735 // because if the stack needed aligning then CFA won't be at a fixed 736 // offset from FP/SP. 737 unsigned Reg = MRI->getDwarfRegNum(BPReg, true); 738 CFIIndex = MMI.addFrameInst( 739 MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); 740 } else { 741 // Adjust the definition of CFA to account for the change in SP. 742 assert(NegFrameSize); 743 CFIIndex = MMI.addFrameInst( 744 MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize)); 745 } 746 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 747 .addCFIIndex(CFIIndex); 748 749 if (HasFP) { 750 // Describe where FP was saved, at a fixed offset from CFA. 751 unsigned Reg = MRI->getDwarfRegNum(FPReg, true); 752 CFIIndex = MMI.addFrameInst( 753 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset)); 754 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 755 .addCFIIndex(CFIIndex); 756 } 757 758 if (HasBP) { 759 // Describe where BP was saved, at a fixed offset from CFA. 760 unsigned Reg = MRI->getDwarfRegNum(BPReg, true); 761 CFIIndex = MMI.addFrameInst( 762 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset)); 763 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 764 .addCFIIndex(CFIIndex); 765 } 766 767 if (MustSaveLR) { 768 // Describe where LR was saved, at a fixed offset from CFA. 769 unsigned Reg = MRI->getDwarfRegNum(LRReg, true); 770 CFIIndex = MMI.addFrameInst( 771 MCCFIInstruction::createOffset(nullptr, Reg, LROffset)); 772 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 773 .addCFIIndex(CFIIndex); 774 } 775 } 776 777 // If there is a frame pointer, copy R1 into R31 778 if (HasFP) { 779 BuildMI(MBB, MBBI, dl, OrInst, FPReg) 780 .addReg(SPReg) 781 .addReg(SPReg); 782 783 if (!HasBP && needsCFI) { 784 // Change the definition of CFA from SP+offset to FP+offset, because SP 785 // will change at every alloca. 786 unsigned Reg = MRI->getDwarfRegNum(FPReg, true); 787 unsigned CFIIndex = MMI.addFrameInst( 788 MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); 789 790 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 791 .addCFIIndex(CFIIndex); 792 } 793 } 794 795 if (needsCFI) { 796 // Describe where callee saved registers were saved, at fixed offsets from 797 // CFA. 798 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 799 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 800 unsigned Reg = CSI[I].getReg(); 801 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 802 803 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just 804 // subregisters of CR2. We just need to emit a move of CR2. 805 if (PPC::CRBITRCRegClass.contains(Reg)) 806 continue; 807 808 // For SVR4, don't emit a move for the CR spill slot if we haven't 809 // spilled CRs. 810 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4) 811 && MustSaveCRs.empty()) 812 continue; 813 814 // For 64-bit SVR4 when we have spilled CRs, the spill location 815 // is SP+8, not a frame-relative slot. 816 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 817 // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for 818 // the whole CR word. In the ELFv2 ABI, every CR that was 819 // actually saved gets its own CFI record. 820 unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2; 821 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 822 nullptr, MRI->getDwarfRegNum(CRReg, true), 8)); 823 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 824 .addCFIIndex(CFIIndex); 825 continue; 826 } 827 828 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 829 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 830 nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); 831 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 832 .addCFIIndex(CFIIndex); 833 } 834 } 835} 836 837void PPCFrameLowering::emitEpilogue(MachineFunction &MF, 838 MachineBasicBlock &MBB) const { 839 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 840 assert(MBBI != MBB.end() && "Returning block has no terminator"); 841 const PPCInstrInfo &TII = 842 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 843 const PPCRegisterInfo *RegInfo = 844 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo()); 845 846 unsigned RetOpcode = MBBI->getOpcode(); 847 DebugLoc dl; 848 849 assert((RetOpcode == PPC::BLR || 850 RetOpcode == PPC::TCRETURNri || 851 RetOpcode == PPC::TCRETURNdi || 852 RetOpcode == PPC::TCRETURNai || 853 RetOpcode == PPC::TCRETURNri8 || 854 RetOpcode == PPC::TCRETURNdi8 || 855 RetOpcode == PPC::TCRETURNai8) && 856 "Can only insert epilog into returning blocks"); 857 858 // Get alignment info so we know how to restore the SP. 859 const MachineFrameInfo *MFI = MF.getFrameInfo(); 860 861 // Get the number of bytes allocated from the FrameInfo. 862 int FrameSize = MFI->getStackSize(); 863 864 // Get processor type. 865 bool isPPC64 = Subtarget.isPPC64(); 866 // Get the ABI. 867 bool isDarwinABI = Subtarget.isDarwinABI(); 868 bool isSVR4ABI = Subtarget.isSVR4ABI(); 869 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_; 870 871 // Check if the link register (LR) has been saved. 872 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 873 bool MustSaveLR = FI->mustSaveLR(); 874 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs(); 875 // Do we have a frame pointer and/or base pointer for this function? 876 bool HasFP = hasFP(MF); 877 bool HasBP = RegInfo->hasBasePointer(MF); 878 879 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1; 880 unsigned BPReg = RegInfo->getBaseRegister(MF); 881 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 882 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0; 883 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg 884 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8 885 : PPC::MTLR ); 886 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD 887 : PPC::LWZ ); 888 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8 889 : PPC::LIS ); 890 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8 891 : PPC::ORI ); 892 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8 893 : PPC::ADDI ); 894 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8 895 : PPC::ADD4 ); 896 897 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 898 899 int FPOffset = 0; 900 if (HasFP) { 901 if (isSVR4ABI) { 902 MachineFrameInfo *FFI = MF.getFrameInfo(); 903 int FPIndex = FI->getFramePointerSaveIndex(); 904 assert(FPIndex && "No Frame Pointer Save Slot!"); 905 FPOffset = FFI->getObjectOffset(FPIndex); 906 } else { 907 FPOffset = 908 PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 909 } 910 } 911 912 int BPOffset = 0; 913 if (HasBP) { 914 if (isSVR4ABI) { 915 MachineFrameInfo *FFI = MF.getFrameInfo(); 916 int BPIndex = FI->getBasePointerSaveIndex(); 917 assert(BPIndex && "No Base Pointer Save Slot!"); 918 BPOffset = FFI->getObjectOffset(BPIndex); 919 } else { 920 BPOffset = 921 PPCFrameLowering::getBasePointerSaveOffset(isPPC64, 922 isDarwinABI, 923 isPIC); 924 } 925 } 926 927 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 928 RetOpcode == PPC::TCRETURNdi || 929 RetOpcode == PPC::TCRETURNai || 930 RetOpcode == PPC::TCRETURNri8 || 931 RetOpcode == PPC::TCRETURNdi8 || 932 RetOpcode == PPC::TCRETURNai8; 933 934 if (UsesTCRet) { 935 int MaxTCRetDelta = FI->getTailCallSPDelta(); 936 MachineOperand &StackAdjust = MBBI->getOperand(1); 937 assert(StackAdjust.isImm() && "Expecting immediate value."); 938 // Adjust stack pointer. 939 int StackAdj = StackAdjust.getImm(); 940 int Delta = StackAdj - MaxTCRetDelta; 941 assert((Delta >= 0) && "Delta must be positive"); 942 if (MaxTCRetDelta>0) 943 FrameSize += (StackAdj +Delta); 944 else 945 FrameSize += StackAdj; 946 } 947 948 // Frames of 32KB & larger require special handling because they cannot be 949 // indexed into with a simple LD/LWZ immediate offset operand. 950 bool isLargeFrame = !isInt<16>(FrameSize); 951 952 if (FrameSize) { 953 // In the prologue, the loaded (or persistent) stack pointer value is offset 954 // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now. 955 956 // If this function contained a fastcc call and GuaranteedTailCallOpt is 957 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 958 // call which invalidates the stack pointer value in SP(0). So we use the 959 // value of R31 in this case. 960 if (FI->hasFastCall()) { 961 assert(HasFP && "Expecting a valid frame pointer."); 962 if (!isLargeFrame) { 963 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 964 .addReg(FPReg).addImm(FrameSize); 965 } else { 966 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 967 .addImm(FrameSize >> 16); 968 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 969 .addReg(ScratchReg, RegState::Kill) 970 .addImm(FrameSize & 0xFFFF); 971 BuildMI(MBB, MBBI, dl, AddInst) 972 .addReg(SPReg) 973 .addReg(FPReg) 974 .addReg(ScratchReg); 975 } 976 } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) { 977 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 978 .addReg(SPReg) 979 .addImm(FrameSize); 980 } else { 981 BuildMI(MBB, MBBI, dl, LoadInst, SPReg) 982 .addImm(0) 983 .addReg(SPReg); 984 } 985 986 } 987 988 if (MustSaveLR) 989 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg) 990 .addImm(LROffset) 991 .addReg(SPReg); 992 993 assert((isPPC64 || MustSaveCRs.empty()) && 994 "Epilogue CR restoring supported only in 64-bit mode"); 995 996 if (!MustSaveCRs.empty()) // will only occur for PPC64 997 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg) 998 .addImm(8) 999 .addReg(SPReg); 1000 1001 if (HasFP) 1002 BuildMI(MBB, MBBI, dl, LoadInst, FPReg) 1003 .addImm(FPOffset) 1004 .addReg(SPReg); 1005 1006 if (HasBP) 1007 BuildMI(MBB, MBBI, dl, LoadInst, BPReg) 1008 .addImm(BPOffset) 1009 .addReg(SPReg); 1010 1011 if (!MustSaveCRs.empty()) // will only occur for PPC64 1012 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 1013 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i]) 1014 .addReg(TempReg, getKillRegState(i == e-1)); 1015 1016 if (MustSaveLR) 1017 BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg); 1018 1019 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 1020 // call optimization 1021 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR && 1022 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 1023 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1024 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 1025 1026 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 1027 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 1028 .addReg(SPReg).addImm(CallerAllocatedAmt); 1029 } else { 1030 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 1031 .addImm(CallerAllocatedAmt >> 16); 1032 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 1033 .addReg(ScratchReg, RegState::Kill) 1034 .addImm(CallerAllocatedAmt & 0xFFFF); 1035 BuildMI(MBB, MBBI, dl, AddInst) 1036 .addReg(SPReg) 1037 .addReg(FPReg) 1038 .addReg(ScratchReg); 1039 } 1040 } else if (RetOpcode == PPC::TCRETURNdi) { 1041 MBBI = MBB.getLastNonDebugInstr(); 1042 MachineOperand &JumpTarget = MBBI->getOperand(0); 1043 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 1044 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1045 } else if (RetOpcode == PPC::TCRETURNri) { 1046 MBBI = MBB.getLastNonDebugInstr(); 1047 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1048 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 1049 } else if (RetOpcode == PPC::TCRETURNai) { 1050 MBBI = MBB.getLastNonDebugInstr(); 1051 MachineOperand &JumpTarget = MBBI->getOperand(0); 1052 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 1053 } else if (RetOpcode == PPC::TCRETURNdi8) { 1054 MBBI = MBB.getLastNonDebugInstr(); 1055 MachineOperand &JumpTarget = MBBI->getOperand(0); 1056 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 1057 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1058 } else if (RetOpcode == PPC::TCRETURNri8) { 1059 MBBI = MBB.getLastNonDebugInstr(); 1060 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1061 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 1062 } else if (RetOpcode == PPC::TCRETURNai8) { 1063 MBBI = MBB.getLastNonDebugInstr(); 1064 MachineOperand &JumpTarget = MBBI->getOperand(0); 1065 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 1066 } 1067} 1068 1069/// MustSaveLR - Return true if this function requires that we save the LR 1070/// register onto the stack in the prolog and restore it in the epilog of the 1071/// function. 1072static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 1073 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 1074 1075 // We need a save/restore of LR if there is any def of LR (which is 1076 // defined by calls, including the PIC setup sequence), or if there is 1077 // some use of the LR stack slot (e.g. for builtin_return_address). 1078 // (LR comes in 32 and 64 bit versions.) 1079 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 1080 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 1081} 1082 1083void 1084PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 1085 RegScavenger *) const { 1086 const PPCRegisterInfo *RegInfo = 1087 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo()); 1088 1089 // Save and clear the LR state. 1090 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1091 unsigned LR = RegInfo->getRARegister(); 1092 FI->setMustSaveLR(MustSaveLR(MF, LR)); 1093 MachineRegisterInfo &MRI = MF.getRegInfo(); 1094 MRI.setPhysRegUnused(LR); 1095 1096 // Save R31 if necessary 1097 int FPSI = FI->getFramePointerSaveIndex(); 1098 bool isPPC64 = Subtarget.isPPC64(); 1099 bool isDarwinABI = Subtarget.isDarwinABI(); 1100 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_; 1101 MachineFrameInfo *MFI = MF.getFrameInfo(); 1102 1103 // If the frame pointer save index hasn't been defined yet. 1104 if (!FPSI && needsFP(MF)) { 1105 // Find out what the fix offset of the frame pointer save area. 1106 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI); 1107 // Allocate the frame index for frame pointer save area. 1108 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 1109 // Save the result. 1110 FI->setFramePointerSaveIndex(FPSI); 1111 } 1112 1113 int BPSI = FI->getBasePointerSaveIndex(); 1114 if (!BPSI && RegInfo->hasBasePointer(MF)) { 1115 int BPOffset = getBasePointerSaveOffset(isPPC64, isDarwinABI, isPIC); 1116 // Allocate the frame index for the base pointer save area. 1117 BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true); 1118 // Save the result. 1119 FI->setBasePointerSaveIndex(BPSI); 1120 } 1121 1122 // Reserve stack space to move the linkage area to in case of a tail call. 1123 int TCSPDelta = 0; 1124 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1125 (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 1126 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 1127 } 1128 1129 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the 1130 // function uses CR 2, 3, or 4. 1131 if (!isPPC64 && !isDarwinABI && 1132 (MRI.isPhysRegUsed(PPC::CR2) || 1133 MRI.isPhysRegUsed(PPC::CR3) || 1134 MRI.isPhysRegUsed(PPC::CR4))) { 1135 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true); 1136 FI->setCRSpillFrameIndex(FrameIdx); 1137 } 1138} 1139 1140void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, 1141 RegScavenger *RS) const { 1142 // Early exit if not using the SVR4 ABI. 1143 if (!Subtarget.isSVR4ABI()) { 1144 addScavengingSpillSlot(MF, RS); 1145 return; 1146 } 1147 1148 // Get callee saved register information. 1149 MachineFrameInfo *FFI = MF.getFrameInfo(); 1150 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 1151 1152 // Early exit if no callee saved registers are modified! 1153 if (CSI.empty() && !needsFP(MF)) { 1154 addScavengingSpillSlot(MF, RS); 1155 return; 1156 } 1157 1158 unsigned MinGPR = PPC::R31; 1159 unsigned MinG8R = PPC::X31; 1160 unsigned MinFPR = PPC::F31; 1161 unsigned MinVR = PPC::V31; 1162 1163 bool HasGPSaveArea = false; 1164 bool HasG8SaveArea = false; 1165 bool HasFPSaveArea = false; 1166 bool HasVRSAVESaveArea = false; 1167 bool HasVRSaveArea = false; 1168 1169 SmallVector<CalleeSavedInfo, 18> GPRegs; 1170 SmallVector<CalleeSavedInfo, 18> G8Regs; 1171 SmallVector<CalleeSavedInfo, 18> FPRegs; 1172 SmallVector<CalleeSavedInfo, 18> VRegs; 1173 1174 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1175 unsigned Reg = CSI[i].getReg(); 1176 if (PPC::GPRCRegClass.contains(Reg)) { 1177 HasGPSaveArea = true; 1178 1179 GPRegs.push_back(CSI[i]); 1180 1181 if (Reg < MinGPR) { 1182 MinGPR = Reg; 1183 } 1184 } else if (PPC::G8RCRegClass.contains(Reg)) { 1185 HasG8SaveArea = true; 1186 1187 G8Regs.push_back(CSI[i]); 1188 1189 if (Reg < MinG8R) { 1190 MinG8R = Reg; 1191 } 1192 } else if (PPC::F8RCRegClass.contains(Reg)) { 1193 HasFPSaveArea = true; 1194 1195 FPRegs.push_back(CSI[i]); 1196 1197 if (Reg < MinFPR) { 1198 MinFPR = Reg; 1199 } 1200 } else if (PPC::CRBITRCRegClass.contains(Reg) || 1201 PPC::CRRCRegClass.contains(Reg)) { 1202 ; // do nothing, as we already know whether CRs are spilled 1203 } else if (PPC::VRSAVERCRegClass.contains(Reg)) { 1204 HasVRSAVESaveArea = true; 1205 } else if (PPC::VRRCRegClass.contains(Reg)) { 1206 HasVRSaveArea = true; 1207 1208 VRegs.push_back(CSI[i]); 1209 1210 if (Reg < MinVR) { 1211 MinVR = Reg; 1212 } 1213 } else { 1214 llvm_unreachable("Unknown RegisterClass!"); 1215 } 1216 } 1217 1218 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 1219 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); 1220 1221 int64_t LowerBound = 0; 1222 1223 // Take into account stack space reserved for tail calls. 1224 int TCSPDelta = 0; 1225 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1226 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 1227 LowerBound = TCSPDelta; 1228 } 1229 1230 // The Floating-point register save area is right below the back chain word 1231 // of the previous stack frame. 1232 if (HasFPSaveArea) { 1233 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 1234 int FI = FPRegs[i].getFrameIdx(); 1235 1236 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1237 } 1238 1239 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8; 1240 } 1241 1242 // Check whether the frame pointer register is allocated. If so, make sure it 1243 // is spilled to the correct offset. 1244 if (needsFP(MF)) { 1245 HasGPSaveArea = true; 1246 1247 int FI = PFI->getFramePointerSaveIndex(); 1248 assert(FI && "No Frame Pointer Save Slot!"); 1249 1250 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1251 } 1252 1253 const PPCRegisterInfo *RegInfo = 1254 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo()); 1255 if (RegInfo->hasBasePointer(MF)) { 1256 HasGPSaveArea = true; 1257 1258 int FI = PFI->getBasePointerSaveIndex(); 1259 assert(FI && "No Base Pointer Save Slot!"); 1260 1261 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1262 } 1263 1264 // General register save area starts right below the Floating-point 1265 // register save area. 1266 if (HasGPSaveArea || HasG8SaveArea) { 1267 // Move general register save area spill slots down, taking into account 1268 // the size of the Floating-point register save area. 1269 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 1270 int FI = GPRegs[i].getFrameIdx(); 1271 1272 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1273 } 1274 1275 // Move general register save area spill slots down, taking into account 1276 // the size of the Floating-point register save area. 1277 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 1278 int FI = G8Regs[i].getFrameIdx(); 1279 1280 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1281 } 1282 1283 unsigned MinReg = 1284 std::min<unsigned>(TRI->getEncodingValue(MinGPR), 1285 TRI->getEncodingValue(MinG8R)); 1286 1287 if (Subtarget.isPPC64()) { 1288 LowerBound -= (31 - MinReg + 1) * 8; 1289 } else { 1290 LowerBound -= (31 - MinReg + 1) * 4; 1291 } 1292 } 1293 1294 // For 32-bit only, the CR save area is below the general register 1295 // save area. For 64-bit SVR4, the CR save area is addressed relative 1296 // to the stack pointer and hence does not need an adjustment here. 1297 // Only CR2 (the first nonvolatile spilled) has an associated frame 1298 // index so that we have a single uniform save area. 1299 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) { 1300 // Adjust the frame index of the CR spill slot. 1301 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1302 unsigned Reg = CSI[i].getReg(); 1303 1304 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2) 1305 // Leave Darwin logic as-is. 1306 || (!Subtarget.isSVR4ABI() && 1307 (PPC::CRBITRCRegClass.contains(Reg) || 1308 PPC::CRRCRegClass.contains(Reg)))) { 1309 int FI = CSI[i].getFrameIdx(); 1310 1311 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1312 } 1313 } 1314 1315 LowerBound -= 4; // The CR save area is always 4 bytes long. 1316 } 1317 1318 if (HasVRSAVESaveArea) { 1319 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1320 // which have the VRSAVE register class? 1321 // Adjust the frame index of the VRSAVE spill slot. 1322 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1323 unsigned Reg = CSI[i].getReg(); 1324 1325 if (PPC::VRSAVERCRegClass.contains(Reg)) { 1326 int FI = CSI[i].getFrameIdx(); 1327 1328 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1329 } 1330 } 1331 1332 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 1333 } 1334 1335 if (HasVRSaveArea) { 1336 // Insert alignment padding, we need 16-byte alignment. 1337 LowerBound = (LowerBound - 15) & ~(15); 1338 1339 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1340 int FI = VRegs[i].getFrameIdx(); 1341 1342 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1343 } 1344 } 1345 1346 addScavengingSpillSlot(MF, RS); 1347} 1348 1349void 1350PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF, 1351 RegScavenger *RS) const { 1352 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 1353 // a large stack, which will require scavenging a register to materialize a 1354 // large offset. 1355 1356 // We need to have a scavenger spill slot for spills if the frame size is 1357 // large. In case there is no free register for large-offset addressing, 1358 // this slot is used for the necessary emergency spill. Also, we need the 1359 // slot for dynamic stack allocations. 1360 1361 // The scavenger might be invoked if the frame offset does not fit into 1362 // the 16-bit immediate. We don't know the complete frame size here 1363 // because we've not yet computed callee-saved register spills or the 1364 // needed alignment padding. 1365 unsigned StackSize = determineFrameLayout(MF, false, true); 1366 MachineFrameInfo *MFI = MF.getFrameInfo(); 1367 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) || 1368 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) { 1369 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 1370 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 1371 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 1372 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1373 RC->getAlignment(), 1374 false)); 1375 1376 // Might we have over-aligned allocas? 1377 bool HasAlVars = MFI->hasVarSizedObjects() && 1378 MFI->getMaxAlignment() > getStackAlignment(); 1379 1380 // These kinds of spills might need two registers. 1381 if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars) 1382 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1383 RC->getAlignment(), 1384 false)); 1385 1386 } 1387} 1388 1389bool 1390PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1391 MachineBasicBlock::iterator MI, 1392 const std::vector<CalleeSavedInfo> &CSI, 1393 const TargetRegisterInfo *TRI) const { 1394 1395 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1396 // Return false otherwise to maintain pre-existing behavior. 1397 if (!Subtarget.isSVR4ABI()) 1398 return false; 1399 1400 MachineFunction *MF = MBB.getParent(); 1401 const PPCInstrInfo &TII = 1402 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1403 DebugLoc DL; 1404 bool CRSpilled = false; 1405 MachineInstrBuilder CRMIB; 1406 1407 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1408 unsigned Reg = CSI[i].getReg(); 1409 // Only Darwin actually uses the VRSAVE register, but it can still appear 1410 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on 1411 // Darwin, ignore it. 1412 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI()) 1413 continue; 1414 1415 // CR2 through CR4 are the nonvolatile CR fields. 1416 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; 1417 1418 // Add the callee-saved register as live-in; it's killed at the spill. 1419 MBB.addLiveIn(Reg); 1420 1421 if (CRSpilled && IsCRField) { 1422 CRMIB.addReg(Reg, RegState::ImplicitKill); 1423 continue; 1424 } 1425 1426 // Insert the spill to the stack frame. 1427 if (IsCRField) { 1428 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>(); 1429 if (Subtarget.isPPC64()) { 1430 // The actual spill will happen at the start of the prologue. 1431 FuncInfo->addMustSaveCR(Reg); 1432 } else { 1433 CRSpilled = true; 1434 FuncInfo->setSpillsCR(); 1435 1436 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have 1437 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot. 1438 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12) 1439 .addReg(Reg, RegState::ImplicitKill); 1440 1441 MBB.insert(MI, CRMIB); 1442 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW)) 1443 .addReg(PPC::R12, 1444 getKillRegState(true)), 1445 CSI[i].getFrameIdx())); 1446 } 1447 } else { 1448 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1449 TII.storeRegToStackSlot(MBB, MI, Reg, true, 1450 CSI[i].getFrameIdx(), RC, TRI); 1451 } 1452 } 1453 return true; 1454} 1455 1456static void 1457restoreCRs(bool isPPC64, bool is31, 1458 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, 1459 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1460 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) { 1461 1462 MachineFunction *MF = MBB.getParent(); 1463 const PPCInstrInfo &TII = 1464 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1465 DebugLoc DL; 1466 unsigned RestoreOp, MoveReg; 1467 1468 if (isPPC64) 1469 // This is handled during epilogue generation. 1470 return; 1471 else { 1472 // 32-bit: FP-relative 1473 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), 1474 PPC::R12), 1475 CSI[CSIIndex].getFrameIdx())); 1476 RestoreOp = PPC::MTOCRF; 1477 MoveReg = PPC::R12; 1478 } 1479 1480 if (CR2Spilled) 1481 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2) 1482 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled))); 1483 1484 if (CR3Spilled) 1485 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3) 1486 .addReg(MoveReg, getKillRegState(!CR4Spilled))); 1487 1488 if (CR4Spilled) 1489 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4) 1490 .addReg(MoveReg, getKillRegState(true))); 1491} 1492 1493void PPCFrameLowering:: 1494eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1495 MachineBasicBlock::iterator I) const { 1496 const PPCInstrInfo &TII = 1497 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 1498 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1499 I->getOpcode() == PPC::ADJCALLSTACKUP) { 1500 // Add (actually subtract) back the amount the callee popped on return. 1501 if (int CalleeAmt = I->getOperand(1).getImm()) { 1502 bool is64Bit = Subtarget.isPPC64(); 1503 CalleeAmt *= -1; 1504 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 1505 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 1506 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 1507 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 1508 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 1509 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 1510 MachineInstr *MI = I; 1511 DebugLoc dl = MI->getDebugLoc(); 1512 1513 if (isInt<16>(CalleeAmt)) { 1514 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) 1515 .addReg(StackReg, RegState::Kill) 1516 .addImm(CalleeAmt); 1517 } else { 1518 MachineBasicBlock::iterator MBBI = I; 1519 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 1520 .addImm(CalleeAmt >> 16); 1521 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 1522 .addReg(TmpReg, RegState::Kill) 1523 .addImm(CalleeAmt & 0xFFFF); 1524 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) 1525 .addReg(StackReg, RegState::Kill) 1526 .addReg(TmpReg); 1527 } 1528 } 1529 } 1530 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 1531 MBB.erase(I); 1532} 1533 1534bool 1535PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1536 MachineBasicBlock::iterator MI, 1537 const std::vector<CalleeSavedInfo> &CSI, 1538 const TargetRegisterInfo *TRI) const { 1539 1540 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1541 // Return false otherwise to maintain pre-existing behavior. 1542 if (!Subtarget.isSVR4ABI()) 1543 return false; 1544 1545 MachineFunction *MF = MBB.getParent(); 1546 const PPCInstrInfo &TII = 1547 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1548 bool CR2Spilled = false; 1549 bool CR3Spilled = false; 1550 bool CR4Spilled = false; 1551 unsigned CSIIndex = 0; 1552 1553 // Initialize insertion-point logic; we will be restoring in reverse 1554 // order of spill. 1555 MachineBasicBlock::iterator I = MI, BeforeI = I; 1556 bool AtStart = I == MBB.begin(); 1557 1558 if (!AtStart) 1559 --BeforeI; 1560 1561 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1562 unsigned Reg = CSI[i].getReg(); 1563 1564 // Only Darwin actually uses the VRSAVE register, but it can still appear 1565 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on 1566 // Darwin, ignore it. 1567 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI()) 1568 continue; 1569 1570 if (Reg == PPC::CR2) { 1571 CR2Spilled = true; 1572 // The spill slot is associated only with CR2, which is the 1573 // first nonvolatile spilled. Save it here. 1574 CSIIndex = i; 1575 continue; 1576 } else if (Reg == PPC::CR3) { 1577 CR3Spilled = true; 1578 continue; 1579 } else if (Reg == PPC::CR4) { 1580 CR4Spilled = true; 1581 continue; 1582 } else { 1583 // When we first encounter a non-CR register after seeing at 1584 // least one CR register, restore all spilled CRs together. 1585 if ((CR2Spilled || CR3Spilled || CR4Spilled) 1586 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 1587 bool is31 = needsFP(*MF); 1588 restoreCRs(Subtarget.isPPC64(), is31, 1589 CR2Spilled, CR3Spilled, CR4Spilled, 1590 MBB, I, CSI, CSIIndex); 1591 CR2Spilled = CR3Spilled = CR4Spilled = false; 1592 } 1593 1594 // Default behavior for non-CR saves. 1595 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1596 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(), 1597 RC, TRI); 1598 assert(I != MBB.begin() && 1599 "loadRegFromStackSlot didn't insert any code!"); 1600 } 1601 1602 // Insert in reverse order. 1603 if (AtStart) 1604 I = MBB.begin(); 1605 else { 1606 I = BeforeI; 1607 ++I; 1608 } 1609 } 1610 1611 // If we haven't yet spilled the CRs, do so now. 1612 if (CR2Spilled || CR3Spilled || CR4Spilled) { 1613 bool is31 = needsFP(*MF); 1614 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled, 1615 MBB, I, CSI, CSIIndex); 1616 } 1617 1618 return true; 1619} 1620