NVPTXInstrInfo.h revision 303975
1184610Salfred//===- NVPTXInstrInfo.h - NVPTX Instruction Information----------*- C++ -*-===// 2184610Salfred// 3184610Salfred// The LLVM Compiler Infrastructure 4184610Salfred// 5184610Salfred// This file is distributed under the niversity of Illinois Open Source 6184610Salfred// License. See LICENSE.TXT for details. 7184610Salfred// 8184610Salfred//===----------------------------------------------------------------------===// 9184610Salfred// 10184610Salfred// This file contains the NVPTX implementation of the TargetInstrInfo class. 11184610Salfred// 12184610Salfred//===----------------------------------------------------------------------===// 13184610Salfred 14184610Salfred#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXINSTRINFO_H 15184610Salfred#define LLVM_LIB_TARGET_NVPTX_NVPTXINSTRINFO_H 16184610Salfred 17184610Salfred#include "NVPTX.h" 18184610Salfred#include "NVPTXRegisterInfo.h" 19184610Salfred#include "llvm/Target/TargetInstrInfo.h" 20184610Salfred 21184610Salfred#define GET_INSTRINFO_HEADER 22184610Salfred#include "NVPTXGenInstrInfo.inc" 23184610Salfred 24184610Salfrednamespace llvm { 25184610Salfred 26184610Salfredclass NVPTXInstrInfo : public NVPTXGenInstrInfo { 27184610Salfred const NVPTXRegisterInfo RegInfo; 28184610Salfred virtual void anchor(); 29184610Salfredpublic: 30184610Salfred explicit NVPTXInstrInfo(); 31184610Salfred 32184610Salfred const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; } 33184610Salfred 34184610Salfred /* The following virtual functions are used in register allocation. 35190174Sthompsa * They are not implemented because the existing interface and the logic 36187170Sthompsa * at the caller side do not work for the elementized vector load and store. 37184610Salfred * 38184610Salfred * virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 39184610Salfred * int &FrameIndex) const; 40184610Salfred * virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 41184610Salfred * int &FrameIndex) const; 42184610Salfred * virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 43184610Salfred * MachineBasicBlock::iterator MBBI, 44184610Salfred * unsigned SrcReg, bool isKill, int FrameIndex, 45184610Salfred * const TargetRegisterClass *RC) const; 46184610Salfred * virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 47184610Salfred * MachineBasicBlock::iterator MBBI, 48184610Salfred * unsigned DestReg, int FrameIndex, 49184610Salfred * const TargetRegisterClass *RC) const; 50184610Salfred */ 51184610Salfred 52184610Salfred void copyPhysReg( 53184610Salfred MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, 54184610Salfred unsigned DestReg, unsigned SrcReg, bool KillSrc) const override; 55184610Salfred virtual bool isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, 56184610Salfred unsigned &DestReg) const; 57184610Salfred bool isLoadInstr(const MachineInstr &MI, unsigned &AddrSpace) const; 58184610Salfred bool isStoreInstr(const MachineInstr &MI, unsigned &AddrSpace) const; 59184610Salfred 60184610Salfred virtual bool CanTailMerge(const MachineInstr *MI) const; 61184610Salfred // Branch analysis. 62184610Salfred bool AnalyzeBranch( 63184610Salfred MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, 64184610Salfred SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override; 65184610Salfred unsigned RemoveBranch(MachineBasicBlock &MBB) const override; 66184610Salfred unsigned InsertBranch( 67184610Salfred MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, 68184610Salfred ArrayRef<MachineOperand> Cond, DebugLoc DL) const override; 69184610Salfred unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const { 70184610Salfred return MI.getOperand(2).getImm(); 71184610Salfred } 72184610Salfred 73184610Salfred}; 74184610Salfred 75184610Salfred} // namespace llvm 76184610Salfred 77184610Salfred#endif 78184610Salfred