NVPTXISelLowering.h revision 249423 
1//===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that NVPTX uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef NVPTXISELLOWERING_H
16#define NVPTXISELLOWERING_H
17
18#include "NVPTX.h"
19#include "NVPTXSubtarget.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/Target/TargetLowering.h"
22
23namespace llvm {
24namespace NVPTXISD {
25enum NodeType {
26  // Start the numbering from where ISD NodeType finishes.
27  FIRST_NUMBER = ISD::BUILTIN_OP_END,
28  Wrapper,
29  CALL,
30  RET_FLAG,
31  LOAD_PARAM,
32  NVBuiltin,
33  DeclareParam,
34  DeclareScalarParam,
35  DeclareRetParam,
36  DeclareRet,
37  DeclareScalarRet,
38  LoadParam,
39  StoreParam,
40  StoreParamS32, // to sext and store a <32bit value, not used currently
41  StoreParamU32, // to zext and store a <32bit value, not used currently
42  MoveToParam,
43  PrintCall,
44  PrintCallUni,
45  CallArgBegin,
46  CallArg,
47  LastCallArg,
48  CallArgEnd,
49  CallVoid,
50  CallVal,
51  CallSymbol,
52  Prototype,
53  MoveParam,
54  MoveRetval,
55  MoveToRetval,
56  StoreRetval,
57  PseudoUseParam,
58  RETURN,
59  CallSeqBegin,
60  CallSeqEnd,
61  Dummy,
62
63  LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE,
64  LoadV4,
65  LDGV2, // LDG.v2
66  LDGV4, // LDG.v4
67  LDUV2, // LDU.v2
68  LDUV4, // LDU.v4
69  StoreV2,
70  StoreV4
71};
72}
73
74//===--------------------------------------------------------------------===//
75// TargetLowering Implementation
76//===--------------------------------------------------------------------===//
77class NVPTXTargetLowering : public TargetLowering {
78public:
79  explicit NVPTXTargetLowering(NVPTXTargetMachine &TM);
80  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
81
82  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
83  SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
84                             SelectionDAG &DAG) const;
85
86  virtual const char *getTargetNodeName(unsigned Opcode) const;
87
88  bool isTypeSupportedInIntrinsic(MVT VT) const;
89
90  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
91                          unsigned Intrinsic) const;
92
93  /// isLegalAddressingMode - Return true if the addressing mode represented
94  /// by AM is legal for this target, for a load/store of the specified type
95  /// Used to guide target specific optimizations, like loop strength
96  /// reduction (LoopStrengthReduce.cpp) and memory optimization for
97  /// address mode (CodeGenPrepare.cpp)
98  virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
99
100  /// getFunctionAlignment - Return the Log2 alignment of this function.
101  virtual unsigned getFunctionAlignment(const Function *F) const;
102
103  virtual EVT getSetCCResultType(EVT VT) const {
104    if (VT.isVector())
105      return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
106    return MVT::i1;
107  }
108
109  ConstraintType getConstraintType(const std::string &Constraint) const;
110  std::pair<unsigned, const TargetRegisterClass *>
111  getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
112
113  virtual SDValue LowerFormalArguments(
114      SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
115      const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG,
116      SmallVectorImpl<SDValue> &InVals) const;
117
118  virtual SDValue
119  LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const;
120
121  std::string getPrototype(Type *, const ArgListTy &,
122                           const SmallVectorImpl<ISD::OutputArg> &,
123                           unsigned retAlignment) const;
124
125  virtual SDValue
126  LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
127              const SmallVectorImpl<ISD::OutputArg> &Outs,
128              const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl,
129              SelectionDAG &DAG) const;
130
131  virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
132                                            std::vector<SDValue> &Ops,
133                                            SelectionDAG &DAG) const;
134
135  NVPTXTargetMachine *nvTM;
136
137  // PTX always uses 32-bit shift amounts
138  virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
139
140  virtual bool shouldSplitVectorElementType(EVT VT) const;
141
142private:
143  const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here
144
145  SDValue getExtSymb(SelectionDAG &DAG, const char *name, int idx,
146                     EVT = MVT::i32) const;
147  SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT = MVT::i32) const;
148  SDValue getParamHelpSymbol(SelectionDAG &DAG, int idx);
149
150  SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
151
152  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
153  SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
154
155  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
156  SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
157  SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
158
159  virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
160                                  SelectionDAG &DAG) const;
161};
162} // namespace llvm
163
164#endif // NVPTXISELLOWERING_H
165