MipsSEFrameLowering.cpp revision 261991
1//===-- MipsSEFrameLowering.cpp - Mips32/64 Frame Information -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips32/64 implementation of TargetFrameLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "MipsSEFrameLowering.h" 15#include "MCTargetDesc/MipsBaseInfo.h" 16#include "MipsAnalyzeImmediate.h" 17#include "MipsMachineFunction.h" 18#include "MipsSEInstrInfo.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineModuleInfo.h" 23#include "llvm/CodeGen/MachineRegisterInfo.h" 24#include "llvm/CodeGen/RegisterScavenging.h" 25#include "llvm/IR/DataLayout.h" 26#include "llvm/IR/Function.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Target/TargetOptions.h" 29 30using namespace llvm; 31 32namespace { 33typedef MachineBasicBlock::iterator Iter; 34 35static std::pair<unsigned, unsigned> getMFHiLoOpc(unsigned Src) { 36 if (Mips::ACC64RegClass.contains(Src)) 37 return std::make_pair((unsigned)Mips::PseudoMFHI, 38 (unsigned)Mips::PseudoMFLO); 39 40 if (Mips::ACC64DSPRegClass.contains(Src)) 41 return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP); 42 43 if (Mips::ACC128RegClass.contains(Src)) 44 return std::make_pair((unsigned)Mips::PseudoMFHI64, 45 (unsigned)Mips::PseudoMFLO64); 46 47 return std::make_pair(0, 0); 48} 49 50/// Helper class to expand pseudos. 51class ExpandPseudo { 52public: 53 ExpandPseudo(MachineFunction &MF); 54 bool expand(); 55 56private: 57 bool expandInstr(MachineBasicBlock &MBB, Iter I); 58 void expandLoadCCond(MachineBasicBlock &MBB, Iter I); 59 void expandStoreCCond(MachineBasicBlock &MBB, Iter I); 60 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize); 61 void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc, 62 unsigned MFLoOpc, unsigned RegSize); 63 bool expandCopy(MachineBasicBlock &MBB, Iter I); 64 bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc, 65 unsigned MFLoOpc); 66 67 MachineFunction &MF; 68 MachineRegisterInfo &MRI; 69}; 70} 71 72ExpandPseudo::ExpandPseudo(MachineFunction &MF_) 73 : MF(MF_), MRI(MF.getRegInfo()) {} 74 75bool ExpandPseudo::expand() { 76 bool Expanded = false; 77 78 for (MachineFunction::iterator BB = MF.begin(), BBEnd = MF.end(); 79 BB != BBEnd; ++BB) 80 for (Iter I = BB->begin(), End = BB->end(); I != End;) 81 Expanded |= expandInstr(*BB, I++); 82 83 return Expanded; 84} 85 86bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) { 87 switch(I->getOpcode()) { 88 case Mips::LOAD_CCOND_DSP: 89 expandLoadCCond(MBB, I); 90 break; 91 case Mips::STORE_CCOND_DSP: 92 expandStoreCCond(MBB, I); 93 break; 94 case Mips::LOAD_ACC64: 95 case Mips::LOAD_ACC64DSP: 96 expandLoadACC(MBB, I, 4); 97 break; 98 case Mips::LOAD_ACC128: 99 expandLoadACC(MBB, I, 8); 100 break; 101 case Mips::STORE_ACC64: 102 expandStoreACC(MBB, I, Mips::PseudoMFHI, Mips::PseudoMFLO, 4); 103 break; 104 case Mips::STORE_ACC64DSP: 105 expandStoreACC(MBB, I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4); 106 break; 107 case Mips::STORE_ACC128: 108 expandStoreACC(MBB, I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8); 109 break; 110 case TargetOpcode::COPY: 111 if (!expandCopy(MBB, I)) 112 return false; 113 break; 114 default: 115 return false; 116 } 117 118 MBB.erase(I); 119 return true; 120} 121 122void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) { 123 // load $vr, FI 124 // copy ccond, $vr 125 126 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); 127 128 const MipsSEInstrInfo &TII = 129 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); 130 const MipsRegisterInfo &RegInfo = 131 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); 132 133 const TargetRegisterClass *RC = RegInfo.intRegClass(4); 134 unsigned VR = MRI.createVirtualRegister(RC); 135 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex(); 136 137 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); 138 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst) 139 .addReg(VR, RegState::Kill); 140} 141 142void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) { 143 // copy $vr, ccond 144 // store $vr, FI 145 146 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); 147 148 const MipsSEInstrInfo &TII = 149 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); 150 const MipsRegisterInfo &RegInfo = 151 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); 152 153 const TargetRegisterClass *RC = RegInfo.intRegClass(4); 154 unsigned VR = MRI.createVirtualRegister(RC); 155 unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex(); 156 157 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) 158 .addReg(Src, getKillRegState(I->getOperand(0).isKill())); 159 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); 160} 161 162void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I, 163 unsigned RegSize) { 164 // load $vr0, FI 165 // copy lo, $vr0 166 // load $vr1, FI + 4 167 // copy hi, $vr1 168 169 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); 170 171 const MipsSEInstrInfo &TII = 172 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); 173 const MipsRegisterInfo &RegInfo = 174 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); 175 176 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); 177 unsigned VR0 = MRI.createVirtualRegister(RC); 178 unsigned VR1 = MRI.createVirtualRegister(RC); 179 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex(); 180 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); 181 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); 182 DebugLoc DL = I->getDebugLoc(); 183 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY); 184 185 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0); 186 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill); 187 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); 188 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); 189} 190 191void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I, 192 unsigned MFHiOpc, unsigned MFLoOpc, 193 unsigned RegSize) { 194 // mflo $vr0, src 195 // store $vr0, FI 196 // mfhi $vr1, src 197 // store $vr1, FI + 4 198 199 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); 200 201 const MipsSEInstrInfo &TII = 202 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); 203 const MipsRegisterInfo &RegInfo = 204 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); 205 206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); 207 unsigned VR0 = MRI.createVirtualRegister(RC); 208 unsigned VR1 = MRI.createVirtualRegister(RC); 209 unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex(); 210 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill()); 211 DebugLoc DL = I->getDebugLoc(); 212 213 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); 214 TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0); 215 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); 216 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); 217} 218 219bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) { 220 unsigned Src = I->getOperand(1).getReg(); 221 std::pair<unsigned, unsigned> Opcodes = getMFHiLoOpc(Src); 222 223 if (!Opcodes.first) 224 return false; 225 226 return expandCopyACC(MBB, I, Opcodes.first, Opcodes.second); 227} 228 229bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I, 230 unsigned MFHiOpc, unsigned MFLoOpc) { 231 // mflo $vr0, src 232 // copy dst_lo, $vr0 233 // mfhi $vr1, src 234 // copy dst_hi, $vr1 235 236 const MipsSEInstrInfo &TII = 237 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); 238 const MipsRegisterInfo &RegInfo = 239 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); 240 241 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg(); 242 unsigned VRegSize = RegInfo.getMinimalPhysRegClass(Dst)->getSize() / 2; 243 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); 244 unsigned VR0 = MRI.createVirtualRegister(RC); 245 unsigned VR1 = MRI.createVirtualRegister(RC); 246 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill()); 247 unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo); 248 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi); 249 DebugLoc DL = I->getDebugLoc(); 250 251 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); 252 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo) 253 .addReg(VR0, RegState::Kill); 254 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); 255 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi) 256 .addReg(VR1, RegState::Kill); 257 return true; 258} 259 260unsigned MipsSEFrameLowering::ehDataReg(unsigned I) const { 261 static const unsigned EhDataReg[] = { 262 Mips::A0, Mips::A1, Mips::A2, Mips::A3 263 }; 264 static const unsigned EhDataReg64[] = { 265 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64 266 }; 267 268 return STI.isABI_N64() ? EhDataReg64[I] : EhDataReg[I]; 269} 270 271void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { 272 MachineBasicBlock &MBB = MF.front(); 273 MachineFrameInfo *MFI = MF.getFrameInfo(); 274 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 275 276 const MipsSEInstrInfo &TII = 277 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); 278 const MipsRegisterInfo &RegInfo = 279 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); 280 281 MachineBasicBlock::iterator MBBI = MBB.begin(); 282 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 283 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; 284 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 285 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 286 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 287 288 // First, compute final stack size. 289 uint64_t StackSize = MFI->getStackSize(); 290 291 // No need to allocate space on the stack. 292 if (StackSize == 0 && !MFI->adjustsStack()) return; 293 294 MachineModuleInfo &MMI = MF.getMMI(); 295 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); 296 MachineLocation DstML, SrcML; 297 298 // Adjust stack. 299 TII.adjustStackPtr(SP, -StackSize, MBB, MBBI); 300 301 // emit ".cfi_def_cfa_offset StackSize" 302 MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol(); 303 BuildMI(MBB, MBBI, dl, 304 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel); 305 MMI.addFrameInst( 306 MCCFIInstruction::createDefCfaOffset(AdjustSPLabel, -StackSize)); 307 308 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 309 310 if (CSI.size()) { 311 // Find the instruction past the last instruction that saves a callee-saved 312 // register to the stack. 313 for (unsigned i = 0; i < CSI.size(); ++i) 314 ++MBBI; 315 316 // Iterate over list of callee-saved registers and emit .cfi_offset 317 // directives. 318 MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol(); 319 BuildMI(MBB, MBBI, dl, 320 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel); 321 322 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(), 323 E = CSI.end(); I != E; ++I) { 324 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx()); 325 unsigned Reg = I->getReg(); 326 327 // If Reg is a double precision register, emit two cfa_offsets, 328 // one for each of the paired single precision registers. 329 if (Mips::AFGR64RegClass.contains(Reg)) { 330 unsigned Reg0 = 331 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true); 332 unsigned Reg1 = 333 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true); 334 335 if (!STI.isLittle()) 336 std::swap(Reg0, Reg1); 337 338 MMI.addFrameInst( 339 MCCFIInstruction::createOffset(CSLabel, Reg0, Offset)); 340 MMI.addFrameInst( 341 MCCFIInstruction::createOffset(CSLabel, Reg1, Offset + 4)); 342 } else { 343 // Reg is either in GPR32 or FGR32. 344 MMI.addFrameInst(MCCFIInstruction::createOffset( 345 CSLabel, MRI->getDwarfRegNum(Reg, 1), Offset)); 346 } 347 } 348 } 349 350 if (MipsFI->callsEhReturn()) { 351 const TargetRegisterClass *RC = STI.isABI_N64() ? 352 &Mips::GPR64RegClass : &Mips::GPR32RegClass; 353 354 // Insert instructions that spill eh data registers. 355 for (int I = 0; I < 4; ++I) { 356 if (!MBB.isLiveIn(ehDataReg(I))) 357 MBB.addLiveIn(ehDataReg(I)); 358 TII.storeRegToStackSlot(MBB, MBBI, ehDataReg(I), false, 359 MipsFI->getEhDataRegFI(I), RC, &RegInfo); 360 } 361 362 // Emit .cfi_offset directives for eh data registers. 363 MCSymbol *CSLabel2 = MMI.getContext().CreateTempSymbol(); 364 BuildMI(MBB, MBBI, dl, 365 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel2); 366 for (int I = 0; I < 4; ++I) { 367 int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I)); 368 unsigned Reg = MRI->getDwarfRegNum(ehDataReg(I), true); 369 MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel2, Reg, Offset)); 370 } 371 } 372 373 // if framepointer enabled, set it to point to the stack pointer. 374 if (hasFP(MF)) { 375 // Insert instruction "move $fp, $sp" at this location. 376 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO); 377 378 // emit ".cfi_def_cfa_register $fp" 379 MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol(); 380 BuildMI(MBB, MBBI, dl, 381 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel); 382 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister( 383 SetFPLabel, MRI->getDwarfRegNum(FP, true))); 384 } 385} 386 387void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF, 388 MachineBasicBlock &MBB) const { 389 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 390 MachineFrameInfo *MFI = MF.getFrameInfo(); 391 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 392 393 const MipsSEInstrInfo &TII = 394 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); 395 const MipsRegisterInfo &RegInfo = 396 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); 397 398 DebugLoc dl = MBBI->getDebugLoc(); 399 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; 400 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 401 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 402 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 403 404 // if framepointer enabled, restore the stack pointer. 405 if (hasFP(MF)) { 406 // Find the first instruction that restores a callee-saved register. 407 MachineBasicBlock::iterator I = MBBI; 408 409 for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i) 410 --I; 411 412 // Insert instruction "move $sp, $fp" at this location. 413 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO); 414 } 415 416 if (MipsFI->callsEhReturn()) { 417 const TargetRegisterClass *RC = STI.isABI_N64() ? 418 &Mips::GPR64RegClass : &Mips::GPR32RegClass; 419 420 // Find first instruction that restores a callee-saved register. 421 MachineBasicBlock::iterator I = MBBI; 422 for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i) 423 --I; 424 425 // Insert instructions that restore eh data registers. 426 for (int J = 0; J < 4; ++J) { 427 TII.loadRegFromStackSlot(MBB, I, ehDataReg(J), MipsFI->getEhDataRegFI(J), 428 RC, &RegInfo); 429 } 430 } 431 432 // Get the number of bytes from FrameInfo 433 uint64_t StackSize = MFI->getStackSize(); 434 435 if (!StackSize) 436 return; 437 438 // Adjust stack. 439 TII.adjustStackPtr(SP, StackSize, MBB, MBBI); 440} 441 442bool MipsSEFrameLowering:: 443spillCalleeSavedRegisters(MachineBasicBlock &MBB, 444 MachineBasicBlock::iterator MI, 445 const std::vector<CalleeSavedInfo> &CSI, 446 const TargetRegisterInfo *TRI) const { 447 MachineFunction *MF = MBB.getParent(); 448 MachineBasicBlock *EntryBlock = MF->begin(); 449 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 450 451 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 452 // Add the callee-saved register as live-in. Do not add if the register is 453 // RA and return address is taken, because it has already been added in 454 // method MipsTargetLowering::LowerRETURNADDR. 455 // It's killed at the spill, unless the register is RA and return address 456 // is taken. 457 unsigned Reg = CSI[i].getReg(); 458 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64) 459 && MF->getFrameInfo()->isReturnAddressTaken(); 460 if (!IsRAAndRetAddrIsTaken) 461 EntryBlock->addLiveIn(Reg); 462 463 // Insert the spill to the stack frame. 464 bool IsKill = !IsRAAndRetAddrIsTaken; 465 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 466 TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, 467 CSI[i].getFrameIdx(), RC, TRI); 468 } 469 470 return true; 471} 472 473bool 474MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { 475 const MachineFrameInfo *MFI = MF.getFrameInfo(); 476 477 // Reserve call frame if the size of the maximum call frame fits into 16-bit 478 // immediate field and there are no variable sized objects on the stack. 479 // Make sure the second register scavenger spill slot can be accessed with one 480 // instruction. 481 return isInt<16>(MFI->getMaxCallFrameSize() + getStackAlignment()) && 482 !MFI->hasVarSizedObjects(); 483} 484 485// Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions 486void MipsSEFrameLowering:: 487eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 488 MachineBasicBlock::iterator I) const { 489 const MipsSEInstrInfo &TII = 490 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); 491 492 if (!hasReservedCallFrame(MF)) { 493 int64_t Amount = I->getOperand(0).getImm(); 494 495 if (I->getOpcode() == Mips::ADJCALLSTACKDOWN) 496 Amount = -Amount; 497 498 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; 499 TII.adjustStackPtr(SP, Amount, MBB, I); 500 } 501 502 MBB.erase(I); 503} 504 505void MipsSEFrameLowering:: 506processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 507 RegScavenger *RS) const { 508 MachineRegisterInfo &MRI = MF.getRegInfo(); 509 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 510 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 511 512 // Mark $fp as used if function has dedicated frame pointer. 513 if (hasFP(MF)) 514 MRI.setPhysRegUsed(FP); 515 516 // Create spill slots for eh data registers if function calls eh_return. 517 if (MipsFI->callsEhReturn()) 518 MipsFI->createEhDataRegsFI(); 519 520 // Expand pseudo instructions which load, store or copy accumulators. 521 // Add an emergency spill slot if a pseudo was expanded. 522 if (ExpandPseudo(MF).expand()) { 523 // The spill slot should be half the size of the accumulator. If target is 524 // mips64, it should be 64-bit, otherwise it should be 32-bt. 525 const TargetRegisterClass *RC = STI.hasMips64() ? 526 &Mips::GPR64RegClass : &Mips::GPR32RegClass; 527 int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(), 528 RC->getAlignment(), false); 529 RS->addScavengingFrameIndex(FI); 530 } 531 532 // Set scavenging frame index if necessary. 533 uint64_t MaxSPOffset = MF.getInfo<MipsFunctionInfo>()->getIncomingArgSize() + 534 estimateStackSize(MF); 535 536 if (isInt<16>(MaxSPOffset)) 537 return; 538 539 const TargetRegisterClass *RC = STI.isABI_N64() ? 540 &Mips::GPR64RegClass : &Mips::GPR32RegClass; 541 int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(), 542 RC->getAlignment(), false); 543 RS->addScavengingFrameIndex(FI); 544} 545 546const MipsFrameLowering * 547llvm::createMipsSEFrameLowering(const MipsSubtarget &ST) { 548 return new MipsSEFrameLowering(ST); 549} 550