1223017Sdim//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9223017Sdim// 10223017Sdim// This file contains the Mips implementation of the TargetInstrInfo class. 11223017Sdim// 12223017Sdim//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed 15193323Sed//===----------------------------------------------------------------------===// 16193323Sed// Mips profiles and nodes 17193323Sed//===----------------------------------------------------------------------===// 18193323Sed 19193323Seddef SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20218893Sdimdef SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21221345Sdim SDTCisSameAs<1, 2>, 22221345Sdim SDTCisSameAs<3, 4>, 23221345Sdim SDTCisInt<4>]>; 24193323Seddef SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25193323Seddef SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26261991Sdimdef SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>; 27261991Sdimdef SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 28261991Sdim SDTCisInt<1>, SDTCisSameAs<1, 2>]>; 29249423Sdimdef SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>, 30249423Sdim SDTCisSameAs<1, 2>]>; 31249423Sdimdef SDT_MipsMAddMSub : SDTypeProfile<1, 3, 32249423Sdim [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 33249423Sdim SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 34249423Sdimdef SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 35193323Sed 36223017Sdimdef SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 37223017Sdim 38226633Sdimdef SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 39224145Sdim 40226633Sdimdef SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41226633Sdim SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 42226633Sdimdef SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 43226633Sdim SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 44226633Sdim SDTCisSameAs<0, 4>]>; 45226633Sdim 46239462Sdimdef SDTMipsLoadLR : SDTypeProfile<1, 2, 47239462Sdim [SDTCisInt<0>, SDTCisPtrTy<1>, 48239462Sdim SDTCisSameAs<0, 2>]>; 49239462Sdim 50193323Sed// Call 51218893Sdimdef MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 52218893Sdim [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 53205407Srdivacky SDNPVariadic]>; 54193323Sed 55243830Sdim// Tail call 56243830Sdimdef MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 57243830Sdim [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 58243830Sdim 59218893Sdim// Hi and Lo nodes are used to handle global addresses. Used on 60218893Sdim// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 61193323Sed// static model. (nothing to do with Mips Registers Hi and Lo) 62193323Seddef MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 63193323Seddef MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 64193323Seddef MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 65193323Sed 66223017Sdim// TlsGd node is used to handle General Dynamic TLS 67223017Sdimdef MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 68223017Sdim 69223017Sdim// TprelHi and TprelLo nodes are used to handle Local Exec TLS 70223017Sdimdef MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 71223017Sdimdef MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 72223017Sdim 73223017Sdim// Thread pointer 74223017Sdimdef MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 75223017Sdim 76193323Sed// Return 77249423Sdimdef MipsRet : SDNode<"MipsISD::Ret", SDTNone, 78249423Sdim [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 79193323Sed 80296417Sdimdef MipsERet : SDNode<"MipsISD::ERet", SDTNone, 81296417Sdim [SDNPHasChain, SDNPOptInGlue, SDNPSideEffect]>; 82296417Sdim 83193323Sed// These are target-independent nodes, but have target-specific formats. 84193323Seddef callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 85243830Sdim [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 86193323Seddef callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 87243830Sdim [SDNPHasChain, SDNPSideEffect, 88243830Sdim SDNPOptInGlue, SDNPOutGlue]>; 89193323Sed 90261991Sdim// Nodes used to extract LO/HI registers. 91261991Sdimdef MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>; 92261991Sdimdef MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>; 93249423Sdim 94249423Sdim// Node used to insert 32-bit integers to LOHI register pair. 95261991Sdimdef MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>; 96249423Sdim 97249423Sdim// Mult nodes. 98249423Sdimdef MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>; 99249423Sdimdef MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>; 100249423Sdim 101218893Sdim// MAdd*/MSub* nodes 102249423Sdimdef MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>; 103249423Sdimdef MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>; 104249423Sdimdef MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>; 105249423Sdimdef MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>; 106193323Sed 107221345Sdim// DivRem(u) nodes 108249423Sdimdef MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>; 109249423Sdimdef MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>; 110261991Sdimdef MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, 111261991Sdim [SDNPOutGlue]>; 112249423Sdimdef MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, 113221345Sdim [SDNPOutGlue]>; 114221345Sdim 115223017Sdim// Target constant nodes that are not part of any isel patterns and remain 116223017Sdim// unchanged can cause instructions with illegal operands to be emitted. 117223017Sdim// Wrapper node patterns give the instruction selector a chance to replace 118223017Sdim// target constant nodes that would otherwise remain unchanged with ADDiu 119223017Sdim// nodes. Without these wrapper node patterns, the following conditional move 120261991Sdim// instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 121234353Sdim// compiled: 122223017Sdim// movn %got(d)($gp), %got(c)($gp), $4 123223017Sdim// This instruction is illegal since movn can take only register operands. 124223017Sdim 125234353Sdimdef MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 126223017Sdim 127243830Sdimdef MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 128226633Sdim 129226633Sdimdef MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 130226633Sdimdef MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 131226633Sdim 132239462Sdimdef MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 133239462Sdim [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 134239462Sdimdef MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 135239462Sdim [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 136239462Sdimdef MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 137239462Sdim [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 138239462Sdimdef MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 139239462Sdim [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 140239462Sdimdef MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 141239462Sdim [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 142239462Sdimdef MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 143239462Sdim [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 144239462Sdimdef MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 145239462Sdim [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 146239462Sdimdef MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 147239462Sdim [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 148239462Sdim 149193323Sed//===----------------------------------------------------------------------===// 150193323Sed// Mips Instruction Predicate Definitions. 151193323Sed//===----------------------------------------------------------------------===// 152276479Sdimdef HasMips2 : Predicate<"Subtarget->hasMips2()">, 153276479Sdim AssemblerPredicate<"FeatureMips2">; 154276479Sdimdef HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">, 155276479Sdim AssemblerPredicate<"FeatureMips3_32">; 156276479Sdimdef HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">, 157276479Sdim AssemblerPredicate<"FeatureMips3_32r2">; 158276479Sdimdef HasMips3 : Predicate<"Subtarget->hasMips3()">, 159276479Sdim AssemblerPredicate<"FeatureMips3">; 160276479Sdimdef HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">, 161276479Sdim AssemblerPredicate<"FeatureMips4_32">; 162280031Sdimdef NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">, 163296417Sdim AssemblerPredicate<"!FeatureMips4_32">; 164276479Sdimdef HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">, 165276479Sdim AssemblerPredicate<"FeatureMips4_32r2">; 166276479Sdimdef HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">, 167276479Sdim AssemblerPredicate<"FeatureMips5_32r2">; 168276479Sdimdef HasMips32 : Predicate<"Subtarget->hasMips32()">, 169234982Sdim AssemblerPredicate<"FeatureMips32">; 170276479Sdimdef HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">, 171234982Sdim AssemblerPredicate<"FeatureMips32r2">; 172296417Sdimdef HasMips32r5 : Predicate<"Subtarget->hasMips32r5()">, 173296417Sdim AssemblerPredicate<"FeatureMips32r5">; 174276479Sdimdef HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">, 175276479Sdim AssemblerPredicate<"FeatureMips32r6">; 176276479Sdimdef NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">, 177276479Sdim AssemblerPredicate<"!FeatureMips32r6">; 178276479Sdimdef IsGP64bit : Predicate<"Subtarget->isGP64bit()">, 179276479Sdim AssemblerPredicate<"FeatureGP64Bit">; 180276479Sdimdef IsGP32bit : Predicate<"!Subtarget->isGP64bit()">, 181276479Sdim AssemblerPredicate<"!FeatureGP64Bit">; 182276479Sdimdef HasMips64 : Predicate<"Subtarget->hasMips64()">, 183234982Sdim AssemblerPredicate<"FeatureMips64">; 184296417Sdimdef NotMips64 : Predicate<"!Subtarget->hasMips64()">, 185296417Sdim AssemblerPredicate<"!FeatureMips64">; 186276479Sdimdef HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">, 187234982Sdim AssemblerPredicate<"FeatureMips64r2">; 188276479Sdimdef HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">, 189276479Sdim AssemblerPredicate<"FeatureMips64r6">; 190276479Sdimdef NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">, 191276479Sdim AssemblerPredicate<"!FeatureMips64r6">; 192288943Sdimdef HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">, 193288943Sdim AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">; 194296417Sdimdef HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">, 195296417Sdim AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">; 196276479Sdimdef InMips16Mode : Predicate<"Subtarget->inMips16Mode()">, 197239462Sdim AssemblerPredicate<"FeatureMips16">; 198276479Sdimdef HasCnMips : Predicate<"Subtarget->hasCnMips()">, 199276479Sdim AssemblerPredicate<"FeatureCnMips">; 200288943Sdimdef RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; 201288943Sdimdef RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">; 202276479Sdimdef NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">; 203276479Sdimdef HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">, 204249423Sdim AssemblerPredicate<"!FeatureMips16">; 205276479Sdimdef NotDSP : Predicate<"!Subtarget->hasDSP()">; 206276479Sdimdef InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">, 207261991Sdim AssemblerPredicate<"FeatureMicroMips">; 208276479Sdimdef NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">, 209261991Sdim AssemblerPredicate<"!FeatureMicroMips">; 210276479Sdimdef IsLE : Predicate<"Subtarget->isLittle()">; 211276479Sdimdef IsBE : Predicate<"!Subtarget->isLittle()">; 212276479Sdimdef IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; 213296417Sdimdef UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">; 214296417Sdimdef HasEVA : Predicate<"Subtarget->hasEVA()">, 215296417Sdim AssemblerPredicate<"FeatureEVA,FeatureMips32r2">; 216296417Sdimdef HasMSA : Predicate<"Subtarget->hasMSA()">, 217296417Sdim AssemblerPredicate<"FeatureMSA">; 218193323Sed 219296417Sdim 220276479Sdim//===----------------------------------------------------------------------===// 221276479Sdim// Mips GPR size adjectives. 222276479Sdim// They are mutually exclusive. 223276479Sdim//===----------------------------------------------------------------------===// 224276479Sdim 225276479Sdimclass GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; } 226276479Sdimclass GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; } 227276479Sdim 228276479Sdim//===----------------------------------------------------------------------===// 229276479Sdim// Mips ISA/ASE membership and instruction group membership adjectives. 230276479Sdim// They are mutually exclusive. 231276479Sdim//===----------------------------------------------------------------------===// 232276479Sdim 233276479Sdim// FIXME: I'd prefer to use additive predicates to build the instruction sets 234276479Sdim// but we are short on assembler feature bits at the moment. Using a 235276479Sdim// subtractive predicate will hopefully keep us under the 32 predicate 236276479Sdim// limit long enough to develop an alternative way to handle P1||P2 237276479Sdim// predicates. 238280031Sdimclass ISA_MIPS1_NOT_4_32 { 239280031Sdim list<Predicate> InsnPredicates = [NotMips4_32]; 240280031Sdim} 241276479Sdimclass ISA_MIPS1_NOT_32R6_64R6 { 242276479Sdim list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6]; 243239462Sdim} 244276479Sdimclass ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; } 245276479Sdimclass ISA_MIPS2_NOT_32R6_64R6 { 246276479Sdim list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6]; 247276479Sdim} 248276479Sdimclass ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; } 249276479Sdimclass ISA_MIPS3_NOT_32R6_64R6 { 250276479Sdim list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6]; 251276479Sdim} 252276479Sdimclass ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; } 253276479Sdimclass ISA_MIPS32_NOT_32R6_64R6 { 254276479Sdim list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6]; 255276479Sdim} 256276479Sdimclass ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; } 257276479Sdimclass ISA_MIPS32R2_NOT_32R6_64R6 { 258276479Sdim list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6]; 259276479Sdim} 260296417Sdimclass ISA_MIPS32R5 { list<Predicate> InsnPredicates = [HasMips32r5]; } 261276479Sdimclass ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; } 262276479Sdimclass ISA_MIPS64_NOT_64R6 { 263276479Sdim list<Predicate> InsnPredicates = [HasMips64, NotMips64r6]; 264276479Sdim} 265276479Sdimclass ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; } 266276479Sdimclass ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; } 267276479Sdimclass ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; } 268296417Sdimclass ISA_MICROMIPS { list<Predicate> InsnPredicates = [InMicroMips]; } 269288943Sdimclass ISA_MICROMIPS32R6 { 270288943Sdim list<Predicate> InsnPredicates = [HasMicroMips32r6]; 271288943Sdim} 272296417Sdimclass ISA_MICROMIPS64R6 { 273296417Sdim list<Predicate> InsnPredicates = [HasMicroMips64r6]; 274296417Sdim} 275296417Sdimclass ISA_MICROMIPS32_NOT_MIPS32R6 { 276296417Sdim list<Predicate> InsnPredicates = [InMicroMips, NotMips32r6]; 277296417Sdim} 278239462Sdim 279296417Sdimclass INSN_EVA { list<Predicate> InsnPredicates = [HasEVA]; } 280296417Sdimclass INSN_EVA_NOT_32R6_64R6 { 281296417Sdim list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6, HasEVA]; 282296417Sdim} 283296417Sdim 284276479Sdim// The portions of MIPS-III that were also added to MIPS32 285276479Sdimclass INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; } 286276479Sdim 287276479Sdim// The portions of MIPS-III that were also added to MIPS32 but were removed in 288276479Sdim// MIPS32r6 and MIPS64r6. 289276479Sdimclass INSN_MIPS3_32_NOT_32R6_64R6 { 290276479Sdim list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6]; 291276479Sdim} 292276479Sdim 293276479Sdim// The portions of MIPS-III that were also added to MIPS32 294276479Sdimclass INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; } 295276479Sdim 296276479Sdim// The portions of MIPS-IV that were also added to MIPS32 but were removed in 297276479Sdim// MIPS32r6 and MIPS64r6. 298276479Sdimclass INSN_MIPS4_32_NOT_32R6_64R6 { 299276479Sdim list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6]; 300276479Sdim} 301276479Sdim 302276479Sdim// The portions of MIPS-IV that were also added to MIPS32r2 but were removed in 303276479Sdim// MIPS32r6 and MIPS64r6. 304276479Sdimclass INSN_MIPS4_32R2_NOT_32R6_64R6 { 305276479Sdim list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6]; 306276479Sdim} 307276479Sdim 308276479Sdim// The portions of MIPS-V that were also added to MIPS32r2 but were removed in 309276479Sdim// MIPS32r6 and MIPS64r6. 310276479Sdimclass INSN_MIPS5_32R2_NOT_32R6_64R6 { 311276479Sdim list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6]; 312276479Sdim} 313276479Sdim 314296417Sdimclass ASE_CNMIPS { 315296417Sdim list<Predicate> InsnPredicates = [HasCnMips]; 316296417Sdim} 317296417Sdim 318296417Sdimclass ASE_MSA { 319296417Sdim list<Predicate> InsnPredicates = [HasMSA]; 320296417Sdim} 321296417Sdim 322296417Sdimclass ASE_MSA_NOT_MSA64 { 323296417Sdim list<Predicate> InsnPredicates = [HasMSA, NotMips64]; 324296417Sdim} 325296417Sdim 326296417Sdimclass ASE_MSA64 { 327296417Sdim list<Predicate> InsnPredicates = [HasMSA, HasMips64]; 328296417Sdim} 329296417Sdim 330296417Sdim// Class used for separating microMIPSr6 and microMIPS (r3) instruction. 331296417Sdim// It can be used only on instructions that doesn't inherit PredicateControl. 332296417Sdimclass ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl { 333296417Sdim let InsnPredicates = [InMicroMips, NotMips32r6, NotMips64r6]; 334296417Sdim} 335296417Sdim 336276479Sdim//===----------------------------------------------------------------------===// 337276479Sdim 338276479Sdimclass MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl { 339276479Sdim let EncodingPredicates = [HasStdEnc]; 340276479Sdim} 341276479Sdim 342276479Sdimclass MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> : 343276479Sdim InstAlias<Asm, Result, Emit>, PredicateControl; 344276479Sdim 345249423Sdimclass IsCommutable { 346249423Sdim bit isCommutable = 1; 347249423Sdim} 348249423Sdim 349243830Sdimclass IsBranch { 350243830Sdim bit isBranch = 1; 351243830Sdim} 352243830Sdim 353243830Sdimclass IsReturn { 354243830Sdim bit isReturn = 1; 355243830Sdim} 356243830Sdim 357243830Sdimclass IsCall { 358243830Sdim bit isCall = 1; 359243830Sdim} 360243830Sdim 361243830Sdimclass IsTailCall { 362243830Sdim bit isCall = 1; 363243830Sdim bit isTerminator = 1; 364243830Sdim bit isReturn = 1; 365243830Sdim bit isBarrier = 1; 366243830Sdim bit hasExtraSrcRegAllocReq = 1; 367243830Sdim bit isCodeGenOnly = 1; 368243830Sdim} 369243830Sdim 370243830Sdimclass IsAsCheapAsAMove { 371243830Sdim bit isAsCheapAsAMove = 1; 372243830Sdim} 373243830Sdim 374243830Sdimclass NeverHasSideEffects { 375280031Sdim bit hasSideEffects = 0; 376243830Sdim} 377243830Sdim 378193323Sed//===----------------------------------------------------------------------===// 379239462Sdim// Instruction format superclass 380239462Sdim//===----------------------------------------------------------------------===// 381239462Sdim 382239462Sdiminclude "MipsInstrFormats.td" 383239462Sdim 384239462Sdim//===----------------------------------------------------------------------===// 385193323Sed// Mips Operand, Complex Patterns and Transformations Definitions. 386193323Sed//===----------------------------------------------------------------------===// 387193323Sed 388296417Sdimclass ConstantSImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []> 389296417Sdim : AsmOperandClass { 390296417Sdim let Name = "ConstantSImm" # Bits; 391296417Sdim let RenderMethod = "addImmOperands"; 392296417Sdim let PredicateMethod = "isConstantSImm<" # Bits # ">"; 393296417Sdim let SuperClasses = Supers; 394296417Sdim let DiagnosticType = "SImm" # Bits; 395296417Sdim} 396296417Sdim 397296417Sdimclass ConstantUImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [], 398296417Sdim int Offset = 0> : AsmOperandClass { 399296417Sdim let Name = "ConstantUImm" # Bits # "_" # Offset; 400296417Sdim let RenderMethod = "addConstantUImmOperands<" # Bits # ", " # Offset # ">"; 401296417Sdim let PredicateMethod = "isConstantUImm<" # Bits # ", " # Offset # ">"; 402296417Sdim let SuperClasses = Supers; 403296417Sdim let DiagnosticType = "UImm" # Bits # "_" # Offset; 404296417Sdim} 405296417Sdim 406296417Sdimdef ConstantUImm10AsmOperandClass 407296417Sdim : ConstantUImmAsmOperandClass<10, []>; 408296417Sdimdef ConstantUImm8AsmOperandClass 409296417Sdim : ConstantUImmAsmOperandClass<8, [ConstantUImm10AsmOperandClass]>; 410296417Sdimdef ConstantUImm7AsmOperandClass 411296417Sdim : ConstantUImmAsmOperandClass<7, [ConstantUImm8AsmOperandClass]>; 412296417Sdimdef ConstantUImm6AsmOperandClass 413296417Sdim : ConstantUImmAsmOperandClass<6, [ConstantUImm7AsmOperandClass]>; 414296417Sdimdef ConstantSImm6AsmOperandClass 415296417Sdim : ConstantSImmAsmOperandClass<6, [ConstantUImm7AsmOperandClass]>; 416296417Sdimdef ConstantUImm5Plus1AsmOperandClass 417296417Sdim : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 1>; 418296417Sdimdef ConstantUImm5Plus32AsmOperandClass 419296417Sdim : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 32>; 420296417Sdimdef ConstantUImm5Plus33AsmOperandClass 421296417Sdim : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 33>; 422296417Sdimdef ConstantUImm5Plus32NormalizeAsmOperandClass 423296417Sdim : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 32> { 424296417Sdim let Name = "ConstantUImm5_32_Norm"; 425296417Sdim // We must also subtract 32 when we render the operand. 426296417Sdim let RenderMethod = "addConstantUImmOperands<5, 32, -32>"; 427296417Sdim} 428296417Sdimdef ConstantUImm5Lsl2AsmOperandClass : AsmOperandClass { 429296417Sdim let Name = "UImm5Lsl2"; 430296417Sdim let RenderMethod = "addImmOperands"; 431296417Sdim let PredicateMethod = "isScaledUImm<5, 2>"; 432296417Sdim let SuperClasses = [ConstantUImm6AsmOperandClass]; 433296417Sdim let DiagnosticType = "UImm5_Lsl2"; 434296417Sdim} 435296417Sdimdef ConstantUImm5ReportUImm6AsmOperandClass 436296417Sdim : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass]> { 437296417Sdim let Name = "ConstantUImm5_0_Report_UImm6"; 438296417Sdim let DiagnosticType = "UImm5_0_Report_UImm6"; 439296417Sdim} 440296417Sdimdef ConstantUImm5AsmOperandClass 441296417Sdim : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass]>; 442296417Sdimdef ConstantUImm4AsmOperandClass 443296417Sdim : ConstantUImmAsmOperandClass< 444296417Sdim 4, [ConstantUImm5AsmOperandClass, 445296417Sdim ConstantUImm5Plus32AsmOperandClass, 446296417Sdim ConstantUImm5Plus32NormalizeAsmOperandClass]>; 447296417Sdimdef ConstantUImm3AsmOperandClass 448296417Sdim : ConstantUImmAsmOperandClass<3, [ConstantUImm4AsmOperandClass]>; 449296417Sdimdef ConstantUImm2Plus1AsmOperandClass 450296417Sdim : ConstantUImmAsmOperandClass<2, [ConstantUImm3AsmOperandClass], 1>; 451296417Sdimdef ConstantUImm2AsmOperandClass 452296417Sdim : ConstantUImmAsmOperandClass<2, [ConstantUImm3AsmOperandClass]>; 453296417Sdimdef ConstantUImm1AsmOperandClass 454296417Sdim : ConstantUImmAsmOperandClass<1, [ConstantUImm2AsmOperandClass]>; 455296417Sdimdef ConstantImmzAsmOperandClass : AsmOperandClass { 456296417Sdim let Name = "ConstantImmz"; 457296417Sdim let RenderMethod = "addConstantUImmOperands<1>"; 458296417Sdim let PredicateMethod = "isConstantImmz"; 459296417Sdim let SuperClasses = [ConstantUImm1AsmOperandClass]; 460296417Sdim let DiagnosticType = "Immz"; 461296417Sdim} 462296417Sdim 463276479Sdimdef MipsJumpTargetAsmOperand : AsmOperandClass { 464276479Sdim let Name = "JumpTarget"; 465280031Sdim let ParserMethod = "parseJumpTarget"; 466276479Sdim let PredicateMethod = "isImm"; 467276479Sdim let RenderMethod = "addImmOperands"; 468276479Sdim} 469276479Sdim 470193323Sed// Instruction operand types 471234353Sdimdef jmptarget : Operand<OtherVT> { 472234353Sdim let EncoderMethod = "getJumpTargetOpValue"; 473276479Sdim let ParserMatchClass = MipsJumpTargetAsmOperand; 474234353Sdim} 475234353Sdimdef brtarget : Operand<OtherVT> { 476234353Sdim let EncoderMethod = "getBranchTargetOpValue"; 477234353Sdim let OperandType = "OPERAND_PCREL"; 478234982Sdim let DecoderMethod = "DecodeBranchTarget"; 479276479Sdim let ParserMatchClass = MipsJumpTargetAsmOperand; 480234353Sdim} 481234353Sdimdef calltarget : Operand<iPTR> { 482234353Sdim let EncoderMethod = "getJumpTargetOpValue"; 483276479Sdim let ParserMatchClass = MipsJumpTargetAsmOperand; 484234353Sdim} 485261991Sdim 486288943Sdimdef imm64: Operand<i64>; 487288943Sdim 488296417Sdimdef simm6 : Operand<i32> { 489296417Sdim let ParserMatchClass = ConstantSImm6AsmOperandClass; 490296417Sdim let OperandType = "OPERAND_IMMEDIATE"; 491296417Sdim} 492276479Sdimdef simm9 : Operand<i32>; 493276479Sdimdef simm10 : Operand<i32>; 494276479Sdimdef simm11 : Operand<i32>; 495276479Sdim 496234982Sdimdef simm16 : Operand<i32> { 497234982Sdim let DecoderMethod= "DecodeSimm16"; 498234982Sdim} 499249423Sdim 500276479Sdimdef simm19_lsl2 : Operand<i32> { 501276479Sdim let EncoderMethod = "getSimm19Lsl2Encoding"; 502276479Sdim let DecoderMethod = "DecodeSimm19Lsl2"; 503276479Sdim let ParserMatchClass = MipsJumpTargetAsmOperand; 504276479Sdim} 505276479Sdim 506276479Sdimdef simm18_lsl3 : Operand<i32> { 507276479Sdim let EncoderMethod = "getSimm18Lsl3Encoding"; 508276479Sdim let DecoderMethod = "DecodeSimm18Lsl3"; 509276479Sdim let ParserMatchClass = MipsJumpTargetAsmOperand; 510276479Sdim} 511276479Sdim 512296417Sdimdef simm20 : Operand<i32>; 513296417Sdimdef simm32 : Operand<i32>; 514249423Sdim 515261991Sdimdef uimm20 : Operand<i32> { 516261991Sdim} 517193323Sed 518261991Sdimdef simm16_64 : Operand<i64> { 519261991Sdim let DecoderMethod = "DecodeSimm16"; 520261991Sdim} 521261991Sdim 522276479Sdim// Zero 523276479Sdimdef uimmz : Operand<i32> { 524276479Sdim let PrintMethod = "printUnsignedImm"; 525296417Sdim let ParserMatchClass = ConstantImmzAsmOperandClass; 526276479Sdim} 527276479Sdim 528296417Sdim// Unsigned Operands 529296417Sdimforeach I = {1, 2, 3, 4, 5, 6, 7, 8, 10} in 530296417Sdim def uimm # I : Operand<i32> { 531296417Sdim let PrintMethod = "printUnsignedImm"; 532296417Sdim let ParserMatchClass = 533296417Sdim !cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass"); 534296417Sdim } 535296417Sdim 536296417Sdimdef uimm2_plus1 : Operand<i32> { 537276479Sdim let PrintMethod = "printUnsignedImm"; 538296417Sdim let EncoderMethod = "getUImmWithOffsetEncoding<2, 1>"; 539296417Sdim let DecoderMethod = "DecodeUImmWithOffset<2, 1>"; 540296417Sdim let ParserMatchClass = ConstantUImm2Plus1AsmOperandClass; 541276479Sdim} 542276479Sdim 543296417Sdimdef uimm5_plus1 : Operand<i32> { 544276479Sdim let PrintMethod = "printUnsignedImm"; 545296417Sdim let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>"; 546296417Sdim let DecoderMethod = "DecodeUImmWithOffset<5, 1>"; 547296417Sdim let ParserMatchClass = ConstantUImm5Plus1AsmOperandClass; 548276479Sdim} 549276479Sdim 550296417Sdimdef uimm5_plus32 : Operand<i32> { 551261991Sdim let PrintMethod = "printUnsignedImm"; 552296417Sdim let ParserMatchClass = ConstantUImm5Plus32AsmOperandClass; 553261991Sdim} 554261991Sdim 555296417Sdimdef uimm5_plus33 : Operand<i32> { 556261991Sdim let PrintMethod = "printUnsignedImm"; 557296417Sdim let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>"; 558296417Sdim let DecoderMethod = "DecodeUImmWithOffset<5, 1>"; 559296417Sdim let ParserMatchClass = ConstantUImm5Plus33AsmOperandClass; 560261991Sdim} 561261991Sdim 562296417Sdimdef uimm5_plus32_normalize : Operand<i32> { 563296417Sdim let PrintMethod = "printUnsignedImm"; 564296417Sdim let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass; 565296417Sdim} 566296417Sdim 567296417Sdimdef uimm5_lsl2 : Operand<OtherVT> { 568296417Sdim let EncoderMethod = "getUImm5Lsl2Encoding"; 569296417Sdim let DecoderMethod = "DecodeUImm5lsl2"; 570296417Sdim let ParserMatchClass = ConstantUImm5Lsl2AsmOperandClass; 571296417Sdim} 572296417Sdim 573296417Sdimdef uimm5_plus32_normalize_64 : Operand<i64> { 574296417Sdim let PrintMethod = "printUnsignedImm"; 575296417Sdim let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass; 576296417Sdim} 577296417Sdim 578296417Sdimforeach I = {5} in 579296417Sdim def uimm # I # _64 : Operand<i64> { 580296417Sdim let PrintMethod = "printUnsignedImm"; 581296417Sdim let ParserMatchClass = 582296417Sdim !cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass"); 583296417Sdim } 584296417Sdim 585296417Sdim// Like uimm5_64 but reports a less confusing error for 32-63 when 586296417Sdim// an instruction alias permits that. 587296417Sdimdef uimm5_64_report_uimm6 : Operand<i64> { 588296417Sdim let PrintMethod = "printUnsignedImm"; 589296417Sdim let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass; 590296417Sdim} 591296417Sdim 592193323Seddef uimm16 : Operand<i32> { 593193323Sed let PrintMethod = "printUnsignedImm"; 594193323Sed} 595193323Sed 596261991Sdimdef pcrel16 : Operand<i32> { 597261991Sdim} 598261991Sdim 599243830Sdimdef MipsMemAsmOperand : AsmOperandClass { 600243830Sdim let Name = "Mem"; 601243830Sdim let ParserMethod = "parseMemOperand"; 602243830Sdim} 603243830Sdim 604296417Sdimdef MipsMemSimm9AsmOperand : AsmOperandClass { 605296417Sdim let Name = "MemOffsetSimm9"; 606296417Sdim let SuperClasses = [MipsMemAsmOperand]; 607296417Sdim let RenderMethod = "addMemOperands"; 608296417Sdim let ParserMethod = "parseMemOperand"; 609296417Sdim let PredicateMethod = "isMemWithSimmOffset<9>"; 610296417Sdim} 611296417Sdim 612296417Sdimdef MipsMemSimm9GPRAsmOperand : AsmOperandClass { 613296417Sdim let Name = "MemOffsetSimm9GPR"; 614296417Sdim let SuperClasses = [MipsMemAsmOperand]; 615296417Sdim let RenderMethod = "addMemOperands"; 616296417Sdim let ParserMethod = "parseMemOperand"; 617296417Sdim let PredicateMethod = "isMemWithSimmOffsetGPR<9>"; 618296417Sdim} 619296417Sdim 620276479Sdimdef MipsMemSimm11AsmOperand : AsmOperandClass { 621276479Sdim let Name = "MemOffsetSimm11"; 622276479Sdim let SuperClasses = [MipsMemAsmOperand]; 623276479Sdim let RenderMethod = "addMemOperands"; 624276479Sdim let ParserMethod = "parseMemOperand"; 625276479Sdim let PredicateMethod = "isMemWithSimmOffset<11>"; 626276479Sdim} 627276479Sdim 628280031Sdimdef MipsMemSimm16AsmOperand : AsmOperandClass { 629280031Sdim let Name = "MemOffsetSimm16"; 630280031Sdim let SuperClasses = [MipsMemAsmOperand]; 631280031Sdim let RenderMethod = "addMemOperands"; 632280031Sdim let ParserMethod = "parseMemOperand"; 633280031Sdim let PredicateMethod = "isMemWithSimmOffset<16>"; 634280031Sdim} 635280031Sdim 636261991Sdimdef MipsInvertedImmoperand : AsmOperandClass { 637261991Sdim let Name = "InvNum"; 638261991Sdim let RenderMethod = "addImmOperands"; 639261991Sdim let ParserMethod = "parseInvNum"; 640193323Sed} 641193323Sed 642276479Sdimdef InvertedImOperand : Operand<i32> { 643276479Sdim let ParserMatchClass = MipsInvertedImmoperand; 644261991Sdim} 645261991Sdim 646276479Sdimdef InvertedImOperand64 : Operand<i64> { 647261991Sdim let ParserMatchClass = MipsInvertedImmoperand; 648261991Sdim} 649261991Sdim 650276479Sdimclass mem_generic : Operand<iPTR> { 651226633Sdim let PrintMethod = "printMemOperand"; 652261991Sdim let MIOperandInfo = (ops ptr_rc, simm16); 653239462Sdim let EncoderMethod = "getMemEncoding"; 654243830Sdim let ParserMatchClass = MipsMemAsmOperand; 655249423Sdim let OperandType = "OPERAND_MEMORY"; 656226633Sdim} 657226633Sdim 658276479Sdim// Address operand 659276479Sdimdef mem : mem_generic; 660276479Sdim 661276479Sdim// MSA specific address operand 662276479Sdimdef mem_msa : mem_generic { 663276479Sdim let MIOperandInfo = (ops ptr_rc, simm10); 664276479Sdim let EncoderMethod = "getMSAMemEncoding"; 665276479Sdim} 666276479Sdim 667276479Sdimdef mem_simm9 : mem_generic { 668276479Sdim let MIOperandInfo = (ops ptr_rc, simm9); 669276479Sdim let EncoderMethod = "getMemEncoding"; 670296417Sdim let ParserMatchClass = MipsMemSimm9AsmOperand; 671276479Sdim} 672276479Sdim 673296417Sdimdef mem_simm9gpr : mem_generic { 674296417Sdim let MIOperandInfo = (ops ptr_rc, simm9); 675296417Sdim let EncoderMethod = "getMemEncoding"; 676296417Sdim let ParserMatchClass = MipsMemSimm9GPRAsmOperand; 677296417Sdim} 678296417Sdim 679276479Sdimdef mem_simm11 : mem_generic { 680276479Sdim let MIOperandInfo = (ops ptr_rc, simm11); 681276479Sdim let EncoderMethod = "getMemEncoding"; 682276479Sdim let ParserMatchClass = MipsMemSimm11AsmOperand; 683276479Sdim} 684276479Sdim 685280031Sdimdef mem_simm16 : mem_generic { 686280031Sdim let MIOperandInfo = (ops ptr_rc, simm16); 687280031Sdim let EncoderMethod = "getMemEncoding"; 688280031Sdim let ParserMatchClass = MipsMemSimm16AsmOperand; 689280031Sdim} 690280031Sdim 691261991Sdimdef mem_ea : Operand<iPTR> { 692224145Sdim let PrintMethod = "printMemOperandEA"; 693261991Sdim let MIOperandInfo = (ops ptr_rc, simm16); 694228379Sdim let EncoderMethod = "getMemEncoding"; 695249423Sdim let OperandType = "OPERAND_MEMORY"; 696224145Sdim} 697224145Sdim 698261991Sdimdef PtrRC : Operand<iPTR> { 699261991Sdim let MIOperandInfo = (ops ptr_rc); 700261991Sdim let DecoderMethod = "DecodePtrRegisterClass"; 701276479Sdim let ParserMatchClass = GPR32AsmOperand; 702234353Sdim} 703234353Sdim 704228379Sdim// size operand of ins instruction 705228379Sdimdef size_ins : Operand<i32> { 706228379Sdim let EncoderMethod = "getSizeInsEncoding"; 707234982Sdim let DecoderMethod = "DecodeInsSize"; 708228379Sdim} 709228379Sdim 710193323Sed// Transformation Function - get the lower 16 bits. 711193323Seddef LO16 : SDNodeXForm<imm, [{ 712234353Sdim return getImm(N, N->getZExtValue() & 0xFFFF); 713193323Sed}]>; 714193323Sed 715193323Sed// Transformation Function - get the higher 16 bits. 716193323Seddef HI16 : SDNodeXForm<imm, [{ 717234353Sdim return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 718193323Sed}]>; 719193323Sed 720249423Sdim// Plus 1. 721249423Sdimdef Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 722249423Sdim 723276479Sdim// Node immediate is zero (e.g. insve.d) 724276479Sdimdef immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>; 725276479Sdim 726193323Sed// Node immediate fits as 16-bit sign extended on target immediate. 727193323Sed// e.g. addi, andi 728249423Sdimdef immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 729249423Sdim 730249423Sdim// Node immediate fits as 16-bit sign extended on target immediate. 731249423Sdim// e.g. addi, andi 732212904Sdimdef immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 733193323Sed 734249423Sdim// Node immediate fits as 15-bit sign extended on target immediate. 735249423Sdim// e.g. addi, andi 736249423Sdimdef immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 737249423Sdim 738193323Sed// Node immediate fits as 16-bit zero extended on target immediate. 739193323Sed// The LO16 param means that only the lower 16 bits of the node 740193323Sed// immediate are caught. 741193323Sed// e.g. addiu, sltiu 742193323Seddef immZExt16 : PatLeaf<(imm), [{ 743193323Sed if (N->getValueType(0) == MVT::i32) 744193323Sed return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 745193323Sed else 746193323Sed return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 747193323Sed}], LO16>; 748193323Sed 749234353Sdim// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 750234353Sdimdef immLow16Zero : PatLeaf<(imm), [{ 751234353Sdim int64_t Val = N->getSExtValue(); 752234353Sdim return isInt<32>(Val) && !(Val & 0xffff); 753193323Sed}]>; 754193323Sed 755234353Sdim// shamt field must fit in 5 bits. 756234353Sdimdef immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 757234353Sdim 758249423Sdim// True if (N + 1) fits in 16-bit field. 759249423Sdimdef immSExt16Plus1 : PatLeaf<(imm), [{ 760249423Sdim return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 761249423Sdim}]>; 762249423Sdim 763193323Sed// Mips Address Mode! SDNode frameindex could possibily be a match 764193323Sed// since load and store instructions from stack used it. 765239462Sdimdef addr : 766249423Sdim ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 767193323Sed 768249423Sdimdef addrRegImm : 769249423Sdim ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 770249423Sdim 771261991Sdimdef addrRegReg : 772261991Sdim ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>; 773261991Sdim 774249423Sdimdef addrDefault : 775249423Sdim ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 776249423Sdim 777276479Sdimdef addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>; 778276479Sdim 779193323Sed//===----------------------------------------------------------------------===// 780243830Sdim// Instructions specific format 781226633Sdim//===----------------------------------------------------------------------===// 782226633Sdim 783226633Sdim// Arithmetic and logical instructions with 3 register operands. 784249423Sdimclass ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 785249423Sdim InstrItinClass Itin = NoItinerary, 786249423Sdim SDPatternOperator OpNode = null_frag>: 787249423Sdim InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 788249423Sdim !strconcat(opstr, "\t$rd, $rs, $rt"), 789251662Sdim [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> { 790223017Sdim let isCommutable = isComm; 791234982Sdim let isReMaterializable = 1; 792276479Sdim let TwoOperandAliasConstraint = "$rd = $rs"; 793223017Sdim} 794193323Sed 795226633Sdim// Arithmetic and logical instructions with 2 register operands. 796249423Sdimclass ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 797261991Sdim InstrItinClass Itin = NoItinerary, 798249423Sdim SDPatternOperator imm_type = null_frag, 799249423Sdim SDPatternOperator OpNode = null_frag> : 800249423Sdim InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 801249423Sdim !strconcat(opstr, "\t$rt, $rs, $imm16"), 802251662Sdim [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], 803261991Sdim Itin, FrmI, opstr> { 804234982Sdim let isReMaterializable = 1; 805261991Sdim let TwoOperandAliasConstraint = "$rs = $rt"; 806234982Sdim} 807193323Sed 808193323Sed// Arithmetic Multiply ADD/SUB 809276479Sdimclass MArithR<string opstr, InstrItinClass itin, bit isComm = 0> : 810261991Sdim InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 811276479Sdim !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> { 812261991Sdim let Defs = [HI0, LO0]; 813261991Sdim let Uses = [HI0, LO0]; 814223017Sdim let isCommutable = isComm; 815223017Sdim} 816193323Sed 817193323Sed// Logical 818261991Sdimclass LogicNOR<string opstr, RegisterOperand RO>: 819261991Sdim InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 820249423Sdim !strconcat(opstr, "\t$rd, $rs, $rt"), 821276479Sdim [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> { 822226633Sdim let isCommutable = 1; 823226633Sdim} 824193323Sed 825193323Sed// Shifts 826249423Sdimclass shift_rotate_imm<string opstr, Operand ImmOpnd, 827276479Sdim RegisterOperand RO, InstrItinClass itin, 828276479Sdim SDPatternOperator OpNode = null_frag, 829249423Sdim SDPatternOperator PF = null_frag> : 830261991Sdim InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt), 831249423Sdim !strconcat(opstr, "\t$rd, $rt, $shamt"), 832276479Sdim [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> { 833276479Sdim let TwoOperandAliasConstraint = "$rt = $rd"; 834276479Sdim} 835193323Sed 836276479Sdimclass shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin, 837249423Sdim SDPatternOperator OpNode = null_frag>: 838261991Sdim InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs), 839249423Sdim !strconcat(opstr, "\t$rd, $rt, $rs"), 840276479Sdim [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR, 841276479Sdim opstr>; 842234353Sdim 843296417Sdim// Load Upper Immediate 844261991Sdimclass LoadUpper<string opstr, RegisterOperand RO, Operand Imm>: 845261991Sdim InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 846276479Sdim [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove { 847280031Sdim let hasSideEffects = 0; 848234982Sdim let isReMaterializable = 1; 849226633Sdim} 850193323Sed 851193323Sed// Memory Load/Store 852261991Sdimclass Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 853261991Sdim InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 854261991Sdim InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 855261991Sdim [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> { 856249423Sdim let DecoderMethod = "DecodeMem"; 857249423Sdim let canFoldAsLoad = 1; 858249423Sdim let mayLoad = 1; 859226633Sdim} 860193323Sed 861296417Sdimclass StoreMemory<string opstr, DAGOperand RO, DAGOperand MO, 862296417Sdim SDPatternOperator OpNode = null_frag, 863261991Sdim InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 864296417Sdim InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"), 865261991Sdim [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> { 866249423Sdim let DecoderMethod = "DecodeMem"; 867249423Sdim let mayStore = 1; 868226633Sdim} 869193323Sed 870296417Sdimclass Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 871296417Sdim InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 872296417Sdim StoreMemory<opstr, RO, mem, OpNode, Itin, Addr>; 873296417Sdim 874239462Sdim// Load/Store Left/Right 875239462Sdimlet canFoldAsLoad = 1 in 876261991Sdimclass LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 877261991Sdim InstrItinClass Itin> : 878261991Sdim InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src), 879249423Sdim !strconcat(opstr, "\t$rt, $addr"), 880261991Sdim [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> { 881249423Sdim let DecoderMethod = "DecodeMem"; 882239462Sdim string Constraints = "$src = $rt"; 883239462Sdim} 884239462Sdim 885261991Sdimclass StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 886261991Sdim InstrItinClass Itin> : 887261991Sdim InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 888261991Sdim [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> { 889249423Sdim let DecoderMethod = "DecodeMem"; 890234353Sdim} 891234353Sdim 892280031Sdim// COP2 Load/Store 893280031Sdimclass LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin, 894280031Sdim SDPatternOperator OpNode= null_frag> : 895280031Sdim InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 896280031Sdim [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> { 897280031Sdim let DecoderMethod = "DecodeFMem2"; 898280031Sdim let mayLoad = 1; 899280031Sdim} 900280031Sdim 901280031Sdimclass SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin, 902280031Sdim SDPatternOperator OpNode= null_frag> : 903280031Sdim InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 904280031Sdim [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> { 905280031Sdim let DecoderMethod = "DecodeFMem2"; 906280031Sdim let mayStore = 1; 907280031Sdim} 908280031Sdim 909280031Sdim// COP3 Load/Store 910280031Sdimclass LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin, 911280031Sdim SDPatternOperator OpNode= null_frag> : 912280031Sdim InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 913280031Sdim [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> { 914280031Sdim let DecoderMethod = "DecodeFMem3"; 915280031Sdim let mayLoad = 1; 916280031Sdim} 917280031Sdim 918280031Sdimclass SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin, 919280031Sdim SDPatternOperator OpNode= null_frag> : 920280031Sdim InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 921280031Sdim [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> { 922280031Sdim let DecoderMethod = "DecodeFMem3"; 923280031Sdim let mayStore = 1; 924280031Sdim} 925280031Sdim 926193323Sed// Conditional Branch 927261991Sdimclass CBranch<string opstr, DAGOperand opnd, PatFrag cond_op, 928280031Sdim RegisterOperand RO, bit DelaySlot = 1> : 929261991Sdim InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset), 930249423Sdim !strconcat(opstr, "\t$rs, $rt, $offset"), 931296417Sdim [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], II_BCC, 932261991Sdim FrmI, opstr> { 933226633Sdim let isBranch = 1; 934226633Sdim let isTerminator = 1; 935280031Sdim let hasDelaySlot = DelaySlot; 936239462Sdim let Defs = [AT]; 937226633Sdim} 938193323Sed 939261991Sdimclass CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op, 940280031Sdim RegisterOperand RO, bit DelaySlot = 1> : 941261991Sdim InstSE<(outs), (ins RO:$rs, opnd:$offset), 942249423Sdim !strconcat(opstr, "\t$rs, $offset"), 943296417Sdim [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], II_BCCZ, 944261991Sdim FrmI, opstr> { 945226633Sdim let isBranch = 1; 946226633Sdim let isTerminator = 1; 947280031Sdim let hasDelaySlot = DelaySlot; 948239462Sdim let Defs = [AT]; 949193323Sed} 950193323Sed 951193323Sed// SetCC 952261991Sdimclass SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> : 953261991Sdim InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt), 954249423Sdim !strconcat(opstr, "\t$rd, $rs, $rt"), 955261991Sdim [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))], 956276479Sdim II_SLT_SLTU, FrmR, opstr>; 957249423Sdim 958249423Sdimclass SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 959261991Sdim RegisterOperand RO>: 960261991Sdim InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16), 961249423Sdim !strconcat(opstr, "\t$rt, $rs, $imm16"), 962261991Sdim [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))], 963276479Sdim II_SLTI_SLTIU, FrmI, opstr>; 964193323Sed 965234353Sdim// Jump 966249423Sdimclass JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 967261991Sdim SDPatternOperator targetoperator, string bopstr> : 968249423Sdim InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 969296417Sdim [(operator targetoperator:$target)], II_J, FrmJ, bopstr> { 970234353Sdim let isTerminator=1; 971234353Sdim let isBarrier=1; 972234353Sdim let hasDelaySlot = 1; 973234982Sdim let DecoderMethod = "DecodeJumpTarget"; 974239462Sdim let Defs = [AT]; 975234353Sdim} 976193323Sed 977234353Sdim// Unconditional branch 978261991Sdimclass UncondBranch<Instruction BEQInst> : 979296417Sdim PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], II_B>, 980261991Sdim PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> { 981234353Sdim let isBranch = 1; 982234353Sdim let isTerminator = 1; 983234353Sdim let isBarrier = 1; 984234353Sdim let hasDelaySlot = 1; 985276479Sdim let AdditionalPredicates = [RelocPIC]; 986239462Sdim let Defs = [AT]; 987234353Sdim} 988234353Sdim 989239462Sdim// Base class for indirect branch and return instruction classes. 990239462Sdimlet isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 991261991Sdimclass JumpFR<string opstr, RegisterOperand RO, 992261991Sdim SDPatternOperator operator = null_frag>: 993296417Sdim InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], II_JR, 994261991Sdim FrmR, opstr>; 995193323Sed 996239462Sdim// Indirect branch 997276479Sdimclass IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> { 998239462Sdim let isBranch = 1; 999239462Sdim let isIndirectBranch = 1; 1000239462Sdim} 1001239462Sdim 1002193323Sed// Jump and Link (Call) 1003239462Sdimlet isCall=1, hasDelaySlot=1, Defs = [RA] in { 1004261991Sdim class JumpLink<string opstr, DAGOperand opnd> : 1005261991Sdim InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 1006296417Sdim [(MipsJmpLink tglobaladdr:$target)], II_JAL, FrmJ, opstr> { 1007249423Sdim let DecoderMethod = "DecodeJumpTarget"; 1008226633Sdim } 1009193323Sed 1010261991Sdim class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst, 1011261991Sdim Register RetReg, RegisterOperand ResRO = RO>: 1012296417Sdim PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], II_JALR>, 1013261991Sdim PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>; 1014249423Sdim 1015261991Sdim class JumpLinkReg<string opstr, RegisterOperand RO>: 1016261991Sdim InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 1017296417Sdim [], II_JALR, FrmR, opstr>; 1018249423Sdim 1019280031Sdim class BGEZAL_FT<string opstr, DAGOperand opnd, 1020280031Sdim RegisterOperand RO, bit DelaySlot = 1> : 1021261991Sdim InstSE<(outs), (ins RO:$rs, opnd:$offset), 1022296417Sdim !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZAL, FrmI, opstr> { 1023280031Sdim let hasDelaySlot = DelaySlot; 1024280031Sdim } 1025249423Sdim 1026193323Sed} 1027193323Sed 1028276479Sdimlet isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1, 1029276479Sdim hasExtraSrcRegAllocReq = 1, Defs = [AT] in { 1030276479Sdim class TailCall<Instruction JumpInst> : 1031296417Sdim PseudoSE<(outs), (ins calltarget:$target), [], II_J>, 1032276479Sdim PseudoInstExpansion<(JumpInst jmptarget:$target)>; 1033276479Sdim 1034276479Sdim class TailCallReg<RegisterOperand RO, Instruction JRInst, 1035276479Sdim RegisterOperand ResRO = RO> : 1036296417Sdim PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>, 1037276479Sdim PseudoInstExpansion<(JRInst ResRO:$rs)>; 1038276479Sdim} 1039276479Sdim 1040261991Sdimclass BAL_BR_Pseudo<Instruction RealInst> : 1041296417Sdim PseudoSE<(outs), (ins brtarget:$offset), [], II_BCCZAL>, 1042261991Sdim PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> { 1043249423Sdim let isBranch = 1; 1044249423Sdim let isTerminator = 1; 1045249423Sdim let isBarrier = 1; 1046249423Sdim let hasDelaySlot = 1; 1047249423Sdim let Defs = [RA]; 1048249423Sdim} 1049249423Sdim 1050261991Sdim// Syscall 1051261991Sdimclass SYS_FT<string opstr> : 1052261991Sdim InstSE<(outs), (ins uimm20:$code_), 1053276479Sdim !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>; 1054261991Sdim// Break 1055261991Sdimclass BRK_FT<string opstr> : 1056261991Sdim InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2), 1057276479Sdim !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, 1058276479Sdim FrmOther, opstr>; 1059261991Sdim 1060261991Sdim// (D)Eret 1061261991Sdimclass ER_FT<string opstr> : 1062261991Sdim InstSE<(outs), (ins), 1063276479Sdim opstr, [], NoItinerary, FrmOther, opstr>; 1064261991Sdim 1065261991Sdim// Interrupts 1066261991Sdimclass DEI_FT<string opstr, RegisterOperand RO> : 1067261991Sdim InstSE<(outs RO:$rt), (ins), 1068276479Sdim !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>; 1069261991Sdim 1070261991Sdim// Wait 1071261991Sdimclass WAIT_FT<string opstr> : 1072276479Sdim InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>; 1073261991Sdim 1074249423Sdim// Sync 1075249423Sdimlet hasSideEffects = 1 in 1076276479Sdimclass SYNC_FT<string opstr> : 1077249423Sdim InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 1078276479Sdim NoItinerary, FrmOther, opstr>; 1079249423Sdim 1080280031Sdimclass SYNCI_FT<string opstr> : 1081280031Sdim InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [], 1082280031Sdim NoItinerary, FrmOther, opstr> { 1083280031Sdim let hasSideEffects = 1; 1084280031Sdim let DecoderMethod = "DecodeSyncI"; 1085280031Sdim} 1086280031Sdim 1087261991Sdimlet hasSideEffects = 1 in 1088261991Sdimclass TEQ_FT<string opstr, RegisterOperand RO> : 1089261991Sdim InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_), 1090261991Sdim !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, 1091261991Sdim FrmI, opstr>; 1092261991Sdim 1093261991Sdimclass TEQI_FT<string opstr, RegisterOperand RO> : 1094261991Sdim InstSE<(outs), (ins RO:$rs, uimm16:$imm16), 1095261991Sdim !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>; 1096193323Sed// Mul, Div 1097249423Sdimclass Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 1098249423Sdim list<Register> DefRegs> : 1099249423Sdim InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 1100251662Sdim itin, FrmR, opstr> { 1101226633Sdim let isCommutable = 1; 1102234353Sdim let Defs = DefRegs; 1103280031Sdim let hasSideEffects = 0; 1104226633Sdim} 1105193323Sed 1106249423Sdim// Pseudo multiply/divide instruction with explicit accumulator register 1107249423Sdim// operands. 1108249423Sdimclass MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1, 1109249423Sdim SDPatternOperator OpNode, InstrItinClass Itin, 1110261991Sdim bit IsComm = 1, bit HasSideEffects = 0, 1111261991Sdim bit UsesCustomInserter = 0> : 1112249423Sdim PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt), 1113249423Sdim [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>, 1114249423Sdim PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> { 1115249423Sdim let isCommutable = IsComm; 1116249423Sdim let hasSideEffects = HasSideEffects; 1117261991Sdim let usesCustomInserter = UsesCustomInserter; 1118249423Sdim} 1119234353Sdim 1120249423Sdim// Pseudo multiply add/sub instruction with explicit accumulator register 1121249423Sdim// operands. 1122276479Sdimclass MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode, 1123276479Sdim InstrItinClass itin> 1124261991Sdim : PseudoSE<(outs ACC64:$ac), 1125261991Sdim (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin), 1126261991Sdim [(set ACC64:$ac, 1127261991Sdim (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))], 1128276479Sdim itin>, 1129261991Sdim PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> { 1130249423Sdim string Constraints = "$acin = $ac"; 1131249423Sdim} 1132249423Sdim 1133249423Sdimclass Div<string opstr, InstrItinClass itin, RegisterOperand RO, 1134249423Sdim list<Register> DefRegs> : 1135249423Sdim InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), 1136261991Sdim [], itin, FrmR, opstr> { 1137234353Sdim let Defs = DefRegs; 1138221345Sdim} 1139221345Sdim 1140193323Sed// Move from Hi/Lo 1141261991Sdimclass PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> 1142261991Sdim : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo), 1143276479Sdim [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>; 1144261991Sdim 1145261991Sdimclass MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>: 1146276479Sdim InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO, 1147276479Sdim FrmR, opstr> { 1148261991Sdim let Uses = [UseReg]; 1149280031Sdim let hasSideEffects = 0; 1150226633Sdim} 1151193323Sed 1152261991Sdimclass PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC> 1153261991Sdim : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi), 1154276479Sdim [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))], 1155276479Sdim II_MTHI_MTLO>; 1156261991Sdim 1157261991Sdimclass MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>: 1158276479Sdim InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO, 1159261991Sdim FrmR, opstr> { 1160234353Sdim let Defs = DefRegs; 1161280031Sdim let hasSideEffects = 0; 1162226633Sdim} 1163193323Sed 1164261991Sdimclass EffectiveAddress<string opstr, RegisterOperand RO> : 1165261991Sdim InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"), 1166276479Sdim [(set RO:$rt, addr:$addr)], NoItinerary, FrmI, 1167276479Sdim !strconcat(opstr, "_lea")> { 1168249423Sdim let isCodeGenOnly = 1; 1169249423Sdim let DecoderMethod = "DecodeMem"; 1170239462Sdim} 1171193323Sed 1172193323Sed// Count Leading Ones/Zeros in Word 1173249423Sdimclass CountLeading0<string opstr, RegisterOperand RO>: 1174249423Sdim InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 1175276479Sdim [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>; 1176193323Sed 1177249423Sdimclass CountLeading1<string opstr, RegisterOperand RO>: 1178249423Sdim InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 1179276479Sdim [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>; 1180234353Sdim 1181193323Sed// Sign Extend in Register. 1182276479Sdimclass SignExtInReg<string opstr, ValueType vt, RegisterOperand RO, 1183276479Sdim InstrItinClass itin> : 1184261991Sdim InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), 1185276479Sdim [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>; 1186193323Sed 1187234353Sdim// Subword Swap 1188296417Sdimclass SubwordSwap<string opstr, RegisterOperand RO, 1189296417Sdim InstrItinClass itin = NoItinerary>: 1190296417Sdim InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], itin, 1191296417Sdim FrmR, opstr> { 1192280031Sdim let hasSideEffects = 0; 1193226633Sdim} 1194193323Sed 1195223017Sdim// Read Hardware 1196261991Sdimclass ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> : 1197261991Sdim InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 1198280031Sdim II_RDHWR, FrmR, "rdhwr">; 1199223017Sdim 1200226633Sdim// Ext and Ins 1201261991Sdimclass ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd, 1202296417Sdim Operand SizeOpnd, SDPatternOperator Op = null_frag> : 1203296417Sdim InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size), 1204249423Sdim !strconcat(opstr, " $rt, $rs, $pos, $size"), 1205288943Sdim [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], II_EXT, 1206276479Sdim FrmR, opstr>, ISA_MIPS32R2; 1207226633Sdim 1208261991Sdimclass InsBase<string opstr, RegisterOperand RO, Operand PosOpnd, 1209261991Sdim SDPatternOperator Op = null_frag>: 1210261991Sdim InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src), 1211249423Sdim !strconcat(opstr, " $rt, $rs, $pos, $size"), 1212261991Sdim [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))], 1213288943Sdim II_INS, FrmR, opstr>, ISA_MIPS32R2 { 1214234353Sdim let Constraints = "$src = $rt"; 1215234353Sdim} 1216234353Sdim 1217226633Sdim// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 1218261991Sdimclass Atomic2Ops<PatFrag Op, RegisterClass DRC> : 1219261991Sdim PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr), 1220261991Sdim [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>; 1221226633Sdim 1222226633Sdim// Atomic Compare & Swap. 1223261991Sdimclass AtomicCmpSwap<PatFrag Op, RegisterClass DRC> : 1224261991Sdim PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap), 1225261991Sdim [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>; 1226226633Sdim 1227261991Sdimclass LLBase<string opstr, RegisterOperand RO> : 1228261991Sdim InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 1229249423Sdim [], NoItinerary, FrmI> { 1230249423Sdim let DecoderMethod = "DecodeMem"; 1231234353Sdim let mayLoad = 1; 1232234353Sdim} 1233234353Sdim 1234261991Sdimclass SCBase<string opstr, RegisterOperand RO> : 1235261991Sdim InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr), 1236249423Sdim !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 1237249423Sdim let DecoderMethod = "DecodeMem"; 1238234353Sdim let mayStore = 1; 1239234353Sdim let Constraints = "$rt = $dst"; 1240234353Sdim} 1241234353Sdim 1242288943Sdimclass MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> : 1243288943Sdim InstSE<(outs RO:$rt), (ins RD:$rd, uimm16:$sel), 1244261991Sdim !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>; 1245249423Sdim 1246288943Sdimclass MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> : 1247288943Sdim InstSE<(outs RO:$rd), (ins RD:$rt, uimm16:$sel), 1248288943Sdim !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>; 1249288943Sdim 1250261991Sdimclass TrapBase<Instruction RealInst> 1251261991Sdim : PseudoSE<(outs), (ins), [(trap)], NoItinerary>, 1252261991Sdim PseudoInstExpansion<(RealInst 0, 0)> { 1253261991Sdim let isBarrier = 1; 1254261991Sdim let isTerminator = 1; 1255261991Sdim let isCodeGenOnly = 1; 1256261991Sdim} 1257261991Sdim 1258193323Sed//===----------------------------------------------------------------------===// 1259193323Sed// Pseudo instructions 1260193323Sed//===----------------------------------------------------------------------===// 1261193323Sed 1262239462Sdim// Return RA. 1263239462Sdimlet isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 1264249423Sdimdef RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 1265239462Sdim 1266296417Sdimlet isReturn=1, isTerminator=1, isBarrier=1, hasCtrlDep=1, hasSideEffects=1 in 1267296417Sdimdef ERet : PseudoSE<(outs), (ins), [(MipsERet)]>; 1268296417Sdim 1269239462Sdimlet Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 1270239462Sdimdef ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 1271193323Sed [(callseq_start timm:$amt)]>; 1272239462Sdimdef ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 1273193323Sed [(callseq_end timm:$amt1, timm:$amt2)]>; 1274193323Sed} 1275193323Sed 1276223017Sdimlet usesCustomInserter = 1 in { 1277261991Sdim def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>; 1278261991Sdim def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>; 1279261991Sdim def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>; 1280261991Sdim def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>; 1281261991Sdim def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>; 1282261991Sdim def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>; 1283261991Sdim def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>; 1284261991Sdim def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>; 1285261991Sdim def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>; 1286261991Sdim def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>; 1287261991Sdim def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>; 1288261991Sdim def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>; 1289261991Sdim def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>; 1290261991Sdim def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>; 1291261991Sdim def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>; 1292261991Sdim def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>; 1293261991Sdim def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>; 1294261991Sdim def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>; 1295223017Sdim 1296261991Sdim def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>; 1297261991Sdim def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>; 1298261991Sdim def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>; 1299223017Sdim 1300261991Sdim def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>; 1301261991Sdim def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>; 1302261991Sdim def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>; 1303223017Sdim} 1304223017Sdim 1305251662Sdim/// Pseudo instructions for loading and storing accumulator registers. 1306261991Sdimlet isPseudo = 1, isCodeGenOnly = 1 in { 1307261991Sdim def LOAD_ACC64 : Load<"", ACC64>; 1308261991Sdim def STORE_ACC64 : Store<"", ACC64>; 1309249423Sdim} 1310249423Sdim 1311276479Sdim// We need these two pseudo instructions to avoid offset calculation for long 1312276479Sdim// branches. See the comment in file MipsLongBranch.cpp for detailed 1313276479Sdim// explanation. 1314276479Sdim 1315276479Sdim// Expands to: lui $dst, %hi($tgt - $baltgt) 1316276479Sdimdef LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst), 1317276479Sdim (ins brtarget:$tgt, brtarget:$baltgt), []>; 1318276479Sdim 1319276479Sdim// Expands to: addiu $dst, $src, %lo($tgt - $baltgt) 1320276479Sdimdef LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst), 1321276479Sdim (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>; 1322276479Sdim 1323193323Sed//===----------------------------------------------------------------------===// 1324193323Sed// Instruction definition 1325193323Sed//===----------------------------------------------------------------------===// 1326193323Sed//===----------------------------------------------------------------------===// 1327193323Sed// MipsI Instructions 1328193323Sed//===----------------------------------------------------------------------===// 1329193323Sed 1330193323Sed/// Arithmetic Instructions (ALU Immediate) 1331280031Sdimlet AdditionalPredicates = [NotInMicroMips] in { 1332288943Sdimdef ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16, GPR32Opnd, 1333288943Sdim II_ADDIU, immSExt16, add>, 1334288943Sdim ADDI_FM<0x9>, IsAsCheapAsAMove; 1335280031Sdim} 1336276479Sdimdef ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>, 1337276479Sdim ISA_MIPS1_NOT_32R6_64R6; 1338261991Sdimdef SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, 1339251662Sdim SLTI_FM<0xa>; 1340261991Sdimdef SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, 1341251662Sdim SLTI_FM<0xb>; 1342280031Sdimlet AdditionalPredicates = [NotInMicroMips] in { 1343288943Sdimdef ANDi : MMRel, StdMMR6Rel, 1344288943Sdim ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>, 1345288943Sdim ADDI_FM<0xc>; 1346280031Sdim} 1347288943Sdimdef ORi : MMRel, StdMMR6Rel, 1348288943Sdim ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>, 1349249423Sdim ADDI_FM<0xd>; 1350288943Sdimdef XORi : MMRel, StdMMR6Rel, 1351288943Sdim ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>, 1352249423Sdim ADDI_FM<0xe>; 1353261991Sdimdef LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM; 1354288943Sdimlet AdditionalPredicates = [NotInMicroMips] in { 1355193323Sed/// Arithmetic Instructions (3-Operand, R-Type) 1356288943Sdimdef ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, 1357251662Sdim ADD_FM<0, 0x21>; 1358276479Sdimdef SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, 1359251662Sdim ADD_FM<0, 0x23>; 1360288943Sdim} 1361261991Sdimlet Defs = [HI0, LO0] in 1362276479Sdimdef MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>, 1363276479Sdim ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6; 1364288943Sdimdef ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>; 1365261991Sdimdef SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>; 1366261991Sdimdef SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; 1367261991Sdimdef SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; 1368288943Sdimlet AdditionalPredicates = [NotInMicroMips] in { 1369288943Sdimdef AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, 1370251662Sdim ADD_FM<0, 0x24>; 1371288943Sdimdef OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>, 1372251662Sdim ADD_FM<0, 0x25>; 1373288943Sdimdef XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, 1374251662Sdim ADD_FM<0, 0x26>; 1375288943Sdim} 1376288943Sdimdef NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; 1377193323Sed 1378193323Sed/// Shift Instructions 1379280031Sdimlet AdditionalPredicates = [NotInMicroMips] in { 1380276479Sdimdef SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl, 1381276479Sdim immZExt5>, SRA_FM<0, 0>; 1382276479Sdimdef SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl, 1383276479Sdim immZExt5>, SRA_FM<2, 0>; 1384280031Sdim} 1385276479Sdimdef SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra, 1386276479Sdim immZExt5>, SRA_FM<3, 0>; 1387276479Sdimdef SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>, 1388276479Sdim SRLV_FM<4, 0>; 1389276479Sdimdef SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>, 1390276479Sdim SRLV_FM<6, 0>; 1391276479Sdimdef SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>, 1392276479Sdim SRLV_FM<7, 0>; 1393193323Sed 1394218893Sdim// Rotate Instructions 1395276479Sdimdef ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr, 1396276479Sdim immZExt5>, 1397276479Sdim SRA_FM<2, 1>, ISA_MIPS32R2; 1398276479Sdimdef ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, 1399276479Sdim SRLV_FM<6, 1>, ISA_MIPS32R2; 1400218893Sdim 1401193323Sed/// Load and Store Instructions 1402226633Sdim/// aligned 1403276479Sdimdef LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>; 1404276479Sdimdef LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel, 1405261991Sdim LW_FM<0x24>; 1406276479Sdimdef LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel, 1407261991Sdim LW_FM<0x21>; 1408276479Sdimdef LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>; 1409288943Sdimlet AdditionalPredicates = [NotInMicroMips] in { 1410296417Sdimdef LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel, 1411261991Sdim LW_FM<0x23>; 1412288943Sdim} 1413296417Sdimdef SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, 1414296417Sdim LW_FM<0x28>; 1415276479Sdimdef SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>; 1416288943Sdimlet AdditionalPredicates = [NotInMicroMips] in { 1417276479Sdimdef SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>; 1418288943Sdim} 1419193323Sed 1420239462Sdim/// load/store left/right 1421276479Sdimlet EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug 1422276479Sdim AdditionalPredicates = [NotInMicroMips] in { 1423276479Sdimdef LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>, 1424276479Sdim ISA_MIPS1_NOT_32R6_64R6; 1425276479Sdimdef LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>, 1426276479Sdim ISA_MIPS1_NOT_32R6_64R6; 1427276479Sdimdef SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>, 1428276479Sdim ISA_MIPS1_NOT_32R6_64R6; 1429276479Sdimdef SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>, 1430276479Sdim ISA_MIPS1_NOT_32R6_64R6; 1431261991Sdim} 1432234353Sdim 1433288943Sdimlet AdditionalPredicates = [NotInMicroMips] in { 1434280031Sdim// COP2 Memory Instructions 1435280031Sdimdef LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>, 1436280031Sdim ISA_MIPS1_NOT_32R6_64R6; 1437280031Sdimdef SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>, 1438280031Sdim ISA_MIPS1_NOT_32R6_64R6; 1439280031Sdimdef LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>, 1440280031Sdim ISA_MIPS2_NOT_32R6_64R6; 1441280031Sdimdef SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>, 1442280031Sdim ISA_MIPS2_NOT_32R6_64R6; 1443280031Sdim 1444280031Sdim// COP3 Memory Instructions 1445280031Sdimlet DecoderNamespace = "COP3_" in { 1446280031Sdim def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>; 1447280031Sdim def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>; 1448280031Sdim def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>, 1449280031Sdim ISA_MIPS2; 1450280031Sdim def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>, 1451280031Sdim ISA_MIPS2; 1452280031Sdim} 1453288943Sdim} 1454280031Sdim 1455296417Sdimdef SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32; 1456296417Sdimdef SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2; 1457226633Sdim 1458296417Sdimlet AdditionalPredicates = [NotInMicroMips] in { 1459296417Sdim def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2; 1460296417Sdim def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2; 1461296417Sdim def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2; 1462296417Sdim def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2; 1463296417Sdim def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2; 1464296417Sdim def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2; 1465296417Sdim} 1466280031Sdim 1467276479Sdimdef TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>, 1468276479Sdim ISA_MIPS2_NOT_32R6_64R6; 1469276479Sdimdef TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>, 1470276479Sdim ISA_MIPS2_NOT_32R6_64R6; 1471276479Sdimdef TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>, 1472276479Sdim ISA_MIPS2_NOT_32R6_64R6; 1473276479Sdimdef TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>, 1474276479Sdim ISA_MIPS2_NOT_32R6_64R6; 1475276479Sdimdef TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>, 1476276479Sdim ISA_MIPS2_NOT_32R6_64R6; 1477276479Sdimdef TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>, 1478276479Sdim ISA_MIPS2_NOT_32R6_64R6; 1479261991Sdim 1480288943Sdimlet AdditionalPredicates = [NotInMicroMips] in { 1481288943Sdimdef BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>; 1482288943Sdim} 1483276479Sdimdef SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>; 1484261991Sdimdef TRAP : TrapBase<BREAK>; 1485280031Sdimdef SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6; 1486261991Sdim 1487288943Sdimlet AdditionalPredicates = [NotInMicroMips] in { 1488296417Sdim def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18, 0x0>, INSN_MIPS3_32; 1489296417Sdim def ERETNC : MMRel, ER_FT<"eretnc">, ER_FM<0x18, 0x1>, ISA_MIPS32R5; 1490296417Sdim def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f, 0x0>, ISA_MIPS32; 1491288943Sdim} 1492261991Sdim 1493288943Sdimlet AdditionalPredicates = [NotInMicroMips] in { 1494296417Sdim def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2; 1495296417Sdim def DI : MMRel, StdMMR6Rel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2; 1496288943Sdim} 1497261991Sdim 1498276479Sdimlet EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug 1499276479Sdim AdditionalPredicates = [NotInMicroMips] in { 1500276479Sdimdef WAIT : WAIT_FT<"wait">, WAIT_FM; 1501261991Sdim 1502223017Sdim/// Load-linked, Store-conditional 1503276479Sdimdef LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6; 1504276479Sdimdef SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6; 1505276479Sdim} 1506234982Sdim 1507193323Sed/// Jump and Branch Instructions 1508261991Sdimdef J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>, 1509276479Sdim AdditionalRequires<[RelocStatic]>, IsBranch; 1510261991Sdimdef JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>; 1511261991Sdimdef BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>; 1512280031Sdimdef BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>, 1513280031Sdim BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6; 1514261991Sdimdef BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>; 1515280031Sdimdef BNEL : MMRel, CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>, 1516280031Sdim BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6; 1517261991Sdimdef BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>, 1518261991Sdim BGEZ_FM<1, 1>; 1519280031Sdimdef BGEZL : MMRel, CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>, 1520280031Sdim BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6; 1521261991Sdimdef BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>, 1522261991Sdim BGEZ_FM<7, 0>; 1523280031Sdimdef BGTZL : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>, 1524280031Sdim BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6; 1525261991Sdimdef BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>, 1526261991Sdim BGEZ_FM<6, 0>; 1527280031Sdimdef BLEZL : MMRel, CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>, 1528280031Sdim BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6; 1529261991Sdimdef BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>, 1530261991Sdim BGEZ_FM<1, 0>; 1531280031Sdimdef BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>, 1532280031Sdim BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6; 1533261991Sdimdef B : UncondBranch<BEQ>; 1534193323Sed 1535261991Sdimdef JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>; 1536276479Sdimlet AdditionalPredicates = [NotInMicroMips] in { 1537276479Sdim def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM; 1538276479Sdim def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>; 1539276479Sdim} 1540276479Sdim 1541288943Sdimdef JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>, 1542288943Sdim ISA_MIPS32_NOT_32R6_64R6; 1543276479Sdimdef BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>, 1544276479Sdim ISA_MIPS1_NOT_32R6_64R6; 1545280031Sdimdef BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>, 1546280031Sdim BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6; 1547276479Sdimdef BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>, 1548276479Sdim ISA_MIPS1_NOT_32R6_64R6; 1549280031Sdimdef BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>, 1550280031Sdim BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6; 1551261991Sdimdef BAL_BR : BAL_BR_Pseudo<BGEZAL>; 1552276479Sdimdef TAILCALL : TailCall<J>; 1553276479Sdimdef TAILCALL_R : TailCallReg<GPR32Opnd, JR>; 1554239462Sdim 1555276479Sdim// Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64 1556276479Sdim// then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA. 1557276479Sdimclass PseudoIndirectBranchBase<RegisterOperand RO> : 1558296417Sdim MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)], 1559296417Sdim II_IndirectBranchPseudo> { 1560276479Sdim let isTerminator=1; 1561276479Sdim let isBarrier=1; 1562276479Sdim let hasDelaySlot = 1; 1563276479Sdim let isBranch = 1; 1564276479Sdim let isIndirectBranch = 1; 1565276479Sdim} 1566193323Sed 1567276479Sdimdef PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>; 1568276479Sdim 1569296417Sdim// Return instructions are matched as a RetRA instruction, then are expanded 1570276479Sdim// into PseudoReturn/PseudoReturn64 after register allocation. Finally, 1571276479Sdim// MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the 1572276479Sdim// ISA. 1573276479Sdimclass PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs), 1574296417Sdim [], II_ReturnPseudo> { 1575276479Sdim let isTerminator = 1; 1576276479Sdim let isBarrier = 1; 1577276479Sdim let hasDelaySlot = 1; 1578276479Sdim let isReturn = 1; 1579276479Sdim let isCodeGenOnly = 1; 1580276479Sdim let hasCtrlDep = 1; 1581276479Sdim let hasExtraSrcRegAllocReq = 1; 1582276479Sdim} 1583276479Sdim 1584276479Sdimdef PseudoReturn : PseudoReturnBase<GPR32Opnd>; 1585276479Sdim 1586249423Sdim// Exception handling related node and instructions. 1587249423Sdim// The conversion sequence is: 1588249423Sdim// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 1589249423Sdim// MIPSeh_return -> (stack change + indirect branch) 1590249423Sdim// 1591249423Sdim// MIPSeh_return takes the place of regular return instruction 1592249423Sdim// but takes two arguments (V1, V0) which are used for storing 1593249423Sdim// the offset and return address respectively. 1594249423Sdimdef SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 1595249423Sdim 1596249423Sdimdef MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 1597249423Sdim [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 1598249423Sdim 1599249423Sdimlet Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 1600261991Sdim def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst), 1601261991Sdim [(MIPSehret GPR32:$spoff, GPR32:$dst)]>; 1602261991Sdim def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff, 1603261991Sdim GPR64:$dst), 1604261991Sdim [(MIPSehret GPR64:$spoff, GPR64:$dst)]>; 1605249423Sdim} 1606249423Sdim 1607218893Sdim/// Multiply and Divide Instructions. 1608276479Sdimdef MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>, 1609276479Sdim MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6; 1610276479Sdimdef MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>, 1611276479Sdim MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6; 1612276479Sdimdef SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>, 1613276479Sdim MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6; 1614276479Sdimdef UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>, 1615276479Sdim MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6; 1616193323Sed 1617276479Sdimdef MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>, 1618276479Sdim ISA_MIPS1_NOT_32R6_64R6; 1619276479Sdimdef MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>, 1620276479Sdim ISA_MIPS1_NOT_32R6_64R6; 1621276479Sdimlet EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug 1622276479Sdim AdditionalPredicates = [NotInMicroMips] in { 1623276479Sdimdef MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>, 1624276479Sdim ISA_MIPS1_NOT_32R6_64R6; 1625276479Sdimdef MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>, 1626276479Sdim ISA_MIPS1_NOT_32R6_64R6; 1627276479Sdim} 1628193323Sed 1629193323Sed/// Sign Ext In Register Instructions. 1630288943Sdimdef SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, 1631276479Sdim SEB_FM<0x10, 0x20>, ISA_MIPS32R2; 1632288943Sdimdef SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, 1633276479Sdim SEB_FM<0x18, 0x20>, ISA_MIPS32R2; 1634193323Sed 1635193323Sed/// Count Leading 1636276479Sdimdef CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>, 1637276479Sdim ISA_MIPS32_NOT_32R6_64R6; 1638276479Sdimdef CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>, 1639276479Sdim ISA_MIPS32_NOT_32R6_64R6; 1640193323Sed 1641296417Sdimlet AdditionalPredicates = [NotInMicroMips] in { 1642296417Sdim /// Word Swap Bytes Within Halfwords 1643296417Sdim def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM<2, 0x20>, 1644296417Sdim ISA_MIPS32R2; 1645296417Sdim} 1646193323Sed 1647249423Sdim/// No operation. 1648249423Sdimdef NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 1649193323Sed 1650193323Sed// FrameIndexes are legalized when they are operands from load/store 1651193323Sed// instructions. The same not happens for stack address copies, so an 1652193323Sed// add op with mem ComplexPattern is used and the stack address copy 1653193323Sed// can be matched. It's similar to Sparc LEA_ADDRi 1654276479Sdimdef LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>; 1655193323Sed 1656218893Sdim// MADD*/MSUB* 1657276479Sdimdef MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>, 1658276479Sdim ISA_MIPS32_NOT_32R6_64R6; 1659276479Sdimdef MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>, 1660276479Sdim ISA_MIPS32_NOT_32R6_64R6; 1661276479Sdimdef MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>, 1662276479Sdim ISA_MIPS32_NOT_32R6_64R6; 1663276479Sdimdef MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>, 1664276479Sdim ISA_MIPS32_NOT_32R6_64R6; 1665261991Sdim 1666276479Sdimlet AdditionalPredicates = [NotDSP] in { 1667276479Sdimdef PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>, 1668276479Sdim ISA_MIPS1_NOT_32R6_64R6; 1669276479Sdimdef PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>, 1670276479Sdim ISA_MIPS1_NOT_32R6_64R6; 1671276479Sdimdef PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6; 1672276479Sdimdef PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6; 1673276479Sdimdef PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6; 1674276479Sdimdef PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>, 1675276479Sdim ISA_MIPS32_NOT_32R6_64R6; 1676276479Sdimdef PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>, 1677276479Sdim ISA_MIPS32_NOT_32R6_64R6; 1678276479Sdimdef PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>, 1679276479Sdim ISA_MIPS32_NOT_32R6_64R6; 1680276479Sdimdef PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>, 1681276479Sdim ISA_MIPS32_NOT_32R6_64R6; 1682261991Sdim} 1683193323Sed 1684276479Sdimdef PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV, 1685276479Sdim 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6; 1686276479Sdimdef PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU, 1687276479Sdim 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6; 1688296417Sdimlet AdditionalPredicates = [NotInMicroMips] in { 1689280031Sdimdef RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM; 1690296417Sdim} 1691296417Sdim// TODO: Add '0 < pos+size <= 32' constraint check to ext instruction 1692296417Sdimdef EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, MipsExt>, 1693296417Sdim EXT_FM<0>; 1694261991Sdimdef INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>; 1695261991Sdim 1696249423Sdim/// Move Control Registers From/To CPU Registers 1697288943Sdimdef MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32; 1698288943Sdimdef MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32; 1699288943Sdimdef MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd>, MFC3OP_FM<0x12, 0>; 1700288943Sdimdef MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd>, MFC3OP_FM<0x12, 4>; 1701226633Sdim 1702276479Sdimclass Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary, 1703280031Sdim FrmOther, asmstr>; 1704296417Sdimdef SSNOP : MMRel, StdMMR6Rel, Barrier<"ssnop">, BARRIER_FM<1>; 1705280031Sdimdef EHB : MMRel, Barrier<"ehb">, BARRIER_FM<3>; 1706296417Sdimdef PAUSE : MMRel, StdMMR6Rel, Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2; 1707276479Sdim 1708276479Sdim// JR_HB and JALR_HB are defined here using the new style naming 1709276479Sdim// scheme because some of this code is shared with Mips32r6InstrInfo.td 1710276479Sdim// and because of that it doesn't follow the naming convention of the 1711276479Sdim// rest of the file. To avoid a mixture of old vs new style, the new 1712276479Sdim// style was chosen. 1713276479Sdimclass JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 1714276479Sdim dag OutOperandList = (outs); 1715276479Sdim dag InOperandList = (ins GPROpnd:$rs); 1716276479Sdim string AsmString = !strconcat(instr_asm, "\t$rs"); 1717276479Sdim list<dag> Pattern = []; 1718276479Sdim} 1719276479Sdim 1720276479Sdimclass JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 1721276479Sdim dag OutOperandList = (outs GPROpnd:$rd); 1722276479Sdim dag InOperandList = (ins GPROpnd:$rs); 1723276479Sdim string AsmString = !strconcat(instr_asm, "\t$rd, $rs"); 1724276479Sdim list<dag> Pattern = []; 1725276479Sdim} 1726276479Sdim 1727276479Sdimclass JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>, 1728276479Sdim JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> { 1729276479Sdim let isBranch=1; 1730276479Sdim let isIndirectBranch=1; 1731276479Sdim let hasDelaySlot=1; 1732276479Sdim let isTerminator=1; 1733276479Sdim let isBarrier=1; 1734276479Sdim} 1735276479Sdim 1736276479Sdimclass JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>, 1737276479Sdim JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> { 1738276479Sdim let isIndirectBranch=1; 1739276479Sdim let hasDelaySlot=1; 1740276479Sdim} 1741276479Sdim 1742276479Sdimclass JR_HB_ENC : JR_HB_FM<8>; 1743276479Sdimclass JALR_HB_ENC : JALR_HB_FM<9>; 1744276479Sdim 1745276479Sdimdef JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6; 1746276479Sdimdef JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32; 1747276479Sdim 1748276479Sdimclass TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary, 1749280031Sdim FrmOther, asmstr>; 1750280031Sdimdef TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>; 1751280031Sdimdef TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>; 1752280031Sdimdef TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>; 1753280031Sdimdef TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>; 1754276479Sdim 1755277320Sdimclass CacheOp<string instr_asm, Operand MemOpnd> : 1756276479Sdim InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint), 1757280031Sdim !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther, 1758280031Sdim instr_asm> { 1759277320Sdim let DecoderMethod = "DecodeCacheOp"; 1760277320Sdim} 1761276479Sdim 1762280031Sdimdef CACHE : MMRel, CacheOp<"cache", mem>, CACHEOP_FM<0b101111>, 1763276479Sdim INSN_MIPS3_32_NOT_32R6_64R6; 1764280031Sdimdef PREF : MMRel, CacheOp<"pref", mem>, CACHEOP_FM<0b110011>, 1765276479Sdim INSN_MIPS3_32_NOT_32R6_64R6; 1766276479Sdim 1767296417Sdimdef ROL : MipsAsmPseudoInst<(outs), 1768296417Sdim (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd), 1769296417Sdim "rol\t$rs, $rt, $rd">; 1770296417Sdimdef ROLImm : MipsAsmPseudoInst<(outs), 1771296417Sdim (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 1772296417Sdim "rol\t$rs, $rt, $imm">; 1773296417Sdimdef : MipsInstAlias<"rol $rd, $rs", 1774296417Sdim (ROL GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>; 1775296417Sdimdef : MipsInstAlias<"rol $rd, $imm", 1776296417Sdim (ROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>; 1777296417Sdim 1778296417Sdimdef ROR : MipsAsmPseudoInst<(outs), 1779296417Sdim (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd), 1780296417Sdim "ror\t$rs, $rt, $rd">; 1781296417Sdimdef RORImm : MipsAsmPseudoInst<(outs), 1782296417Sdim (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 1783296417Sdim "ror\t$rs, $rt, $imm">; 1784296417Sdimdef : MipsInstAlias<"ror $rd, $rs", 1785296417Sdim (ROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>; 1786296417Sdimdef : MipsInstAlias<"ror $rd, $imm", 1787296417Sdim (RORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>; 1788296417Sdim 1789296417Sdimdef DROL : MipsAsmPseudoInst<(outs), 1790296417Sdim (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd), 1791296417Sdim "drol\t$rs, $rt, $rd">, ISA_MIPS64; 1792296417Sdimdef DROLImm : MipsAsmPseudoInst<(outs), 1793296417Sdim (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 1794296417Sdim "drol\t$rs, $rt, $imm">, ISA_MIPS64; 1795296417Sdimdef : MipsInstAlias<"drol $rd, $rs", 1796296417Sdim (DROL GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, ISA_MIPS64; 1797296417Sdimdef : MipsInstAlias<"drol $rd, $imm", 1798296417Sdim (DROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, ISA_MIPS64; 1799296417Sdim 1800296417Sdimdef DROR : MipsAsmPseudoInst<(outs), 1801296417Sdim (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd), 1802296417Sdim "dror\t$rs, $rt, $rd">, ISA_MIPS64; 1803296417Sdimdef DRORImm : MipsAsmPseudoInst<(outs), 1804296417Sdim (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 1805296417Sdim "dror\t$rs, $rt, $imm">, ISA_MIPS64; 1806296417Sdimdef : MipsInstAlias<"dror $rd, $rs", 1807296417Sdim (DROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, ISA_MIPS64; 1808296417Sdimdef : MipsInstAlias<"dror $rd, $imm", 1809296417Sdim (DRORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, ISA_MIPS64; 1810296417Sdim 1811193323Sed//===----------------------------------------------------------------------===// 1812243830Sdim// Instruction aliases 1813243830Sdim//===----------------------------------------------------------------------===// 1814276479Sdimdef : MipsInstAlias<"move $dst, $src", 1815296417Sdim (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>, 1816276479Sdim GPR_32 { 1817276479Sdim let AdditionalPredicates = [NotInMicroMips]; 1818276479Sdim} 1819296417Sdimdef : MipsInstAlias<"move $dst, $src", 1820296417Sdim (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>, 1821296417Sdim GPR_32 { 1822296417Sdim let AdditionalPredicates = [NotInMicroMips]; 1823296417Sdim} 1824276479Sdimdef : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>, 1825276479Sdim ISA_MIPS1_NOT_32R6_64R6; 1826276479Sdimdef : MipsInstAlias<"addu $rs, $rt, $imm", 1827276479Sdim (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1828280031Sdimdef : MipsInstAlias<"addu $rs, $imm", 1829280031Sdim (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>; 1830276479Sdimdef : MipsInstAlias<"add $rs, $rt, $imm", 1831280031Sdim (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>, 1832280031Sdim ISA_MIPS1_NOT_32R6_64R6; 1833280031Sdimdef : MipsInstAlias<"add $rs, $imm", 1834280031Sdim (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>, 1835280031Sdim ISA_MIPS1_NOT_32R6_64R6; 1836276479Sdimdef : MipsInstAlias<"and $rs, $rt, $imm", 1837276479Sdim (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1838276479Sdimdef : MipsInstAlias<"and $rs, $imm", 1839276479Sdim (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>; 1840276479Sdimdef : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>; 1841276479Sdimlet Predicates = [NotInMicroMips] in { 1842276479Sdimdef : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1843276479Sdim} 1844276479Sdimdef : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32; 1845276479Sdimdef : MipsInstAlias<"not $rt, $rs", 1846276479Sdim (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; 1847276479Sdimdef : MipsInstAlias<"neg $rt, $rs", 1848276479Sdim (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1849276479Sdimdef : MipsInstAlias<"negu $rt", 1850276479Sdim (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>; 1851276479Sdimdef : MipsInstAlias<"negu $rt, $rs", 1852276479Sdim (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1853276479Sdimdef : MipsInstAlias<"slt $rs, $rt, $imm", 1854276479Sdim (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1855276479Sdimdef : MipsInstAlias<"sltu $rt, $rs, $imm", 1856276479Sdim (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>; 1857276479Sdimdef : MipsInstAlias<"xor $rs, $rt, $imm", 1858276479Sdim (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1859288943Sdimdef : MipsInstAlias<"xor $rs, $imm", 1860288943Sdim (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; 1861276479Sdimdef : MipsInstAlias<"or $rs, $rt, $imm", 1862276479Sdim (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1863276479Sdimdef : MipsInstAlias<"or $rs, $imm", 1864276479Sdim (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; 1865288943Sdimlet AdditionalPredicates = [NotInMicroMips] in { 1866276479Sdimdef : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1867288943Sdim} 1868288943Sdimdef : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>; 1869288943Sdimdef : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>; 1870288943Sdimdef : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>; 1871288943Sdimdef : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>; 1872288943Sdimlet AdditionalPredicates = [NotInMicroMips] in { 1873276479Sdimdef : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>; 1874288943Sdim} 1875276479Sdimdef : MipsInstAlias<"bnez $rs,$offset", 1876276479Sdim (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1877288943Sdimdef : MipsInstAlias<"bnezl $rs,$offset", 1878288943Sdim (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1879276479Sdimdef : MipsInstAlias<"beqz $rs,$offset", 1880276479Sdim (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1881288943Sdimdef : MipsInstAlias<"beqzl $rs,$offset", 1882288943Sdim (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1883276479Sdimdef : MipsInstAlias<"syscall", (SYSCALL 0), 1>; 1884296417Sdim 1885276479Sdimdef : MipsInstAlias<"break", (BREAK 0, 0), 1>; 1886276479Sdimdef : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; 1887288943Sdimlet AdditionalPredicates = [NotInMicroMips] in { 1888296417Sdim def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2; 1889296417Sdim def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2; 1890288943Sdim} 1891296417Sdimlet AdditionalPredicates = [NotInMicroMips] in { 1892296417Sdim def : MipsInstAlias<"teq $rs, $rt", 1893296417Sdim (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 1894296417Sdim def : MipsInstAlias<"tge $rs, $rt", 1895296417Sdim (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 1896296417Sdim def : MipsInstAlias<"tgeu $rs, $rt", 1897296417Sdim (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 1898296417Sdim def : MipsInstAlias<"tlt $rs, $rt", 1899296417Sdim (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 1900296417Sdim def : MipsInstAlias<"tltu $rs, $rt", 1901296417Sdim (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 1902296417Sdim def : MipsInstAlias<"tne $rs, $rt", 1903296417Sdim (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; 1904296417Sdim} 1905276479Sdimdef : MipsInstAlias<"sll $rd, $rt, $rs", 1906276479Sdim (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; 1907276479Sdimdef : MipsInstAlias<"sub, $rd, $rs, $imm", 1908276479Sdim (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, 1909280031Sdim InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6; 1910276479Sdimdef : MipsInstAlias<"sub $rs, $imm", 1911276479Sdim (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm), 1912280031Sdim 0>, ISA_MIPS1_NOT_32R6_64R6; 1913276479Sdimdef : MipsInstAlias<"subu, $rd, $rs, $imm", 1914276479Sdim (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, 1915276479Sdim InvertedImOperand:$imm), 0>; 1916276479Sdimdef : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, 1917276479Sdim InvertedImOperand:$imm), 0>; 1918276479Sdimdef : MipsInstAlias<"sra $rd, $rt, $rs", 1919276479Sdim (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; 1920276479Sdimdef : MipsInstAlias<"srl $rd, $rt, $rs", 1921276479Sdim (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; 1922276479Sdimdef : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6; 1923276479Sdimdef : MipsInstAlias<"sync", 1924276479Sdim (SYNC 0), 1>, ISA_MIPS2; 1925243830Sdim//===----------------------------------------------------------------------===// 1926249423Sdim// Assembler Pseudo Instructions 1927249423Sdim//===----------------------------------------------------------------------===// 1928249423Sdim 1929288943Sdimclass LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> : 1930249423Sdim MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1931249423Sdim !strconcat(instr_asm, "\t$rt, $imm32")> ; 1932296417Sdimdef LoadImm32 : LoadImmediate32<"li", simm32, GPR32Opnd>; 1933249423Sdim 1934288943Sdimclass LoadAddressFromReg32<string instr_asm, Operand MemOpnd, 1935288943Sdim RegisterOperand RO> : 1936249423Sdim MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1937249423Sdim !strconcat(instr_asm, "\t$rt, $addr")> ; 1938288943Sdimdef LoadAddrReg32 : LoadAddressFromReg32<"la", mem, GPR32Opnd>; 1939249423Sdim 1940288943Sdimclass LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> : 1941249423Sdim MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1942249423Sdim !strconcat(instr_asm, "\t$rt, $imm32")> ; 1943296417Sdimdef LoadAddrImm32 : LoadAddressFromImm32<"la", simm32, GPR32Opnd>; 1944249423Sdim 1945288943Sdimdef JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs), 1946288943Sdim "jal\t$rd, $rs"> ; 1947288943Sdimdef JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs), 1948288943Sdim "jal\t$rs"> ; 1949288943Sdim 1950296417Sdimdef NORImm : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 1951296417Sdim "nor\t$rs, $rt, $imm"> ; 1952296417Sdim 1953288943Sdimlet hasDelaySlot = 1 in { 1954288943Sdimdef BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), 1955288943Sdim (ins imm64:$imm64, brtarget:$offset), 1956288943Sdim "bne\t$rt, $imm64, $offset">; 1957288943Sdimdef BeqImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), 1958288943Sdim (ins imm64:$imm64, brtarget:$offset), 1959288943Sdim "beq\t$rt, $imm64, $offset">; 1960288943Sdim 1961288943Sdimclass CondBranchPseudo<string instr_asm> : 1962288943Sdim MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, 1963288943Sdim brtarget:$offset), 1964288943Sdim !strconcat(instr_asm, "\t$rs, $rt, $offset")>; 1965288943Sdim} 1966288943Sdim 1967288943Sdimdef BLT : CondBranchPseudo<"blt">; 1968288943Sdimdef BLE : CondBranchPseudo<"ble">; 1969288943Sdimdef BGE : CondBranchPseudo<"bge">; 1970288943Sdimdef BGT : CondBranchPseudo<"bgt">; 1971288943Sdimdef BLTU : CondBranchPseudo<"bltu">; 1972288943Sdimdef BLEU : CondBranchPseudo<"bleu">; 1973288943Sdimdef BGEU : CondBranchPseudo<"bgeu">; 1974288943Sdimdef BGTU : CondBranchPseudo<"bgtu">; 1975296417Sdimdef BLTL : CondBranchPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6; 1976296417Sdimdef BLEL : CondBranchPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6; 1977296417Sdimdef BGEL : CondBranchPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6; 1978296417Sdimdef BGTL : CondBranchPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6; 1979296417Sdimdef BLTUL: CondBranchPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6; 1980296417Sdimdef BLEUL: CondBranchPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6; 1981296417Sdimdef BGEUL: CondBranchPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6; 1982296417Sdimdef BGTUL: CondBranchPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6; 1983288943Sdim 1984296417Sdimclass CondBranchImmPseudo<string instr_asm> : 1985296417Sdim MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, imm64:$imm, brtarget:$offset), 1986296417Sdim !strconcat(instr_asm, "\t$rs, $imm, $offset")>; 1987296417Sdim 1988296417Sdimdef BLTImmMacro : CondBranchImmPseudo<"blt">; 1989296417Sdimdef BLEImmMacro : CondBranchImmPseudo<"ble">; 1990296417Sdimdef BGEImmMacro : CondBranchImmPseudo<"bge">; 1991296417Sdimdef BGTImmMacro : CondBranchImmPseudo<"bgt">; 1992296417Sdimdef BLTUImmMacro : CondBranchImmPseudo<"bltu">; 1993296417Sdimdef BLEUImmMacro : CondBranchImmPseudo<"bleu">; 1994296417Sdimdef BGEUImmMacro : CondBranchImmPseudo<"bgeu">; 1995296417Sdimdef BGTUImmMacro : CondBranchImmPseudo<"bgtu">; 1996296417Sdimdef BLTLImmMacro : CondBranchImmPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6; 1997296417Sdimdef BLELImmMacro : CondBranchImmPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6; 1998296417Sdimdef BGELImmMacro : CondBranchImmPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6; 1999296417Sdimdef BGTLImmMacro : CondBranchImmPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6; 2000296417Sdimdef BLTULImmMacro : CondBranchImmPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6; 2001296417Sdimdef BLEULImmMacro : CondBranchImmPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6; 2002296417Sdimdef BGEULImmMacro : CondBranchImmPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6; 2003296417Sdimdef BGTULImmMacro : CondBranchImmPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6; 2004296417Sdim 2005296417Sdim// FIXME: Predicates are removed because instructions are matched regardless of 2006296417Sdim// predicates, because PredicateControl was not in the hierarchy. This was 2007296417Sdim// done to emit more precise error message from expansion function. 2008296417Sdim// Once the tablegen-erated errors are made better, this needs to be fixed and 2009296417Sdim// predicates needs to be restored. 2010296417Sdim 2011296417Sdimdef SDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 2012296417Sdim "div\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6; 2013296417Sdim 2014296417Sdimdef UDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 2015296417Sdim "divu\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6; 2016296417Sdim 2017296417Sdimdef DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 2018296417Sdim "ddiv\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6; 2019296417Sdim 2020296417Sdimdef DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 2021296417Sdim "ddivu\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6; 2022296417Sdim 2023296417Sdimdef Ulh : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), 2024296417Sdim "ulh\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; 2025296417Sdim 2026288943Sdimdef Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), 2027296417Sdim "ulhu\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; 2028288943Sdim 2029288943Sdimdef Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), 2030296417Sdim "ulw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; 2031288943Sdim 2032249423Sdim//===----------------------------------------------------------------------===// 2033193323Sed// Arbitrary patterns that map to one or more instructions 2034193323Sed//===----------------------------------------------------------------------===// 2035193323Sed 2036249423Sdim// Load/store pattern templates. 2037249423Sdimclass LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : 2038249423Sdim MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; 2039249423Sdim 2040249423Sdimclass StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : 2041249423Sdim MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; 2042249423Sdim 2043193323Sed// Small immediates 2044280031Sdimlet AdditionalPredicates = [NotInMicroMips] in { 2045239462Sdimdef : MipsPat<(i32 immSExt16:$in), 2046239462Sdim (ADDiu ZERO, imm:$in)>; 2047239462Sdimdef : MipsPat<(i32 immZExt16:$in), 2048239462Sdim (ORi ZERO, imm:$in)>; 2049280031Sdim} 2050239462Sdimdef : MipsPat<(i32 immLow16Zero:$in), 2051239462Sdim (LUi (HI16 imm:$in))>; 2052193323Sed 2053193323Sed// Arbitrary immediates 2054239462Sdimdef : MipsPat<(i32 imm:$imm), 2055193323Sed (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 2056193323Sed 2057239462Sdim// Carry MipsPatterns 2058261991Sdimdef : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), 2059261991Sdim (SUBu GPR32:$lhs, GPR32:$rhs)>; 2060276479Sdimlet AdditionalPredicates = [NotDSP] in { 2061261991Sdim def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs), 2062261991Sdim (ADDu GPR32:$lhs, GPR32:$rhs)>; 2063261991Sdim def : MipsPat<(addc GPR32:$src, immSExt16:$imm), 2064261991Sdim (ADDiu GPR32:$src, imm:$imm)>; 2065251662Sdim} 2066193323Sed 2067280031Sdim// Support multiplication for pre-Mips32 targets that don't have 2068280031Sdim// the MUL instruction. 2069280031Sdimdef : MipsPat<(mul GPR32:$lhs, GPR32:$rhs), 2070280031Sdim (PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>, 2071280031Sdim ISA_MIPS1_NOT_32R6_64R6; 2072280031Sdim 2073276479Sdim// SYNC 2074276479Sdimdef : MipsPat<(MipsSync (i32 immz)), 2075276479Sdim (SYNC 0)>, ISA_MIPS2; 2076276479Sdim 2077193323Sed// Call 2078239462Sdimdef : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 2079239462Sdim (JAL texternalsym:$dst)>; 2080261991Sdim//def : MipsPat<(MipsJmpLink GPR32:$dst), 2081261991Sdim// (JALR GPR32:$dst)>; 2082193323Sed 2083243830Sdim// Tail call 2084243830Sdimdef : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 2085243830Sdim (TAILCALL tglobaladdr:$dst)>; 2086243830Sdimdef : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 2087243830Sdim (TAILCALL texternalsym:$dst)>; 2088193323Sed// hi/lo relocs 2089239462Sdimdef : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 2090239462Sdimdef : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 2091239462Sdimdef : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 2092239462Sdimdef : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 2093239462Sdimdef : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 2094244628Sdimdef : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 2095234353Sdim 2096239462Sdimdef : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 2097239462Sdimdef : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 2098239462Sdimdef : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 2099239462Sdimdef : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 2100239462Sdimdef : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 2101244628Sdimdef : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 2102234353Sdim 2103261991Sdimdef : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)), 2104261991Sdim (ADDiu GPR32:$hi, tglobaladdr:$lo)>; 2105261991Sdimdef : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)), 2106261991Sdim (ADDiu GPR32:$hi, tblockaddress:$lo)>; 2107261991Sdimdef : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)), 2108261991Sdim (ADDiu GPR32:$hi, tjumptable:$lo)>; 2109261991Sdimdef : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)), 2110261991Sdim (ADDiu GPR32:$hi, tconstpool:$lo)>; 2111261991Sdimdef : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)), 2112261991Sdim (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>; 2113193323Sed 2114193323Sed// gp_rel relocs 2115261991Sdimdef : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)), 2116261991Sdim (ADDiu GPR32:$gp, tglobaladdr:$in)>; 2117261991Sdimdef : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)), 2118261991Sdim (ADDiu GPR32:$gp, tconstpool:$in)>; 2119193323Sed 2120223017Sdim// wrapper_pic 2121234353Sdimclass WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 2122239462Sdim MipsPat<(MipsWrapper RC:$gp, node:$in), 2123239462Sdim (ADDiuOp RC:$gp, node:$in)>; 2124223017Sdim 2125261991Sdimdef : WrapperPat<tglobaladdr, ADDiu, GPR32>; 2126261991Sdimdef : WrapperPat<tconstpool, ADDiu, GPR32>; 2127261991Sdimdef : WrapperPat<texternalsym, ADDiu, GPR32>; 2128261991Sdimdef : WrapperPat<tblockaddress, ADDiu, GPR32>; 2129261991Sdimdef : WrapperPat<tjumptable, ADDiu, GPR32>; 2130261991Sdimdef : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>; 2131223017Sdim 2132288943Sdimlet AdditionalPredicates = [NotInMicroMips] in { 2133193323Sed// Mips does not have "not", so we expand our way 2134261991Sdimdef : MipsPat<(not GPR32:$in), 2135261991Sdim (NOR GPR32Opnd:$in, ZERO)>; 2136288943Sdim} 2137193323Sed 2138234353Sdim// extended loads 2139276479Sdimdef : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 2140276479Sdimdef : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 2141276479Sdimdef : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 2142193323Sed 2143193323Sed// peepholes 2144261991Sdimdef : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 2145193323Sed 2146193323Sed// brcond patterns 2147226633Sdimmulticlass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 2148226633Sdim Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 2149226633Sdim Instruction SLTiuOp, Register ZEROReg> { 2150239462Sdimdef : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 2151239462Sdim (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 2152239462Sdimdef : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 2153239462Sdim (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 2154193323Sed 2155239462Sdimdef : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 2156239462Sdim (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 2157239462Sdimdef : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 2158239462Sdim (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 2159239462Sdimdef : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 2160239462Sdim (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 2161239462Sdimdef : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 2162239462Sdim (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 2163261991Sdimdef : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 2164261991Sdim (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 2165261991Sdimdef : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 2166261991Sdim (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 2167193323Sed 2168239462Sdimdef : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 2169239462Sdim (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 2170239462Sdimdef : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 2171239462Sdim (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 2172193323Sed 2173239462Sdimdef : MipsPat<(brcond RC:$cond, bb:$dst), 2174239462Sdim (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 2175226633Sdim} 2176193323Sed 2177261991Sdimdefm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 2178226633Sdim 2179261991Sdimdef : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), 2180261991Sdim (BLEZ i32:$lhs, bb:$dst)>; 2181261991Sdimdef : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), 2182261991Sdim (BGEZ i32:$lhs, bb:$dst)>; 2183261991Sdim 2184193323Sed// setcc patterns 2185226633Sdimmulticlass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 2186226633Sdim Instruction SLTuOp, Register ZEROReg> { 2187261991Sdim def : MipsPat<(seteq RC:$lhs, 0), 2188261991Sdim (SLTiuOp RC:$lhs, 1)>; 2189261991Sdim def : MipsPat<(setne RC:$lhs, 0), 2190261991Sdim (SLTuOp ZEROReg, RC:$lhs)>; 2191239462Sdim def : MipsPat<(seteq RC:$lhs, RC:$rhs), 2192239462Sdim (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 2193239462Sdim def : MipsPat<(setne RC:$lhs, RC:$rhs), 2194239462Sdim (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 2195226633Sdim} 2196193323Sed 2197226633Sdimmulticlass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 2198239462Sdim def : MipsPat<(setle RC:$lhs, RC:$rhs), 2199239462Sdim (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 2200239462Sdim def : MipsPat<(setule RC:$lhs, RC:$rhs), 2201239462Sdim (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 2202226633Sdim} 2203193323Sed 2204226633Sdimmulticlass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 2205239462Sdim def : MipsPat<(setgt RC:$lhs, RC:$rhs), 2206239462Sdim (SLTOp RC:$rhs, RC:$lhs)>; 2207239462Sdim def : MipsPat<(setugt RC:$lhs, RC:$rhs), 2208239462Sdim (SLTuOp RC:$rhs, RC:$lhs)>; 2209226633Sdim} 2210193323Sed 2211226633Sdimmulticlass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 2212239462Sdim def : MipsPat<(setge RC:$lhs, RC:$rhs), 2213239462Sdim (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 2214239462Sdim def : MipsPat<(setuge RC:$lhs, RC:$rhs), 2215239462Sdim (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 2216226633Sdim} 2217193323Sed 2218226633Sdimmulticlass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 2219226633Sdim Instruction SLTiuOp> { 2220239462Sdim def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 2221239462Sdim (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 2222239462Sdim def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 2223239462Sdim (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 2224226633Sdim} 2225193323Sed 2226261991Sdimdefm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>; 2227261991Sdimdefm : SetlePats<GPR32, SLT, SLTu>; 2228261991Sdimdefm : SetgtPats<GPR32, SLT, SLTu>; 2229261991Sdimdefm : SetgePats<GPR32, SLT, SLTu>; 2230261991Sdimdefm : SetgeImmPats<GPR32, SLTi, SLTiu>; 2231226633Sdim 2232234353Sdim// bswap pattern 2233261991Sdimdef : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>; 2234234353Sdim 2235249423Sdim// Load halfword/word patterns. 2236249423Sdimlet AddedComplexity = 40 in { 2237276479Sdim def : LoadRegImmPat<LBu, i32, zextloadi8>; 2238276479Sdim def : LoadRegImmPat<LH, i32, sextloadi16>; 2239288943Sdim let AdditionalPredicates = [NotInMicroMips] in { 2240276479Sdim def : LoadRegImmPat<LW, i32, load>; 2241288943Sdim } 2242249423Sdim} 2243249423Sdim 2244296417Sdim// Atomic load patterns. 2245296417Sdimdef : MipsPat<(atomic_load_8 addr:$a), (LB addr:$a)>; 2246296417Sdimdef : MipsPat<(atomic_load_16 addr:$a), (LH addr:$a)>; 2247296417Sdimdef : MipsPat<(atomic_load_32 addr:$a), (LW addr:$a)>; 2248296417Sdim 2249296417Sdim// Atomic store patterns. 2250296417Sdimdef : MipsPat<(atomic_store_8 addr:$a, GPR32:$v), (SB GPR32:$v, addr:$a)>; 2251296417Sdimdef : MipsPat<(atomic_store_16 addr:$a, GPR32:$v), (SH GPR32:$v, addr:$a)>; 2252296417Sdimdef : MipsPat<(atomic_store_32 addr:$a, GPR32:$v), (SW GPR32:$v, addr:$a)>; 2253296417Sdim 2254193323Sed//===----------------------------------------------------------------------===// 2255193323Sed// Floating Point Support 2256193323Sed//===----------------------------------------------------------------------===// 2257193323Sed 2258193323Sedinclude "MipsInstrFPU.td" 2259226633Sdiminclude "Mips64InstrInfo.td" 2260234353Sdiminclude "MipsCondMov.td" 2261193323Sed 2262276479Sdiminclude "Mips32r6InstrInfo.td" 2263276479Sdiminclude "Mips64r6InstrInfo.td" 2264276479Sdim 2265239462Sdim// 2266239462Sdim// Mips16 2267239462Sdim 2268239462Sdiminclude "Mips16InstrFormats.td" 2269239462Sdiminclude "Mips16InstrInfo.td" 2270243830Sdim 2271243830Sdim// DSP 2272243830Sdiminclude "MipsDSPInstrFormats.td" 2273243830Sdiminclude "MipsDSPInstrInfo.td" 2274243830Sdim 2275261991Sdim// MSA 2276261991Sdiminclude "MipsMSAInstrFormats.td" 2277261991Sdiminclude "MipsMSAInstrInfo.td" 2278261991Sdim 2279296417Sdim// EVA 2280296417Sdiminclude "MipsEVAInstrFormats.td" 2281296417Sdiminclude "MipsEVAInstrInfo.td" 2282296417Sdim 2283251662Sdim// Micromips 2284251662Sdiminclude "MicroMipsInstrFormats.td" 2285251662Sdiminclude "MicroMipsInstrInfo.td" 2286276479Sdiminclude "MicroMipsInstrFPU.td" 2287288943Sdim 2288288943Sdim// Micromips r6 2289288943Sdiminclude "MicroMips32r6InstrFormats.td" 2290288943Sdiminclude "MicroMips32r6InstrInfo.td" 2291296417Sdim 2292296417Sdim// Micromips64 r6 2293296417Sdiminclude "MicroMips64r6InstrFormats.td" 2294296417Sdiminclude "MicroMips64r6InstrInfo.td" 2295296417Sdim 2296296417Sdim// Micromips DSP 2297296417Sdiminclude "MicroMipsDSPInstrFormats.td" 2298296417Sdiminclude "MicroMipsDSPInstrInfo.td" 2299