MipsInstrInfo.cpp revision 243830
1234353Sdim//===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file contains the Mips implementation of the TargetInstrInfo class. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14239462Sdim#include "MipsAnalyzeImmediate.h" 15193323Sed#include "MipsInstrInfo.h" 16193323Sed#include "MipsTargetMachine.h" 17193399Sed#include "MipsMachineFunction.h" 18224145Sdim#include "InstPrinter/MipsInstPrinter.h" 19193323Sed#include "llvm/CodeGen/MachineInstrBuilder.h" 20193399Sed#include "llvm/CodeGen/MachineRegisterInfo.h" 21198090Srdivacky#include "llvm/Support/ErrorHandling.h" 22226633Sdim#include "llvm/Support/TargetRegistry.h" 23224145Sdim#include "llvm/ADT/STLExtras.h" 24224145Sdim 25224145Sdim#define GET_INSTRINFO_CTOR 26193323Sed#include "MipsGenInstrInfo.inc" 27193323Sed 28193323Sedusing namespace llvm; 29193323Sed 30239462SdimMipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm, unsigned UncondBr) 31224145Sdim : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), 32239462Sdim TM(tm), UncondBrOpc(UncondBr) {} 33193323Sed 34239462Sdimconst MipsInstrInfo *MipsInstrInfo::create(MipsTargetMachine &TM) { 35239462Sdim if (TM.getSubtargetImpl()->inMips16Mode()) 36239462Sdim return llvm::createMips16InstrInfo(TM); 37239462Sdim 38239462Sdim return llvm::createMipsSEInstrInfo(TM); 39224145Sdim} 40224145Sdim 41239462Sdimbool MipsInstrInfo::isZeroImm(const MachineOperand &op) const { 42193323Sed return op.isImm() && op.getImm() == 0; 43193323Sed} 44193323Sed 45193323Sed/// insertNoop - If data hazard condition is found insert the target nop 46193323Sed/// instruction. 47193323Sedvoid MipsInstrInfo:: 48221345SdiminsertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const 49193323Sed{ 50206124Srdivacky DebugLoc DL; 51193323Sed BuildMI(MBB, MI, DL, get(Mips::NOP)); 52193323Sed} 53193323Sed 54239462SdimMachineMemOperand *MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI, 55239462Sdim unsigned Flag) const { 56234353Sdim MachineFunction &MF = *MBB.getParent(); 57234353Sdim MachineFrameInfo &MFI = *MF.getFrameInfo(); 58234353Sdim unsigned Align = MFI.getObjectAlignment(FI); 59234353Sdim 60234353Sdim return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag, 61234353Sdim MFI.getObjectSize(FI), Align); 62234353Sdim} 63234353Sdim 64224145SdimMachineInstr* 65224145SdimMipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx, 66224145Sdim uint64_t Offset, const MDNode *MDPtr, 67224145Sdim DebugLoc DL) const { 68224145Sdim MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE)) 69224145Sdim .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 70224145Sdim return &*MIB; 71224145Sdim} 72224145Sdim 73193323Sed//===----------------------------------------------------------------------===// 74193323Sed// Branch Analysis 75193323Sed//===----------------------------------------------------------------------===// 76193323Sed 77239462Sdimvoid MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, 78239462Sdim MachineBasicBlock *&BB, 79239462Sdim SmallVectorImpl<MachineOperand> &Cond) const { 80221345Sdim assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch"); 81221345Sdim int NumOp = Inst->getNumExplicitOperands(); 82234353Sdim 83221345Sdim // for both int and fp branches, the last explicit operand is the 84221345Sdim // MBB. 85221345Sdim BB = Inst->getOperand(NumOp-1).getMBB(); 86221345Sdim Cond.push_back(MachineOperand::CreateImm(Opc)); 87221345Sdim 88221345Sdim for (int i=0; i<NumOp-1; i++) 89221345Sdim Cond.push_back(Inst->getOperand(i)); 90193323Sed} 91193323Sed 92221345Sdimbool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 93193323Sed MachineBasicBlock *&TBB, 94193323Sed MachineBasicBlock *&FBB, 95193323Sed SmallVectorImpl<MachineOperand> &Cond, 96221345Sdim bool AllowModify) const 97193323Sed{ 98243830Sdim 99221345Sdim MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); 100221345Sdim 101221345Sdim // Skip all the debug instructions. 102221345Sdim while (I != REnd && I->isDebugValue()) 103221345Sdim ++I; 104221345Sdim 105221345Sdim if (I == REnd || !isUnpredicatedTerminator(&*I)) { 106221345Sdim // If this block ends with no branches (it just falls through to its succ) 107221345Sdim // just return false, leaving TBB/FBB null. 108221345Sdim TBB = FBB = NULL; 109193323Sed return false; 110206083Srdivacky } 111221345Sdim 112221345Sdim MachineInstr *LastInst = &*I; 113193323Sed unsigned LastOpc = LastInst->getOpcode(); 114221345Sdim 115221345Sdim // Not an analyzable branch (must be an indirect jump). 116221345Sdim if (!GetAnalyzableBrOpc(LastOpc)) 117221345Sdim return true; 118221345Sdim 119221345Sdim // Get the second to last instruction in the block. 120221345Sdim unsigned SecondLastOpc = 0; 121221345Sdim MachineInstr *SecondLastInst = NULL; 122221345Sdim 123221345Sdim if (++I != REnd) { 124221345Sdim SecondLastInst = &*I; 125221345Sdim SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode()); 126221345Sdim 127221345Sdim // Not an analyzable branch (must be an indirect jump). 128221345Sdim if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc) 129193323Sed return true; 130221345Sdim } 131193323Sed 132221345Sdim // If there is only one terminator instruction, process it. 133221345Sdim if (!SecondLastOpc) { 134193323Sed // Unconditional branch 135234353Sdim if (LastOpc == UncondBrOpc) { 136193323Sed TBB = LastInst->getOperand(0).getMBB(); 137193323Sed return false; 138193323Sed } 139193323Sed 140193323Sed // Conditional branch 141221345Sdim AnalyzeCondBr(LastInst, LastOpc, TBB, Cond); 142221345Sdim return false; 143221345Sdim } 144193323Sed 145221345Sdim // If we reached here, there are two branches. 146193323Sed // If there are three terminators, we don't know what sort of block this is. 147221345Sdim if (++I != REnd && isUnpredicatedTerminator(&*I)) 148193323Sed return true; 149193323Sed 150221345Sdim // If second to last instruction is an unconditional branch, 151221345Sdim // analyze it and remove the last instruction. 152234353Sdim if (SecondLastOpc == UncondBrOpc) { 153221345Sdim // Return if the last instruction cannot be removed. 154221345Sdim if (!AllowModify) 155221345Sdim return true; 156193323Sed 157221345Sdim TBB = SecondLastInst->getOperand(0).getMBB(); 158221345Sdim LastInst->eraseFromParent(); 159221345Sdim return false; 160221345Sdim } 161193323Sed 162221345Sdim // Conditional branch followed by an unconditional branch. 163221345Sdim // The last one must be unconditional. 164234353Sdim if (LastOpc != UncondBrOpc) 165221345Sdim return true; 166193323Sed 167221345Sdim AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); 168221345Sdim FBB = LastInst->getOperand(0).getMBB(); 169193323Sed 170221345Sdim return false; 171234353Sdim} 172234353Sdim 173221345Sdimvoid MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, 174221345Sdim MachineBasicBlock *TBB, DebugLoc DL, 175221345Sdim const SmallVectorImpl<MachineOperand>& Cond) 176221345Sdim const { 177221345Sdim unsigned Opc = Cond[0].getImm(); 178224145Sdim const MCInstrDesc &MCID = get(Opc); 179224145Sdim MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); 180193323Sed 181243830Sdim for (unsigned i = 1; i < Cond.size(); ++i) { 182243830Sdim if (Cond[i].isReg()) 183243830Sdim MIB.addReg(Cond[i].getReg()); 184243830Sdim else if (Cond[i].isImm()) 185243830Sdim MIB.addImm(Cond[i].getImm()); 186243830Sdim else 187243830Sdim assert(true && "Cannot copy operand"); 188243830Sdim } 189221345Sdim MIB.addMBB(TBB); 190193323Sed} 191193323Sed 192193323Sedunsigned MipsInstrInfo:: 193221345SdimInsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 194193323Sed MachineBasicBlock *FBB, 195210299Sed const SmallVectorImpl<MachineOperand> &Cond, 196210299Sed DebugLoc DL) const { 197193323Sed // Shouldn't be a fall through. 198193323Sed assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 199193323Sed 200221345Sdim // # of condition operands: 201221345Sdim // Unconditional branches: 0 202221345Sdim // Floating point branches: 1 (opc) 203221345Sdim // Int BranchZero: 2 (opc, reg) 204221345Sdim // Int Branch: 3 (opc, reg0, reg1) 205221345Sdim assert((Cond.size() <= 3) && 206221345Sdim "# of Mips branch conditions must be <= 3!"); 207193323Sed 208221345Sdim // Two-way Conditional branch. 209221345Sdim if (FBB) { 210221345Sdim BuildCondBr(MBB, TBB, DL, Cond); 211234353Sdim BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB); 212221345Sdim return 2; 213193323Sed } 214193323Sed 215221345Sdim // One way branch. 216221345Sdim // Unconditional branch. 217221345Sdim if (Cond.empty()) 218234353Sdim BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB); 219221345Sdim else // Conditional branch. 220221345Sdim BuildCondBr(MBB, TBB, DL, Cond); 221221345Sdim return 1; 222193323Sed} 223193323Sed 224193323Sedunsigned MipsInstrInfo:: 225221345SdimRemoveBranch(MachineBasicBlock &MBB) const 226193323Sed{ 227221345Sdim MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); 228221345Sdim MachineBasicBlock::reverse_iterator FirstBr; 229221345Sdim unsigned removed; 230221345Sdim 231221345Sdim // Skip all the debug instructions. 232221345Sdim while (I != REnd && I->isDebugValue()) 233221345Sdim ++I; 234221345Sdim 235221345Sdim FirstBr = I; 236221345Sdim 237221345Sdim // Up to 2 branches are removed. 238221345Sdim // Note that indirect branches are not removed. 239221345Sdim for(removed = 0; I != REnd && removed < 2; ++I, ++removed) 240221345Sdim if (!GetAnalyzableBrOpc(I->getOpcode())) 241221345Sdim break; 242221345Sdim 243221345Sdim MBB.erase(I.base(), FirstBr.base()); 244221345Sdim 245221345Sdim return removed; 246193323Sed} 247193323Sed 248221345Sdim/// ReverseBranchCondition - Return the inverse opcode of the 249193323Sed/// specified Branch instruction. 250193323Sedbool MipsInstrInfo:: 251221345SdimReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const 252193323Sed{ 253221345Sdim assert( (Cond.size() && Cond.size() <= 3) && 254193323Sed "Invalid Mips branch condition!"); 255239462Sdim Cond[0].setImm(GetOppositeBranchOpc(Cond[0].getImm())); 256193323Sed return false; 257193323Sed} 258193399Sed 259239462Sdim/// Return the number of bytes of code the specified instruction may be. 260239462Sdimunsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 261239462Sdim switch (MI->getOpcode()) { 262239462Sdim default: 263239462Sdim return MI->getDesc().getSize(); 264239462Sdim case TargetOpcode::INLINEASM: { // Inline Asm: Variable size. 265239462Sdim const MachineFunction *MF = MI->getParent()->getParent(); 266239462Sdim const char *AsmStr = MI->getOperand(0).getSymbolName(); 267239462Sdim return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); 268239462Sdim } 269239462Sdim } 270239462Sdim} 271