MipsInstrInfo.cpp revision 234353
1234353Sdim//===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file contains the Mips implementation of the TargetInstrInfo class. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed#include "MipsInstrInfo.h" 15193323Sed#include "MipsTargetMachine.h" 16193399Sed#include "MipsMachineFunction.h" 17224145Sdim#include "InstPrinter/MipsInstPrinter.h" 18193323Sed#include "llvm/CodeGen/MachineInstrBuilder.h" 19193399Sed#include "llvm/CodeGen/MachineRegisterInfo.h" 20198090Srdivacky#include "llvm/Support/ErrorHandling.h" 21226633Sdim#include "llvm/Support/TargetRegistry.h" 22224145Sdim#include "llvm/ADT/STLExtras.h" 23224145Sdim 24224145Sdim#define GET_INSTRINFO_CTOR 25193323Sed#include "MipsGenInstrInfo.inc" 26193323Sed 27193323Sedusing namespace llvm; 28193323Sed 29193323SedMipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm) 30224145Sdim : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), 31226633Sdim TM(tm), IsN64(TM.getSubtarget<MipsSubtarget>().isABI_N64()), 32234353Sdim RI(*TM.getSubtargetImpl(), *this), 33234353Sdim UncondBrOpc(TM.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J) {} 34193323Sed 35234353Sdimconst MipsRegisterInfo &MipsInstrInfo::getRegisterInfo() const { 36224145Sdim return RI; 37224145Sdim} 38224145Sdim 39193323Sedstatic bool isZeroImm(const MachineOperand &op) { 40193323Sed return op.isImm() && op.getImm() == 0; 41193323Sed} 42193323Sed 43193323Sed/// isLoadFromStackSlot - If the specified machine instruction is a direct 44193323Sed/// load from a stack slot, return the virtual or physical register number of 45193323Sed/// the destination along with the FrameIndex of the loaded stack slot. If 46193323Sed/// not, return 0. This predicate must return 0 if the instruction has 47193323Sed/// any side effects other than loading from the stack slot. 48193323Sedunsigned MipsInstrInfo:: 49221345SdimisLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const 50193323Sed{ 51226633Sdim unsigned Opc = MI->getOpcode(); 52226633Sdim 53226633Sdim if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) || 54226633Sdim (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) || 55226633Sdim (Opc == Mips::LDC1) || (Opc == Mips::LDC164) || 56226633Sdim (Opc == Mips::LDC164_P8)) { 57224145Sdim if ((MI->getOperand(1).isFI()) && // is a stack slot 58224145Sdim (MI->getOperand(2).isImm()) && // the imm is zero 59224145Sdim (isZeroImm(MI->getOperand(2)))) { 60224145Sdim FrameIndex = MI->getOperand(1).getIndex(); 61193323Sed return MI->getOperand(0).getReg(); 62193323Sed } 63193323Sed } 64193323Sed 65193323Sed return 0; 66193323Sed} 67193323Sed 68193323Sed/// isStoreToStackSlot - If the specified machine instruction is a direct 69193323Sed/// store to a stack slot, return the virtual or physical register number of 70193323Sed/// the source reg along with the FrameIndex of the loaded stack slot. If 71193323Sed/// not, return 0. This predicate must return 0 if the instruction has 72193323Sed/// any side effects other than storing to the stack slot. 73193323Sedunsigned MipsInstrInfo:: 74221345SdimisStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const 75193323Sed{ 76226633Sdim unsigned Opc = MI->getOpcode(); 77226633Sdim 78226633Sdim if ((Opc == Mips::SW) || (Opc == Mips::SW_P8) || (Opc == Mips::SD) || 79226633Sdim (Opc == Mips::SD_P8) || (Opc == Mips::SWC1) || (Opc == Mips::SWC1_P8) || 80226633Sdim (Opc == Mips::SDC1) || (Opc == Mips::SDC164) || 81226633Sdim (Opc == Mips::SDC164_P8)) { 82224145Sdim if ((MI->getOperand(1).isFI()) && // is a stack slot 83224145Sdim (MI->getOperand(2).isImm()) && // the imm is zero 84224145Sdim (isZeroImm(MI->getOperand(2)))) { 85224145Sdim FrameIndex = MI->getOperand(1).getIndex(); 86193323Sed return MI->getOperand(0).getReg(); 87193323Sed } 88193323Sed } 89193323Sed return 0; 90193323Sed} 91193323Sed 92193323Sed/// insertNoop - If data hazard condition is found insert the target nop 93193323Sed/// instruction. 94193323Sedvoid MipsInstrInfo:: 95221345SdiminsertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const 96193323Sed{ 97206124Srdivacky DebugLoc DL; 98193323Sed BuildMI(MBB, MI, DL, get(Mips::NOP)); 99193323Sed} 100193323Sed 101210299Sedvoid MipsInstrInfo:: 102210299SedcopyPhysReg(MachineBasicBlock &MBB, 103210299Sed MachineBasicBlock::iterator I, DebugLoc DL, 104210299Sed unsigned DestReg, unsigned SrcReg, 105210299Sed bool KillSrc) const { 106226633Sdim unsigned Opc = 0, ZeroReg = 0; 107193323Sed 108226633Sdim if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg. 109226633Sdim if (Mips::CPURegsRegClass.contains(SrcReg)) 110226633Sdim Opc = Mips::ADDu, ZeroReg = Mips::ZERO; 111226633Sdim else if (Mips::CCRRegClass.contains(SrcReg)) 112226633Sdim Opc = Mips::CFC1; 113210299Sed else if (Mips::FGR32RegClass.contains(SrcReg)) 114226633Sdim Opc = Mips::MFC1; 115210299Sed else if (SrcReg == Mips::HI) 116226633Sdim Opc = Mips::MFHI, SrcReg = 0; 117210299Sed else if (SrcReg == Mips::LO) 118226633Sdim Opc = Mips::MFLO, SrcReg = 0; 119210299Sed } 120226633Sdim else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg. 121210299Sed if (Mips::CCRRegClass.contains(DestReg)) 122226633Sdim Opc = Mips::CTC1; 123210299Sed else if (Mips::FGR32RegClass.contains(DestReg)) 124226633Sdim Opc = Mips::MTC1; 125210299Sed else if (DestReg == Mips::HI) 126226633Sdim Opc = Mips::MTHI, DestReg = 0; 127210299Sed else if (DestReg == Mips::LO) 128226633Sdim Opc = Mips::MTLO, DestReg = 0; 129210299Sed } 130226633Sdim else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) 131226633Sdim Opc = Mips::FMOV_S; 132226633Sdim else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) 133226633Sdim Opc = Mips::FMOV_D32; 134234353Sdim else if (Mips::FGR64RegClass.contains(DestReg, SrcReg)) 135234353Sdim Opc = Mips::FMOV_D64; 136226633Sdim else if (Mips::CCRRegClass.contains(DestReg, SrcReg)) 137226633Sdim Opc = Mips::MOVCCRToCCR; 138226633Sdim else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg. 139226633Sdim if (Mips::CPU64RegsRegClass.contains(SrcReg)) 140226633Sdim Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64; 141226633Sdim else if (SrcReg == Mips::HI64) 142226633Sdim Opc = Mips::MFHI64, SrcReg = 0; 143226633Sdim else if (SrcReg == Mips::LO64) 144226633Sdim Opc = Mips::MFLO64, SrcReg = 0; 145234353Sdim else if (Mips::FGR64RegClass.contains(SrcReg)) 146234353Sdim Opc = Mips::DMFC1; 147210299Sed } 148226633Sdim else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg. 149226633Sdim if (DestReg == Mips::HI64) 150226633Sdim Opc = Mips::MTHI64, DestReg = 0; 151226633Sdim else if (DestReg == Mips::LO64) 152226633Sdim Opc = Mips::MTLO64, DestReg = 0; 153234353Sdim else if (Mips::FGR64RegClass.contains(DestReg)) 154234353Sdim Opc = Mips::DMTC1; 155210299Sed } 156193323Sed 157226633Sdim assert(Opc && "Cannot copy registers"); 158226633Sdim 159226633Sdim MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); 160234353Sdim 161226633Sdim if (DestReg) 162226633Sdim MIB.addReg(DestReg, RegState::Define); 163226633Sdim 164226633Sdim if (ZeroReg) 165226633Sdim MIB.addReg(ZeroReg); 166226633Sdim 167226633Sdim if (SrcReg) 168226633Sdim MIB.addReg(SrcReg, getKillRegState(KillSrc)); 169193323Sed} 170193323Sed 171234353Sdimstatic MachineMemOperand* GetMemOperand(MachineBasicBlock &MBB, int FI, 172234353Sdim unsigned Flag) { 173234353Sdim MachineFunction &MF = *MBB.getParent(); 174234353Sdim MachineFrameInfo &MFI = *MF.getFrameInfo(); 175234353Sdim unsigned Align = MFI.getObjectAlignment(FI); 176234353Sdim 177234353Sdim return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag, 178234353Sdim MFI.getObjectSize(FI), Align); 179234353Sdim} 180234353Sdim 181193323Sedvoid MipsInstrInfo:: 182193323SedstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 183221345Sdim unsigned SrcReg, bool isKill, int FI, 184208599Srdivacky const TargetRegisterClass *RC, 185208599Srdivacky const TargetRegisterInfo *TRI) const { 186206124Srdivacky DebugLoc DL; 187193323Sed if (I != MBB.end()) DL = I->getDebugLoc(); 188234353Sdim MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); 189234353Sdim 190226633Sdim unsigned Opc = 0; 191193323Sed 192221345Sdim if (RC == Mips::CPURegsRegisterClass) 193226633Sdim Opc = IsN64 ? Mips::SW_P8 : Mips::SW; 194226633Sdim else if (RC == Mips::CPU64RegsRegisterClass) 195226633Sdim Opc = IsN64 ? Mips::SD_P8 : Mips::SD; 196193323Sed else if (RC == Mips::FGR32RegisterClass) 197226633Sdim Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1; 198226633Sdim else if (RC == Mips::AFGR64RegisterClass) 199226633Sdim Opc = Mips::SDC1; 200226633Sdim else if (RC == Mips::FGR64RegisterClass) 201226633Sdim Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164; 202226633Sdim 203226633Sdim assert(Opc && "Register class not handled!"); 204226633Sdim BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) 205234353Sdim .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 206193323Sed} 207193323Sed 208193323Sedvoid MipsInstrInfo:: 209193323SedloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 210193323Sed unsigned DestReg, int FI, 211208599Srdivacky const TargetRegisterClass *RC, 212221345Sdim const TargetRegisterInfo *TRI) const 213193323Sed{ 214206124Srdivacky DebugLoc DL; 215199989Srdivacky if (I != MBB.end()) DL = I->getDebugLoc(); 216234353Sdim MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad); 217226633Sdim unsigned Opc = 0; 218199989Srdivacky 219221345Sdim if (RC == Mips::CPURegsRegisterClass) 220226633Sdim Opc = IsN64 ? Mips::LW_P8 : Mips::LW; 221226633Sdim else if (RC == Mips::CPU64RegsRegisterClass) 222226633Sdim Opc = IsN64 ? Mips::LD_P8 : Mips::LD; 223193323Sed else if (RC == Mips::FGR32RegisterClass) 224226633Sdim Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1; 225226633Sdim else if (RC == Mips::AFGR64RegisterClass) 226226633Sdim Opc = Mips::LDC1; 227226633Sdim else if (RC == Mips::FGR64RegisterClass) 228226633Sdim Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164; 229226633Sdim 230226633Sdim assert(Opc && "Register class not handled!"); 231234353Sdim BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0) 232234353Sdim .addMemOperand(MMO); 233193323Sed} 234193323Sed 235224145SdimMachineInstr* 236224145SdimMipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx, 237224145Sdim uint64_t Offset, const MDNode *MDPtr, 238224145Sdim DebugLoc DL) const { 239224145Sdim MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE)) 240224145Sdim .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 241224145Sdim return &*MIB; 242224145Sdim} 243224145Sdim 244193323Sed//===----------------------------------------------------------------------===// 245193323Sed// Branch Analysis 246193323Sed//===----------------------------------------------------------------------===// 247193323Sed 248221345Sdimstatic unsigned GetAnalyzableBrOpc(unsigned Opc) { 249226633Sdim return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ || 250226633Sdim Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || 251226633Sdim Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || 252226633Sdim Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || 253234353Sdim Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B || 254234353Sdim Opc == Mips::J) ? 255226633Sdim Opc : 0; 256193323Sed} 257193323Sed 258221345Sdim/// GetOppositeBranchOpc - Return the inverse of the specified 259221345Sdim/// opcode, e.g. turning BEQ to BNE. 260221345Sdimunsigned Mips::GetOppositeBranchOpc(unsigned Opc) 261193323Sed{ 262221345Sdim switch (Opc) { 263234353Sdim default: llvm_unreachable("Illegal opcode!"); 264234353Sdim case Mips::BEQ: return Mips::BNE; 265234353Sdim case Mips::BNE: return Mips::BEQ; 266234353Sdim case Mips::BGTZ: return Mips::BLEZ; 267234353Sdim case Mips::BGEZ: return Mips::BLTZ; 268234353Sdim case Mips::BLTZ: return Mips::BGEZ; 269234353Sdim case Mips::BLEZ: return Mips::BGTZ; 270234353Sdim case Mips::BEQ64: return Mips::BNE64; 271234353Sdim case Mips::BNE64: return Mips::BEQ64; 272234353Sdim case Mips::BGTZ64: return Mips::BLEZ64; 273234353Sdim case Mips::BGEZ64: return Mips::BLTZ64; 274234353Sdim case Mips::BLTZ64: return Mips::BGEZ64; 275234353Sdim case Mips::BLEZ64: return Mips::BGTZ64; 276234353Sdim case Mips::BC1T: return Mips::BC1F; 277234353Sdim case Mips::BC1F: return Mips::BC1T; 278193323Sed } 279193323Sed} 280193323Sed 281221345Sdimstatic void AnalyzeCondBr(const MachineInstr* Inst, unsigned Opc, 282221345Sdim MachineBasicBlock *&BB, 283221345Sdim SmallVectorImpl<MachineOperand>& Cond) { 284221345Sdim assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch"); 285221345Sdim int NumOp = Inst->getNumExplicitOperands(); 286234353Sdim 287221345Sdim // for both int and fp branches, the last explicit operand is the 288221345Sdim // MBB. 289221345Sdim BB = Inst->getOperand(NumOp-1).getMBB(); 290221345Sdim Cond.push_back(MachineOperand::CreateImm(Opc)); 291221345Sdim 292221345Sdim for (int i=0; i<NumOp-1; i++) 293221345Sdim Cond.push_back(Inst->getOperand(i)); 294193323Sed} 295193323Sed 296221345Sdimbool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 297193323Sed MachineBasicBlock *&TBB, 298193323Sed MachineBasicBlock *&FBB, 299193323Sed SmallVectorImpl<MachineOperand> &Cond, 300221345Sdim bool AllowModify) const 301193323Sed{ 302221345Sdim MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); 303221345Sdim 304221345Sdim // Skip all the debug instructions. 305221345Sdim while (I != REnd && I->isDebugValue()) 306221345Sdim ++I; 307221345Sdim 308221345Sdim if (I == REnd || !isUnpredicatedTerminator(&*I)) { 309221345Sdim // If this block ends with no branches (it just falls through to its succ) 310221345Sdim // just return false, leaving TBB/FBB null. 311221345Sdim TBB = FBB = NULL; 312193323Sed return false; 313206083Srdivacky } 314221345Sdim 315221345Sdim MachineInstr *LastInst = &*I; 316193323Sed unsigned LastOpc = LastInst->getOpcode(); 317221345Sdim 318221345Sdim // Not an analyzable branch (must be an indirect jump). 319221345Sdim if (!GetAnalyzableBrOpc(LastOpc)) 320221345Sdim return true; 321221345Sdim 322221345Sdim // Get the second to last instruction in the block. 323221345Sdim unsigned SecondLastOpc = 0; 324221345Sdim MachineInstr *SecondLastInst = NULL; 325221345Sdim 326221345Sdim if (++I != REnd) { 327221345Sdim SecondLastInst = &*I; 328221345Sdim SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode()); 329221345Sdim 330221345Sdim // Not an analyzable branch (must be an indirect jump). 331221345Sdim if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc) 332193323Sed return true; 333221345Sdim } 334193323Sed 335221345Sdim // If there is only one terminator instruction, process it. 336221345Sdim if (!SecondLastOpc) { 337193323Sed // Unconditional branch 338234353Sdim if (LastOpc == UncondBrOpc) { 339193323Sed TBB = LastInst->getOperand(0).getMBB(); 340193323Sed return false; 341193323Sed } 342193323Sed 343193323Sed // Conditional branch 344221345Sdim AnalyzeCondBr(LastInst, LastOpc, TBB, Cond); 345221345Sdim return false; 346221345Sdim } 347193323Sed 348221345Sdim // If we reached here, there are two branches. 349193323Sed // If there are three terminators, we don't know what sort of block this is. 350221345Sdim if (++I != REnd && isUnpredicatedTerminator(&*I)) 351193323Sed return true; 352193323Sed 353221345Sdim // If second to last instruction is an unconditional branch, 354221345Sdim // analyze it and remove the last instruction. 355234353Sdim if (SecondLastOpc == UncondBrOpc) { 356221345Sdim // Return if the last instruction cannot be removed. 357221345Sdim if (!AllowModify) 358221345Sdim return true; 359193323Sed 360221345Sdim TBB = SecondLastInst->getOperand(0).getMBB(); 361221345Sdim LastInst->eraseFromParent(); 362221345Sdim return false; 363221345Sdim } 364193323Sed 365221345Sdim // Conditional branch followed by an unconditional branch. 366221345Sdim // The last one must be unconditional. 367234353Sdim if (LastOpc != UncondBrOpc) 368221345Sdim return true; 369193323Sed 370221345Sdim AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); 371221345Sdim FBB = LastInst->getOperand(0).getMBB(); 372193323Sed 373221345Sdim return false; 374234353Sdim} 375234353Sdim 376221345Sdimvoid MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, 377221345Sdim MachineBasicBlock *TBB, DebugLoc DL, 378221345Sdim const SmallVectorImpl<MachineOperand>& Cond) 379221345Sdim const { 380221345Sdim unsigned Opc = Cond[0].getImm(); 381224145Sdim const MCInstrDesc &MCID = get(Opc); 382224145Sdim MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); 383193323Sed 384221345Sdim for (unsigned i = 1; i < Cond.size(); ++i) 385221345Sdim MIB.addReg(Cond[i].getReg()); 386221345Sdim 387221345Sdim MIB.addMBB(TBB); 388193323Sed} 389193323Sed 390193323Sedunsigned MipsInstrInfo:: 391221345SdimInsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 392193323Sed MachineBasicBlock *FBB, 393210299Sed const SmallVectorImpl<MachineOperand> &Cond, 394210299Sed DebugLoc DL) const { 395193323Sed // Shouldn't be a fall through. 396193323Sed assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 397193323Sed 398221345Sdim // # of condition operands: 399221345Sdim // Unconditional branches: 0 400221345Sdim // Floating point branches: 1 (opc) 401221345Sdim // Int BranchZero: 2 (opc, reg) 402221345Sdim // Int Branch: 3 (opc, reg0, reg1) 403221345Sdim assert((Cond.size() <= 3) && 404221345Sdim "# of Mips branch conditions must be <= 3!"); 405193323Sed 406221345Sdim // Two-way Conditional branch. 407221345Sdim if (FBB) { 408221345Sdim BuildCondBr(MBB, TBB, DL, Cond); 409234353Sdim BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB); 410221345Sdim return 2; 411193323Sed } 412193323Sed 413221345Sdim // One way branch. 414221345Sdim // Unconditional branch. 415221345Sdim if (Cond.empty()) 416234353Sdim BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB); 417221345Sdim else // Conditional branch. 418221345Sdim BuildCondBr(MBB, TBB, DL, Cond); 419221345Sdim return 1; 420193323Sed} 421193323Sed 422193323Sedunsigned MipsInstrInfo:: 423221345SdimRemoveBranch(MachineBasicBlock &MBB) const 424193323Sed{ 425221345Sdim MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); 426221345Sdim MachineBasicBlock::reverse_iterator FirstBr; 427221345Sdim unsigned removed; 428221345Sdim 429221345Sdim // Skip all the debug instructions. 430221345Sdim while (I != REnd && I->isDebugValue()) 431221345Sdim ++I; 432221345Sdim 433221345Sdim FirstBr = I; 434221345Sdim 435221345Sdim // Up to 2 branches are removed. 436221345Sdim // Note that indirect branches are not removed. 437221345Sdim for(removed = 0; I != REnd && removed < 2; ++I, ++removed) 438221345Sdim if (!GetAnalyzableBrOpc(I->getOpcode())) 439221345Sdim break; 440221345Sdim 441221345Sdim MBB.erase(I.base(), FirstBr.base()); 442221345Sdim 443221345Sdim return removed; 444193323Sed} 445193323Sed 446221345Sdim/// ReverseBranchCondition - Return the inverse opcode of the 447193323Sed/// specified Branch instruction. 448193323Sedbool MipsInstrInfo:: 449221345SdimReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const 450193323Sed{ 451221345Sdim assert( (Cond.size() && Cond.size() <= 3) && 452193323Sed "Invalid Mips branch condition!"); 453221345Sdim Cond[0].setImm(Mips::GetOppositeBranchOpc(Cond[0].getImm())); 454193323Sed return false; 455193323Sed} 456193399Sed 457