1234353Sdim//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed// Describe MIPS instructions format 12193323Sed// 13193323Sed// CPU INSTRUCTION FORMATS 14193323Sed// 15193323Sed// opcode - operation code. 16193323Sed// rs - src reg. 17193323Sed// rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 18193323Sed// rd - dst reg, only used on 3 regs instr. 19193323Sed// shamt - only used on shift instructions, contains the shift amount. 20193323Sed// funct - combined with opcode field give us an operation code. 21193323Sed// 22193323Sed//===----------------------------------------------------------------------===// 23193323Sed 24228379Sdim// Format specifies the encoding used by the instruction. This is part of the 25228379Sdim// ad-hoc solution used to emit machine instruction encodings by our machine 26228379Sdim// code emitter. 27228379Sdimclass Format<bits<4> val> { 28228379Sdim bits<4> Value = val; 29228379Sdim} 30228379Sdim 31228379Sdimdef Pseudo : Format<0>; 32228379Sdimdef FrmR : Format<1>; 33228379Sdimdef FrmI : Format<2>; 34228379Sdimdef FrmJ : Format<3>; 35228379Sdimdef FrmFR : Format<4>; 36228379Sdimdef FrmFI : Format<5>; 37228379Sdimdef FrmOther : Format<6>; // Instruction w/ a custom format 38228379Sdim 39251662Sdimclass MMRel; 40251662Sdim 41251662Sdimdef Std2MicroMips : InstrMapping { 42251662Sdim let FilterClass = "MMRel"; 43251662Sdim // Instructions with the same BaseOpcode and isNVStore values form a row. 44251662Sdim let RowFields = ["BaseOpcode"]; 45251662Sdim // Instructions with the same predicate sense form a column. 46251662Sdim let ColFields = ["Arch"]; 47251662Sdim // The key column is the unpredicated instructions. 48251662Sdim let KeyCol = ["se"]; 49251662Sdim // Value columns are PredSense=true and PredSense=false 50251662Sdim let ValueCols = [["se"], ["micromips"]]; 51251662Sdim} 52251662Sdim 53288943Sdimclass StdMMR6Rel; 54288943Sdim 55288943Sdimdef Std2MicroMipsR6 : InstrMapping { 56288943Sdim let FilterClass = "StdMMR6Rel"; 57288943Sdim // Instructions with the same BaseOpcode and isNVStore values form a row. 58288943Sdim let RowFields = ["BaseOpcode"]; 59288943Sdim // Instructions with the same predicate sense form a column. 60288943Sdim let ColFields = ["Arch"]; 61288943Sdim // The key column is the unpredicated instructions. 62288943Sdim let KeyCol = ["se"]; 63288943Sdim // Value columns are PredSense=true and PredSense=false 64288943Sdim let ValueCols = [["se"], ["micromipsr6"]]; 65288943Sdim} 66288943Sdim 67251662Sdimclass StdArch { 68251662Sdim string Arch = "se"; 69251662Sdim} 70251662Sdim 71193323Sed// Generic Mips Format 72221345Sdimclass MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern, 73228379Sdim InstrItinClass itin, Format f>: Instruction 74193323Sed{ 75193323Sed field bits<32> Inst; 76228379Sdim Format Form = f; 77193323Sed 78193323Sed let Namespace = "Mips"; 79193323Sed 80234982Sdim let Size = 4; 81234982Sdim 82228379Sdim bits<6> Opcode = 0; 83193323Sed 84228379Sdim // Top 6 bits are the 'opcode' field 85228379Sdim let Inst{31-26} = Opcode; 86221345Sdim 87228379Sdim let OutOperandList = outs; 88228379Sdim let InOperandList = ins; 89193323Sed 90193323Sed let AsmString = asmstr; 91193323Sed let Pattern = pattern; 92193323Sed let Itinerary = itin; 93228379Sdim 94228379Sdim // 95228379Sdim // Attributes specific to Mips instructions... 96228379Sdim // 97228379Sdim bits<4> FormBits = Form.Value; 98228379Sdim 99228379Sdim // TSFlags layout should be kept in sync with MipsInstrInfo.h. 100228379Sdim let TSFlags{3-0} = FormBits; 101234982Sdim 102234982Sdim let DecoderNamespace = "Mips"; 103234982Sdim 104234982Sdim field bits<32> SoftFail = 0; 105193323Sed} 106193323Sed 107239462Sdim// Mips32/64 Instruction Format 108239462Sdimclass InstSE<dag outs, dag ins, string asmstr, list<dag> pattern, 109251662Sdim InstrItinClass itin, Format f, string opstr = ""> : 110276479Sdim MipsInst<outs, ins, asmstr, pattern, itin, f>, PredicateControl { 111276479Sdim let EncodingPredicates = [HasStdEnc]; 112251662Sdim string BaseOpcode = opstr; 113251662Sdim string Arch; 114239462Sdim} 115239462Sdim 116193323Sed// Mips Pseudo Instructions Format 117249423Sdimclass MipsPseudo<dag outs, dag ins, list<dag> pattern, 118249423Sdim InstrItinClass itin = IIPseudo> : 119249423Sdim MipsInst<outs, ins, "", pattern, itin, Pseudo> { 120228379Sdim let isCodeGenOnly = 1; 121226633Sdim let isPseudo = 1; 122226633Sdim} 123193323Sed 124239462Sdim// Mips32/64 Pseudo Instruction Format 125249423Sdimclass PseudoSE<dag outs, dag ins, list<dag> pattern, 126276479Sdim InstrItinClass itin = IIPseudo> : 127276479Sdim MipsPseudo<outs, ins, pattern, itin>, PredicateControl { 128276479Sdim let EncodingPredicates = [HasStdEnc]; 129239462Sdim} 130239462Sdim 131243830Sdim// Pseudo-instructions for alternate assembly syntax (never used by codegen). 132243830Sdim// These are aliases that require C++ handling to convert to the target 133243830Sdim// instruction, while InstAliases can be handled directly by tblgen. 134243830Sdimclass MipsAsmPseudoInst<dag outs, dag ins, string asmstr>: 135296417Sdim MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo>, PredicateControl { 136243830Sdim let isPseudo = 1; 137243830Sdim let Pattern = []; 138243830Sdim} 139193323Sed//===----------------------------------------------------------------------===// 140193323Sed// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> 141193323Sed//===----------------------------------------------------------------------===// 142193323Sed 143193323Sedclass FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr, 144193323Sed list<dag> pattern, InstrItinClass itin>: 145239462Sdim InstSE<outs, ins, asmstr, pattern, itin, FrmR> 146193323Sed{ 147193323Sed bits<5> rd; 148193323Sed bits<5> rs; 149193323Sed bits<5> rt; 150193323Sed bits<5> shamt; 151193323Sed bits<6> funct; 152193323Sed 153228379Sdim let Opcode = op; 154193323Sed let funct = _funct; 155193323Sed 156193323Sed let Inst{25-21} = rs; 157221345Sdim let Inst{20-16} = rt; 158193323Sed let Inst{15-11} = rd; 159193323Sed let Inst{10-6} = shamt; 160193323Sed let Inst{5-0} = funct; 161193323Sed} 162193323Sed 163193323Sed//===----------------------------------------------------------------------===// 164193323Sed// Format I instruction class in Mips : <|opcode|rs|rt|immediate|> 165193323Sed//===----------------------------------------------------------------------===// 166193323Sed 167193323Sedclass FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 168239462Sdim InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI> 169193323Sed{ 170193323Sed bits<5> rt; 171193323Sed bits<5> rs; 172193323Sed bits<16> imm16; 173193323Sed 174228379Sdim let Opcode = op; 175193323Sed 176193323Sed let Inst{25-21} = rs; 177221345Sdim let Inst{20-16} = rt; 178193323Sed let Inst{15-0} = imm16; 179193323Sed} 180193323Sed 181234353Sdimclass BranchBase<bits<6> op, dag outs, dag ins, string asmstr, 182226633Sdim list<dag> pattern, InstrItinClass itin>: 183239462Sdim InstSE<outs, ins, asmstr, pattern, itin, FrmI> 184226633Sdim{ 185226633Sdim bits<5> rs; 186226633Sdim bits<5> rt; 187226633Sdim bits<16> imm16; 188226633Sdim 189228379Sdim let Opcode = op; 190226633Sdim 191226633Sdim let Inst{25-21} = rs; 192226633Sdim let Inst{20-16} = rt; 193226633Sdim let Inst{15-0} = imm16; 194226633Sdim} 195226633Sdim 196193323Sed//===----------------------------------------------------------------------===// 197193323Sed// Format J instruction class in Mips : <|opcode|address|> 198193323Sed//===----------------------------------------------------------------------===// 199193323Sed 200261991Sdimclass FJ<bits<6> op> : StdArch 201193323Sed{ 202249423Sdim bits<26> target; 203193323Sed 204249423Sdim bits<32> Inst; 205221345Sdim 206249423Sdim let Inst{31-26} = op; 207249423Sdim let Inst{25-0} = target; 208193323Sed} 209193323Sed 210249423Sdim//===----------------------------------------------------------------------===// 211243830Sdim// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|> 212193323Sed//===----------------------------------------------------------------------===// 213249423Sdimclass MFC3OP_FM<bits<6> op, bits<5> mfmt> 214243830Sdim{ 215243830Sdim bits<5> rt; 216243830Sdim bits<5> rd; 217243830Sdim bits<3> sel; 218243830Sdim 219249423Sdim bits<32> Inst; 220243830Sdim 221249423Sdim let Inst{31-26} = op; 222243830Sdim let Inst{25-21} = mfmt; 223243830Sdim let Inst{20-16} = rt; 224243830Sdim let Inst{15-11} = rd; 225243830Sdim let Inst{10-3} = 0; 226243830Sdim let Inst{2-0} = sel; 227243830Sdim} 228243830Sdim 229288943Sdimclass MFC2OP_FM<bits<6> op, bits<5> mfmt> : StdArch { 230288943Sdim bits<5> rt; 231288943Sdim bits<16> imm16; 232288943Sdim 233288943Sdim bits<32> Inst; 234288943Sdim 235288943Sdim let Inst{31-26} = op; 236288943Sdim let Inst{25-21} = mfmt; 237288943Sdim let Inst{20-16} = rt; 238288943Sdim let Inst{15-0} = imm16; 239288943Sdim} 240288943Sdim 241251662Sdimclass ADD_FM<bits<6> op, bits<6> funct> : StdArch { 242249423Sdim bits<5> rd; 243249423Sdim bits<5> rs; 244249423Sdim bits<5> rt; 245249423Sdim 246249423Sdim bits<32> Inst; 247249423Sdim 248249423Sdim let Inst{31-26} = op; 249249423Sdim let Inst{25-21} = rs; 250249423Sdim let Inst{20-16} = rt; 251249423Sdim let Inst{15-11} = rd; 252249423Sdim let Inst{10-6} = 0; 253249423Sdim let Inst{5-0} = funct; 254249423Sdim} 255249423Sdim 256251662Sdimclass ADDI_FM<bits<6> op> : StdArch { 257249423Sdim bits<5> rs; 258249423Sdim bits<5> rt; 259249423Sdim bits<16> imm16; 260249423Sdim 261249423Sdim bits<32> Inst; 262249423Sdim 263249423Sdim let Inst{31-26} = op; 264249423Sdim let Inst{25-21} = rs; 265249423Sdim let Inst{20-16} = rt; 266249423Sdim let Inst{15-0} = imm16; 267249423Sdim} 268249423Sdim 269251662Sdimclass SRA_FM<bits<6> funct, bit rotate> : StdArch { 270249423Sdim bits<5> rd; 271249423Sdim bits<5> rt; 272249423Sdim bits<5> shamt; 273249423Sdim 274249423Sdim bits<32> Inst; 275249423Sdim 276249423Sdim let Inst{31-26} = 0; 277249423Sdim let Inst{25-22} = 0; 278249423Sdim let Inst{21} = rotate; 279249423Sdim let Inst{20-16} = rt; 280249423Sdim let Inst{15-11} = rd; 281249423Sdim let Inst{10-6} = shamt; 282249423Sdim let Inst{5-0} = funct; 283249423Sdim} 284249423Sdim 285251662Sdimclass SRLV_FM<bits<6> funct, bit rotate> : StdArch { 286249423Sdim bits<5> rd; 287249423Sdim bits<5> rt; 288249423Sdim bits<5> rs; 289249423Sdim 290249423Sdim bits<32> Inst; 291249423Sdim 292249423Sdim let Inst{31-26} = 0; 293249423Sdim let Inst{25-21} = rs; 294249423Sdim let Inst{20-16} = rt; 295249423Sdim let Inst{15-11} = rd; 296249423Sdim let Inst{10-7} = 0; 297249423Sdim let Inst{6} = rotate; 298249423Sdim let Inst{5-0} = funct; 299249423Sdim} 300249423Sdim 301261991Sdimclass BEQ_FM<bits<6> op> : StdArch { 302249423Sdim bits<5> rs; 303249423Sdim bits<5> rt; 304249423Sdim bits<16> offset; 305249423Sdim 306249423Sdim bits<32> Inst; 307249423Sdim 308249423Sdim let Inst{31-26} = op; 309249423Sdim let Inst{25-21} = rs; 310249423Sdim let Inst{20-16} = rt; 311249423Sdim let Inst{15-0} = offset; 312249423Sdim} 313249423Sdim 314261991Sdimclass BGEZ_FM<bits<6> op, bits<5> funct> : StdArch { 315249423Sdim bits<5> rs; 316249423Sdim bits<16> offset; 317249423Sdim 318249423Sdim bits<32> Inst; 319249423Sdim 320249423Sdim let Inst{31-26} = op; 321249423Sdim let Inst{25-21} = rs; 322249423Sdim let Inst{20-16} = funct; 323249423Sdim let Inst{15-0} = offset; 324249423Sdim} 325249423Sdim 326288943Sdimclass BBIT_FM<bits<6> op> : StdArch { 327288943Sdim bits<5> rs; 328288943Sdim bits<5> p; 329288943Sdim bits<16> offset; 330288943Sdim 331288943Sdim bits<32> Inst; 332288943Sdim 333288943Sdim let Inst{31-26} = op; 334288943Sdim let Inst{25-21} = rs; 335288943Sdim let Inst{20-16} = p; 336288943Sdim let Inst{15-0} = offset; 337288943Sdim} 338288943Sdim 339251662Sdimclass SLTI_FM<bits<6> op> : StdArch { 340249423Sdim bits<5> rt; 341249423Sdim bits<5> rs; 342249423Sdim bits<16> imm16; 343249423Sdim 344249423Sdim bits<32> Inst; 345249423Sdim 346249423Sdim let Inst{31-26} = op; 347249423Sdim let Inst{25-21} = rs; 348249423Sdim let Inst{20-16} = rt; 349249423Sdim let Inst{15-0} = imm16; 350249423Sdim} 351249423Sdim 352261991Sdimclass MFLO_FM<bits<6> funct> : StdArch { 353249423Sdim bits<5> rd; 354249423Sdim 355249423Sdim bits<32> Inst; 356249423Sdim 357249423Sdim let Inst{31-26} = 0; 358249423Sdim let Inst{25-16} = 0; 359249423Sdim let Inst{15-11} = rd; 360249423Sdim let Inst{10-6} = 0; 361249423Sdim let Inst{5-0} = funct; 362249423Sdim} 363249423Sdim 364261991Sdimclass MTLO_FM<bits<6> funct> : StdArch { 365249423Sdim bits<5> rs; 366249423Sdim 367249423Sdim bits<32> Inst; 368249423Sdim 369249423Sdim let Inst{31-26} = 0; 370249423Sdim let Inst{25-21} = rs; 371249423Sdim let Inst{20-6} = 0; 372249423Sdim let Inst{5-0} = funct; 373249423Sdim} 374249423Sdim 375261991Sdimclass SEB_FM<bits<5> funct, bits<6> funct2> : StdArch { 376249423Sdim bits<5> rd; 377249423Sdim bits<5> rt; 378249423Sdim 379249423Sdim bits<32> Inst; 380249423Sdim 381249423Sdim let Inst{31-26} = 0x1f; 382249423Sdim let Inst{25-21} = 0; 383249423Sdim let Inst{20-16} = rt; 384249423Sdim let Inst{15-11} = rd; 385249423Sdim let Inst{10-6} = funct; 386249423Sdim let Inst{5-0} = funct2; 387249423Sdim} 388249423Sdim 389261991Sdimclass CLO_FM<bits<6> funct> : StdArch { 390249423Sdim bits<5> rd; 391249423Sdim bits<5> rs; 392249423Sdim bits<5> rt; 393249423Sdim 394249423Sdim bits<32> Inst; 395249423Sdim 396249423Sdim let Inst{31-26} = 0x1c; 397249423Sdim let Inst{25-21} = rs; 398249423Sdim let Inst{20-16} = rt; 399249423Sdim let Inst{15-11} = rd; 400249423Sdim let Inst{10-6} = 0; 401249423Sdim let Inst{5-0} = funct; 402249423Sdim let rt = rd; 403249423Sdim} 404249423Sdim 405261991Sdimclass LUI_FM : StdArch { 406249423Sdim bits<5> rt; 407249423Sdim bits<16> imm16; 408249423Sdim 409249423Sdim bits<32> Inst; 410249423Sdim 411249423Sdim let Inst{31-26} = 0xf; 412249423Sdim let Inst{25-21} = 0; 413249423Sdim let Inst{20-16} = rt; 414249423Sdim let Inst{15-0} = imm16; 415249423Sdim} 416249423Sdim 417276479Sdimclass JALR_FM { 418249423Sdim bits<5> rd; 419249423Sdim bits<5> rs; 420249423Sdim 421249423Sdim bits<32> Inst; 422249423Sdim 423249423Sdim let Inst{31-26} = 0; 424249423Sdim let Inst{25-21} = rs; 425249423Sdim let Inst{20-16} = 0; 426249423Sdim let Inst{15-11} = rd; 427249423Sdim let Inst{10-6} = 0; 428249423Sdim let Inst{5-0} = 9; 429249423Sdim} 430249423Sdim 431261991Sdimclass BGEZAL_FM<bits<5> funct> : StdArch { 432249423Sdim bits<5> rs; 433249423Sdim bits<16> offset; 434249423Sdim 435249423Sdim bits<32> Inst; 436249423Sdim 437249423Sdim let Inst{31-26} = 1; 438249423Sdim let Inst{25-21} = rs; 439249423Sdim let Inst{20-16} = funct; 440249423Sdim let Inst{15-0} = offset; 441249423Sdim} 442249423Sdim 443276479Sdimclass SYNC_FM : StdArch { 444249423Sdim bits<5> stype; 445249423Sdim 446249423Sdim bits<32> Inst; 447249423Sdim 448249423Sdim let Inst{31-26} = 0; 449249423Sdim let Inst{10-6} = stype; 450249423Sdim let Inst{5-0} = 0xf; 451249423Sdim} 452249423Sdim 453280031Sdimclass SYNCI_FM : StdArch { 454280031Sdim // Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding). 455280031Sdim bits<21> addr; 456280031Sdim bits<5> rs = addr{20-16}; 457280031Sdim bits<16> offset = addr{15-0}; 458280031Sdim 459280031Sdim bits<32> Inst; 460280031Sdim 461280031Sdim let Inst{31-26} = 0b000001; 462280031Sdim let Inst{25-21} = rs; 463280031Sdim let Inst{20-16} = 0b11111; 464280031Sdim let Inst{15-0} = offset; 465280031Sdim} 466280031Sdim 467251662Sdimclass MULT_FM<bits<6> op, bits<6> funct> : StdArch { 468249423Sdim bits<5> rs; 469249423Sdim bits<5> rt; 470249423Sdim 471249423Sdim bits<32> Inst; 472249423Sdim 473249423Sdim let Inst{31-26} = op; 474249423Sdim let Inst{25-21} = rs; 475249423Sdim let Inst{20-16} = rt; 476249423Sdim let Inst{15-6} = 0; 477249423Sdim let Inst{5-0} = funct; 478249423Sdim} 479249423Sdim 480261991Sdimclass EXT_FM<bits<6> funct> : StdArch { 481249423Sdim bits<5> rt; 482249423Sdim bits<5> rs; 483249423Sdim bits<5> pos; 484249423Sdim bits<5> size; 485249423Sdim 486249423Sdim bits<32> Inst; 487249423Sdim 488249423Sdim let Inst{31-26} = 0x1f; 489249423Sdim let Inst{25-21} = rs; 490249423Sdim let Inst{20-16} = rt; 491249423Sdim let Inst{15-11} = size; 492249423Sdim let Inst{10-6} = pos; 493249423Sdim let Inst{5-0} = funct; 494249423Sdim} 495249423Sdim 496280031Sdimclass RDHWR_FM : StdArch { 497249423Sdim bits<5> rt; 498249423Sdim bits<5> rd; 499249423Sdim 500249423Sdim bits<32> Inst; 501249423Sdim 502249423Sdim let Inst{31-26} = 0x1f; 503249423Sdim let Inst{25-21} = 0; 504249423Sdim let Inst{20-16} = rt; 505249423Sdim let Inst{15-11} = rd; 506249423Sdim let Inst{10-6} = 0; 507249423Sdim let Inst{5-0} = 0x3b; 508249423Sdim} 509249423Sdim 510261991Sdimclass TEQ_FM<bits<6> funct> : StdArch { 511261991Sdim bits<5> rs; 512261991Sdim bits<5> rt; 513261991Sdim bits<10> code_; 514261991Sdim 515261991Sdim bits<32> Inst; 516261991Sdim 517261991Sdim let Inst{31-26} = 0; 518261991Sdim let Inst{25-21} = rs; 519261991Sdim let Inst{20-16} = rt; 520261991Sdim let Inst{15-6} = code_; 521261991Sdim let Inst{5-0} = funct; 522261991Sdim} 523261991Sdim 524261991Sdimclass TEQI_FM<bits<5> funct> : StdArch { 525261991Sdim bits<5> rs; 526261991Sdim bits<16> imm16; 527261991Sdim 528261991Sdim bits<32> Inst; 529261991Sdim 530261991Sdim let Inst{31-26} = 1; 531261991Sdim let Inst{25-21} = rs; 532261991Sdim let Inst{20-16} = funct; 533261991Sdim let Inst{15-0} = imm16; 534261991Sdim} 535276479Sdim 536276479Sdimclass WAIT_FM : StdArch { 537276479Sdim bits<32> Inst; 538276479Sdim 539276479Sdim let Inst{31-26} = 0x10; 540276479Sdim let Inst{25} = 1; 541276479Sdim let Inst{24-6} = 0; 542276479Sdim let Inst{5-0} = 0x20; 543276479Sdim} 544276479Sdim 545276479Sdimclass EXTS_FM<bits<6> funct> : StdArch { 546276479Sdim bits<5> rt; 547276479Sdim bits<5> rs; 548276479Sdim bits<5> pos; 549276479Sdim bits<5> lenm1; 550276479Sdim 551276479Sdim bits<32> Inst; 552276479Sdim 553276479Sdim let Inst{31-26} = 0x1c; 554276479Sdim let Inst{25-21} = rs; 555276479Sdim let Inst{20-16} = rt; 556276479Sdim let Inst{15-11} = lenm1; 557276479Sdim let Inst{10-6} = pos; 558276479Sdim let Inst{5-0} = funct; 559276479Sdim} 560276479Sdim 561276479Sdimclass MTMR_FM<bits<6> funct> : StdArch { 562276479Sdim bits<5> rs; 563276479Sdim 564276479Sdim bits<32> Inst; 565276479Sdim 566276479Sdim let Inst{31-26} = 0x1c; 567276479Sdim let Inst{25-21} = rs; 568276479Sdim let Inst{20-6} = 0; 569276479Sdim let Inst{5-0} = funct; 570276479Sdim} 571276479Sdim 572276479Sdimclass POP_FM<bits<6> funct> : StdArch { 573276479Sdim bits<5> rd; 574276479Sdim bits<5> rs; 575276479Sdim 576276479Sdim bits<32> Inst; 577276479Sdim 578276479Sdim let Inst{31-26} = 0x1c; 579276479Sdim let Inst{25-21} = rs; 580276479Sdim let Inst{20-16} = 0; 581276479Sdim let Inst{15-11} = rd; 582276479Sdim let Inst{10-6} = 0; 583276479Sdim let Inst{5-0} = funct; 584276479Sdim} 585276479Sdim 586276479Sdimclass SEQ_FM<bits<6> funct> : StdArch { 587276479Sdim bits<5> rd; 588276479Sdim bits<5> rs; 589276479Sdim bits<5> rt; 590276479Sdim 591276479Sdim bits<32> Inst; 592276479Sdim 593276479Sdim let Inst{31-26} = 0x1c; 594276479Sdim let Inst{25-21} = rs; 595276479Sdim let Inst{20-16} = rt; 596276479Sdim let Inst{15-11} = rd; 597276479Sdim let Inst{10-6} = 0; 598276479Sdim let Inst{5-0} = funct; 599276479Sdim} 600276479Sdim 601276479Sdimclass SEQI_FM<bits<6> funct> : StdArch { 602276479Sdim bits<5> rs; 603276479Sdim bits<5> rt; 604276479Sdim bits<10> imm10; 605276479Sdim 606276479Sdim bits<32> Inst; 607276479Sdim 608276479Sdim let Inst{31-26} = 0x1c; 609276479Sdim let Inst{25-21} = rs; 610276479Sdim let Inst{20-16} = rt; 611276479Sdim let Inst{15-6} = imm10; 612276479Sdim let Inst{5-0} = funct; 613276479Sdim} 614276479Sdim 615243830Sdim//===----------------------------------------------------------------------===// 616261991Sdim// System calls format <op|code_|funct> 617261991Sdim//===----------------------------------------------------------------------===// 618261991Sdim 619276479Sdimclass SYS_FM<bits<6> funct> : StdArch 620261991Sdim{ 621261991Sdim bits<20> code_; 622261991Sdim bits<32> Inst; 623261991Sdim let Inst{31-26} = 0x0; 624261991Sdim let Inst{25-6} = code_; 625261991Sdim let Inst{5-0} = funct; 626261991Sdim} 627261991Sdim 628261991Sdim//===----------------------------------------------------------------------===// 629261991Sdim// Break instruction format <op|code_1|funct> 630261991Sdim//===----------------------------------------------------------------------===// 631261991Sdim 632276479Sdimclass BRK_FM<bits<6> funct> : StdArch 633261991Sdim{ 634261991Sdim bits<10> code_1; 635261991Sdim bits<10> code_2; 636261991Sdim bits<32> Inst; 637261991Sdim let Inst{31-26} = 0x0; 638261991Sdim let Inst{25-16} = code_1; 639261991Sdim let Inst{15-6} = code_2; 640261991Sdim let Inst{5-0} = funct; 641261991Sdim} 642261991Sdim 643261991Sdim//===----------------------------------------------------------------------===// 644261991Sdim// Exception return format <Cop0|1|0|funct> 645261991Sdim//===----------------------------------------------------------------------===// 646261991Sdim 647296417Sdimclass ER_FM<bits<6> funct, bit LLBit> : StdArch 648261991Sdim{ 649261991Sdim bits<32> Inst; 650261991Sdim let Inst{31-26} = 0x10; 651261991Sdim let Inst{25} = 1; 652296417Sdim let Inst{24-7} = 0; 653296417Sdim let Inst{6} = LLBit; 654261991Sdim let Inst{5-0} = funct; 655261991Sdim} 656261991Sdim 657261991Sdim//===----------------------------------------------------------------------===// 658261991Sdim// Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0> 659261991Sdim//===----------------------------------------------------------------------===// 660261991Sdim 661276479Sdimclass EI_FM<bits<1> sc> : StdArch 662261991Sdim{ 663261991Sdim bits<32> Inst; 664261991Sdim bits<5> rt; 665261991Sdim let Inst{31-26} = 0x10; 666261991Sdim let Inst{25-21} = 0xb; 667261991Sdim let Inst{20-16} = rt; 668261991Sdim let Inst{15-11} = 0xc; 669261991Sdim let Inst{10-6} = 0; 670261991Sdim let Inst{5} = sc; 671261991Sdim let Inst{4-0} = 0; 672261991Sdim} 673261991Sdim 674261991Sdim//===----------------------------------------------------------------------===// 675193323Sed// 676193323Sed// FLOATING POINT INSTRUCTION FORMATS 677193323Sed// 678193323Sed// opcode - operation code. 679193323Sed// fs - src reg. 680193323Sed// ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 681193323Sed// fd - dst reg, only used on 3 regs instr. 682193323Sed// fmt - double or single precision. 683193323Sed// funct - combined with opcode field give us an operation code. 684193323Sed// 685193323Sed//===----------------------------------------------------------------------===// 686193323Sed 687193323Sed//===----------------------------------------------------------------------===// 688193323Sed// Format FI instruction class in Mips : <|opcode|base|ft|immediate|> 689193323Sed//===----------------------------------------------------------------------===// 690193323Sed 691221345Sdimclass FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>: 692239462Sdim InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI> 693193323Sed{ 694193323Sed bits<5> ft; 695193323Sed bits<5> base; 696193323Sed bits<16> imm16; 697193323Sed 698228379Sdim let Opcode = op; 699193323Sed 700193323Sed let Inst{25-21} = base; 701221345Sdim let Inst{20-16} = ft; 702193323Sed let Inst{15-0} = imm16; 703193323Sed} 704193323Sed 705276479Sdimclass ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch { 706249423Sdim bits<5> fd; 707249423Sdim bits<5> fs; 708249423Sdim bits<5> ft; 709193323Sed 710249423Sdim bits<32> Inst; 711193323Sed 712249423Sdim let Inst{31-26} = 0x11; 713193323Sed let Inst{25-21} = fmt; 714221345Sdim let Inst{20-16} = ft; 715193323Sed let Inst{15-11} = fs; 716249423Sdim let Inst{10-6} = fd; 717249423Sdim let Inst{5-0} = funct; 718193323Sed} 719221345Sdim 720276479Sdimclass ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch { 721249423Sdim bits<5> fd; 722249423Sdim bits<5> fs; 723221345Sdim 724249423Sdim bits<32> Inst; 725221345Sdim 726249423Sdim let Inst{31-26} = 0x11; 727249423Sdim let Inst{25-21} = fmt; 728249423Sdim let Inst{20-16} = 0; 729249423Sdim let Inst{15-11} = fs; 730249423Sdim let Inst{10-6} = fd; 731249423Sdim let Inst{5-0} = funct; 732221345Sdim} 733221345Sdim 734276479Sdimclass MFC1_FM<bits<5> funct> : StdArch { 735249423Sdim bits<5> rt; 736249423Sdim bits<5> fs; 737221345Sdim 738249423Sdim bits<32> Inst; 739221345Sdim 740249423Sdim let Inst{31-26} = 0x11; 741249423Sdim let Inst{25-21} = funct; 742249423Sdim let Inst{20-16} = rt; 743221345Sdim let Inst{15-11} = fs; 744249423Sdim let Inst{10-0} = 0; 745226633Sdim} 746226633Sdim 747251662Sdimclass LW_FM<bits<6> op> : StdArch { 748249423Sdim bits<5> rt; 749249423Sdim bits<21> addr; 750226633Sdim 751249423Sdim bits<32> Inst; 752249423Sdim 753249423Sdim let Inst{31-26} = op; 754249423Sdim let Inst{25-21} = addr{20-16}; 755249423Sdim let Inst{20-16} = rt; 756249423Sdim let Inst{15-0} = addr{15-0}; 757226633Sdim} 758226633Sdim 759276479Sdimclass MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch { 760234353Sdim bits<5> fd; 761234353Sdim bits<5> fr; 762234353Sdim bits<5> fs; 763234353Sdim bits<5> ft; 764234353Sdim 765249423Sdim bits<32> Inst; 766249423Sdim 767249423Sdim let Inst{31-26} = 0x13; 768234353Sdim let Inst{25-21} = fr; 769234353Sdim let Inst{20-16} = ft; 770234353Sdim let Inst{15-11} = fs; 771249423Sdim let Inst{10-6} = fd; 772249423Sdim let Inst{5-3} = funct; 773249423Sdim let Inst{2-0} = fmt; 774234353Sdim} 775234353Sdim 776276479Sdimclass LWXC1_FM<bits<6> funct> : StdArch { 777249423Sdim bits<5> fd; 778249423Sdim bits<5> base; 779249423Sdim bits<5> index; 780234353Sdim 781249423Sdim bits<32> Inst; 782234353Sdim 783249423Sdim let Inst{31-26} = 0x13; 784234353Sdim let Inst{25-21} = base; 785234353Sdim let Inst{20-16} = index; 786249423Sdim let Inst{15-11} = 0; 787249423Sdim let Inst{10-6} = fd; 788249423Sdim let Inst{5-0} = funct; 789249423Sdim} 790249423Sdim 791276479Sdimclass SWXC1_FM<bits<6> funct> : StdArch { 792249423Sdim bits<5> fs; 793249423Sdim bits<5> base; 794249423Sdim bits<5> index; 795249423Sdim 796249423Sdim bits<32> Inst; 797249423Sdim 798249423Sdim let Inst{31-26} = 0x13; 799249423Sdim let Inst{25-21} = base; 800249423Sdim let Inst{20-16} = index; 801234353Sdim let Inst{15-11} = fs; 802249423Sdim let Inst{10-6} = 0; 803249423Sdim let Inst{5-0} = funct; 804249423Sdim} 805249423Sdim 806276479Sdimclass BC1F_FM<bit nd, bit tf> : StdArch { 807261991Sdim bits<3> fcc; 808249423Sdim bits<16> offset; 809249423Sdim 810249423Sdim bits<32> Inst; 811249423Sdim 812249423Sdim let Inst{31-26} = 0x11; 813249423Sdim let Inst{25-21} = 0x8; 814261991Sdim let Inst{20-18} = fcc; 815249423Sdim let Inst{17} = nd; 816249423Sdim let Inst{16} = tf; 817249423Sdim let Inst{15-0} = offset; 818249423Sdim} 819249423Sdim 820276479Sdimclass CEQS_FM<bits<5> fmt> : StdArch { 821249423Sdim bits<5> fs; 822249423Sdim bits<5> ft; 823249423Sdim bits<4> cond; 824249423Sdim 825249423Sdim bits<32> Inst; 826249423Sdim 827249423Sdim let Inst{31-26} = 0x11; 828249423Sdim let Inst{25-21} = fmt; 829249423Sdim let Inst{20-16} = ft; 830249423Sdim let Inst{15-11} = fs; 831249423Sdim let Inst{10-8} = 0; // cc 832249423Sdim let Inst{7-4} = 0x3; 833249423Sdim let Inst{3-0} = cond; 834249423Sdim} 835249423Sdim 836261991Sdimclass C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> { 837261991Sdim let cond = c; 838261991Sdim} 839261991Sdim 840276479Sdimclass CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch { 841249423Sdim bits<5> fd; 842249423Sdim bits<5> fs; 843249423Sdim bits<5> rt; 844249423Sdim 845249423Sdim bits<32> Inst; 846249423Sdim 847249423Sdim let Inst{31-26} = 0x11; 848249423Sdim let Inst{25-21} = fmt; 849249423Sdim let Inst{20-16} = rt; 850249423Sdim let Inst{15-11} = fs; 851234353Sdim let Inst{10-6} = fd; 852234353Sdim let Inst{5-0} = funct; 853234353Sdim} 854249423Sdim 855261991Sdimclass CMov_F_I_FM<bit tf> : StdArch { 856249423Sdim bits<5> rd; 857249423Sdim bits<5> rs; 858261991Sdim bits<3> fcc; 859249423Sdim 860249423Sdim bits<32> Inst; 861249423Sdim 862249423Sdim let Inst{31-26} = 0; 863249423Sdim let Inst{25-21} = rs; 864261991Sdim let Inst{20-18} = fcc; 865249423Sdim let Inst{17} = 0; 866249423Sdim let Inst{16} = tf; 867249423Sdim let Inst{15-11} = rd; 868249423Sdim let Inst{10-6} = 0; 869249423Sdim let Inst{5-0} = 1; 870249423Sdim} 871249423Sdim 872276479Sdimclass CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch { 873249423Sdim bits<5> fd; 874249423Sdim bits<5> fs; 875261991Sdim bits<3> fcc; 876249423Sdim 877249423Sdim bits<32> Inst; 878249423Sdim 879249423Sdim let Inst{31-26} = 0x11; 880249423Sdim let Inst{25-21} = fmt; 881261991Sdim let Inst{20-18} = fcc; 882249423Sdim let Inst{17} = 0; 883249423Sdim let Inst{16} = tf; 884249423Sdim let Inst{15-11} = fs; 885249423Sdim let Inst{10-6} = fd; 886249423Sdim let Inst{5-0} = 0x11; 887249423Sdim} 888276479Sdim 889276479Sdimclass BARRIER_FM<bits<5> op> : StdArch { 890276479Sdim bits<32> Inst; 891276479Sdim 892276479Sdim let Inst{31-26} = 0; // SPECIAL 893276479Sdim let Inst{25-21} = 0; 894276479Sdim let Inst{20-16} = 0; // rt = 0 895276479Sdim let Inst{15-11} = 0; // rd = 0 896276479Sdim let Inst{10-6} = op; // Operation 897276479Sdim let Inst{5-0} = 0; // SLL 898276479Sdim} 899276479Sdim 900276479Sdimclass SDBBP_FM : StdArch { 901276479Sdim bits<20> code_; 902276479Sdim 903276479Sdim bits<32> Inst; 904276479Sdim 905276479Sdim let Inst{31-26} = 0b011100; // SPECIAL2 906276479Sdim let Inst{25-6} = code_; 907276479Sdim let Inst{5-0} = 0b111111; // SDBBP 908276479Sdim} 909276479Sdim 910276479Sdimclass JR_HB_FM<bits<6> op> : StdArch{ 911276479Sdim bits<5> rs; 912276479Sdim 913276479Sdim bits<32> Inst; 914276479Sdim 915276479Sdim let Inst{31-26} = 0; // SPECIAL 916276479Sdim let Inst{25-21} = rs; 917276479Sdim let Inst{20-11} = 0; 918276479Sdim let Inst{10} = 1; 919276479Sdim let Inst{9-6} = 0; 920276479Sdim let Inst{5-0} = op; 921276479Sdim} 922276479Sdim 923276479Sdimclass JALR_HB_FM<bits<6> op> : StdArch { 924276479Sdim bits<5> rd; 925276479Sdim bits<5> rs; 926276479Sdim 927276479Sdim bits<32> Inst; 928276479Sdim 929276479Sdim let Inst{31-26} = 0; // SPECIAL 930276479Sdim let Inst{25-21} = rs; 931276479Sdim let Inst{20-16} = 0; 932276479Sdim let Inst{15-11} = rd; 933276479Sdim let Inst{10} = 1; 934276479Sdim let Inst{9-6} = 0; 935276479Sdim let Inst{5-0} = op; 936276479Sdim} 937276479Sdim 938276479Sdimclass COP0_TLB_FM<bits<6> op> : StdArch { 939276479Sdim bits<32> Inst; 940276479Sdim 941276479Sdim let Inst{31-26} = 0x10; // COP0 942276479Sdim let Inst{25} = 1; // CO 943276479Sdim let Inst{24-6} = 0; 944276479Sdim let Inst{5-0} = op; // Operation 945276479Sdim} 946276479Sdim 947276479Sdimclass CACHEOP_FM<bits<6> op> : StdArch { 948276479Sdim bits<21> addr; 949276479Sdim bits<5> hint; 950276479Sdim bits<5> base = addr{20-16}; 951276479Sdim bits<16> offset = addr{15-0}; 952276479Sdim 953276479Sdim bits<32> Inst; 954276479Sdim 955276479Sdim let Inst{31-26} = op; 956276479Sdim let Inst{25-21} = base; 957276479Sdim let Inst{20-16} = hint; 958276479Sdim let Inst{15-0} = offset; 959276479Sdim} 960