1243789Sdim//===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===// 2243789Sdim// 3243789Sdim// The LLVM Compiler Infrastructure 4243789Sdim// 5243789Sdim// This file is distributed under the University of Illinois Open Source 6243789Sdim// License. See LICENSE.TXT for details. 7243789Sdim// 8243789Sdim//===----------------------------------------------------------------------===// 9243789Sdim 10296417Sdimclass DspMMRel; 11296417Sdim 12296417Sdimdef Dsp2MicroMips : InstrMapping { 13296417Sdim let FilterClass = "DspMMRel"; 14296417Sdim // Instructions with the same BaseOpcode and isNVStore values form a row. 15296417Sdim let RowFields = ["BaseOpcode"]; 16296417Sdim // Instructions with the same predicate sense form a column. 17296417Sdim let ColFields = ["Arch"]; 18296417Sdim // The key column is the unpredicated instructions. 19296417Sdim let KeyCol = ["dsp"]; 20296417Sdim // Value columns are PredSense=true and PredSense=false 21296417Sdim let ValueCols = [["dsp"], ["mmdsp"]]; 22296417Sdim} 23296417Sdim 24276479Sdimdef HasDSP : Predicate<"Subtarget->hasDSP()">, 25243789Sdim AssemblerPredicate<"FeatureDSP">; 26276479Sdimdef HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">, 27243789Sdim AssemblerPredicate<"FeatureDSPR2">; 28296417Sdimdef HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">, 29296417Sdim AssemblerPredicate<"FeatureDSPR3">; 30243789Sdim 31296417Sdimclass ISA_DSPR2 { 32296417Sdim list<Predicate> InsnPredicates = [HasDSPR2]; 33296417Sdim} 34296417Sdim 35243789Sdim// Fields. 36243789Sdimclass Field6<bits<6> val> { 37243789Sdim bits<6> V = val; 38243789Sdim} 39243789Sdim 40243789Sdimdef SPECIAL3_OPCODE : Field6<0b011111>; 41243789Sdimdef REGIMM_OPCODE : Field6<0b000001>; 42243789Sdim 43296417Sdimclass DSPInst<string opstr = ""> 44296417Sdim : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl { 45296417Sdim let InsnPredicates = [HasDSP]; 46296417Sdim string BaseOpcode = opstr; 47296417Sdim string Arch = "dsp"; 48243789Sdim} 49243789Sdim 50249423Sdimclass PseudoDSP<dag outs, dag ins, list<dag> pattern, 51296417Sdim InstrItinClass itin = IIPseudo> 52296417Sdim : MipsPseudo<outs, ins, pattern, itin>, PredicateControl { 53296417Sdim let InsnPredicates = [HasDSP]; 54243789Sdim} 55243789Sdim 56296417Sdimclass DSPInstAlias<string Asm, dag Result, bit Emit = 0b1> 57296417Sdim : InstAlias<Asm, Result, Emit>, PredicateControl { 58296417Sdim let InsnPredicates = [HasDSP]; 59296417Sdim} 60296417Sdim 61243789Sdim// ADDU.QB sub-class format. 62243789Sdimclass ADDU_QB_FMT<bits<5> op> : DSPInst { 63243789Sdim bits<5> rd; 64243789Sdim bits<5> rs; 65243789Sdim bits<5> rt; 66243789Sdim 67243789Sdim let Opcode = SPECIAL3_OPCODE.V; 68243789Sdim 69243789Sdim let Inst{25-21} = rs; 70243789Sdim let Inst{20-16} = rt; 71243789Sdim let Inst{15-11} = rd; 72243789Sdim let Inst{10-6} = op; 73243789Sdim let Inst{5-0} = 0b010000; 74243789Sdim} 75243789Sdim 76243789Sdimclass RADDU_W_QB_FMT<bits<5> op> : DSPInst { 77243789Sdim bits<5> rd; 78243789Sdim bits<5> rs; 79243789Sdim 80243789Sdim let Opcode = SPECIAL3_OPCODE.V; 81243789Sdim 82243789Sdim let Inst{25-21} = rs; 83243789Sdim let Inst{20-16} = 0; 84243789Sdim let Inst{15-11} = rd; 85243789Sdim let Inst{10-6} = op; 86243789Sdim let Inst{5-0} = 0b010000; 87243789Sdim} 88243789Sdim 89243789Sdim// CMPU.EQ.QB sub-class format. 90243789Sdimclass CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst { 91243789Sdim bits<5> rs; 92243789Sdim bits<5> rt; 93243789Sdim 94243789Sdim let Opcode = SPECIAL3_OPCODE.V; 95243789Sdim 96243789Sdim let Inst{25-21} = rs; 97243789Sdim let Inst{20-16} = rt; 98243789Sdim let Inst{15-11} = 0; 99243789Sdim let Inst{10-6} = op; 100243789Sdim let Inst{5-0} = 0b010001; 101243789Sdim} 102243789Sdim 103243789Sdimclass CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst { 104243789Sdim bits<5> rs; 105243789Sdim bits<5> rt; 106243789Sdim bits<5> rd; 107243789Sdim 108243789Sdim let Opcode = SPECIAL3_OPCODE.V; 109243789Sdim 110243789Sdim let Inst{25-21} = rs; 111243789Sdim let Inst{20-16} = rt; 112243789Sdim let Inst{15-11} = rd; 113243789Sdim let Inst{10-6} = op; 114243789Sdim let Inst{5-0} = 0b010001; 115243789Sdim} 116243789Sdim 117243789Sdimclass PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst { 118243789Sdim bits<5> rs; 119243789Sdim bits<5> rt; 120243789Sdim bits<5> sa; 121243789Sdim 122243789Sdim let Opcode = SPECIAL3_OPCODE.V; 123243789Sdim 124243789Sdim let Inst{25-21} = rs; 125243789Sdim let Inst{20-16} = rt; 126243789Sdim let Inst{15-11} = sa; 127243789Sdim let Inst{10-6} = op; 128243789Sdim let Inst{5-0} = 0b010001; 129243789Sdim} 130243789Sdim 131243789Sdim// ABSQ_S.PH sub-class format. 132243789Sdimclass ABSQ_S_PH_R2_FMT<bits<5> op> : DSPInst { 133243789Sdim bits<5> rd; 134243789Sdim bits<5> rt; 135243789Sdim 136243789Sdim let Opcode = SPECIAL3_OPCODE.V; 137243789Sdim 138243789Sdim let Inst{25-21} = 0; 139243789Sdim let Inst{20-16} = rt; 140243789Sdim let Inst{15-11} = rd; 141243789Sdim let Inst{10-6} = op; 142243789Sdim let Inst{5-0} = 0b010010; 143243789Sdim} 144243789Sdim 145243789Sdim 146243789Sdimclass REPL_FMT<bits<5> op> : DSPInst { 147243789Sdim bits<5> rd; 148243789Sdim bits<10> imm; 149243789Sdim 150243789Sdim let Opcode = SPECIAL3_OPCODE.V; 151243789Sdim 152243789Sdim let Inst{25-16} = imm; 153243789Sdim let Inst{15-11} = rd; 154243789Sdim let Inst{10-6} = op; 155243789Sdim let Inst{5-0} = 0b010010; 156243789Sdim} 157243789Sdim 158243789Sdim// SHLL.QB sub-class format. 159243789Sdimclass SHLL_QB_FMT<bits<5> op> : DSPInst { 160243789Sdim bits<5> rd; 161243789Sdim bits<5> rt; 162243789Sdim bits<5> rs_sa; 163243789Sdim 164243789Sdim let Opcode = SPECIAL3_OPCODE.V; 165243789Sdim 166243789Sdim let Inst{25-21} = rs_sa; 167243789Sdim let Inst{20-16} = rt; 168243789Sdim let Inst{15-11} = rd; 169243789Sdim let Inst{10-6} = op; 170243789Sdim let Inst{5-0} = 0b010011; 171243789Sdim} 172243789Sdim 173243789Sdim// LX sub-class format. 174243789Sdimclass LX_FMT<bits<5> op> : DSPInst { 175243789Sdim bits<5> rd; 176243789Sdim bits<5> base; 177243789Sdim bits<5> index; 178243789Sdim 179243789Sdim let Opcode = SPECIAL3_OPCODE.V; 180243789Sdim 181243789Sdim let Inst{25-21} = base; 182243789Sdim let Inst{20-16} = index; 183243789Sdim let Inst{15-11} = rd; 184243789Sdim let Inst{10-6} = op; 185243789Sdim let Inst{5-0} = 0b001010; 186243789Sdim} 187243789Sdim 188243789Sdim// ADDUH.QB sub-class format. 189243789Sdimclass ADDUH_QB_FMT<bits<5> op> : DSPInst { 190243789Sdim bits<5> rd; 191243789Sdim bits<5> rs; 192243789Sdim bits<5> rt; 193243789Sdim 194243789Sdim let Opcode = SPECIAL3_OPCODE.V; 195243789Sdim 196243789Sdim let Inst{25-21} = rs; 197243789Sdim let Inst{20-16} = rt; 198243789Sdim let Inst{15-11} = rd; 199243789Sdim let Inst{10-6} = op; 200243789Sdim let Inst{5-0} = 0b011000; 201243789Sdim} 202243789Sdim 203243789Sdim// APPEND sub-class format. 204243789Sdimclass APPEND_FMT<bits<5> op> : DSPInst { 205243789Sdim bits<5> rt; 206243789Sdim bits<5> rs; 207243789Sdim bits<5> sa; 208243789Sdim 209243789Sdim let Opcode = SPECIAL3_OPCODE.V; 210243789Sdim 211243789Sdim let Inst{25-21} = rs; 212243789Sdim let Inst{20-16} = rt; 213243789Sdim let Inst{15-11} = sa; 214243789Sdim let Inst{10-6} = op; 215243789Sdim let Inst{5-0} = 0b110001; 216243789Sdim} 217243789Sdim 218243789Sdim// DPA.W.PH sub-class format. 219243789Sdimclass DPA_W_PH_FMT<bits<5> op> : DSPInst { 220243789Sdim bits<2> ac; 221243789Sdim bits<5> rs; 222243789Sdim bits<5> rt; 223243789Sdim 224243789Sdim let Opcode = SPECIAL3_OPCODE.V; 225243789Sdim 226243789Sdim let Inst{25-21} = rs; 227243789Sdim let Inst{20-16} = rt; 228243789Sdim let Inst{15-13} = 0; 229243789Sdim let Inst{12-11} = ac; 230243789Sdim let Inst{10-6} = op; 231243789Sdim let Inst{5-0} = 0b110000; 232243789Sdim} 233243789Sdim 234243789Sdim// MULT sub-class format. 235243789Sdimclass MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst { 236243789Sdim bits<2> ac; 237243789Sdim bits<5> rs; 238243789Sdim bits<5> rt; 239243789Sdim 240243789Sdim let Opcode = opcode; 241243789Sdim 242243789Sdim let Inst{25-21} = rs; 243243789Sdim let Inst{20-16} = rt; 244243789Sdim let Inst{15-13} = 0; 245243789Sdim let Inst{12-11} = ac; 246243789Sdim let Inst{10-6} = 0; 247243789Sdim let Inst{5-0} = funct; 248243789Sdim} 249243789Sdim 250251662Sdim// MFHI sub-class format. 251251662Sdimclass MFHI_FMT<bits<6> funct> : DSPInst { 252251662Sdim bits<5> rd; 253251662Sdim bits<2> ac; 254251662Sdim 255251662Sdim let Inst{31-26} = 0; 256251662Sdim let Inst{25-23} = 0; 257251662Sdim let Inst{22-21} = ac; 258251662Sdim let Inst{20-16} = 0; 259251662Sdim let Inst{15-11} = rd; 260251662Sdim let Inst{10-6} = 0; 261251662Sdim let Inst{5-0} = funct; 262251662Sdim} 263251662Sdim 264251662Sdim// MTHI sub-class format. 265251662Sdimclass MTHI_FMT<bits<6> funct> : DSPInst { 266251662Sdim bits<5> rs; 267251662Sdim bits<2> ac; 268251662Sdim 269251662Sdim let Inst{31-26} = 0; 270251662Sdim let Inst{25-21} = rs; 271251662Sdim let Inst{20-13} = 0; 272251662Sdim let Inst{12-11} = ac; 273251662Sdim let Inst{10-6} = 0; 274251662Sdim let Inst{5-0} = funct; 275251662Sdim} 276251662Sdim 277243789Sdim// EXTR.W sub-class format (type 1). 278243789Sdimclass EXTR_W_TY1_FMT<bits<5> op> : DSPInst { 279243789Sdim bits<5> rt; 280243789Sdim bits<2> ac; 281243789Sdim bits<5> shift_rs; 282243789Sdim 283243789Sdim let Opcode = SPECIAL3_OPCODE.V; 284243789Sdim 285243789Sdim let Inst{25-21} = shift_rs; 286243789Sdim let Inst{20-16} = rt; 287243789Sdim let Inst{15-13} = 0; 288243789Sdim let Inst{12-11} = ac; 289243789Sdim let Inst{10-6} = op; 290243789Sdim let Inst{5-0} = 0b111000; 291243789Sdim} 292243789Sdim 293243789Sdim// SHILO sub-class format. 294243789Sdimclass SHILO_R1_FMT<bits<5> op> : DSPInst { 295243789Sdim bits<2> ac; 296243789Sdim bits<6> shift; 297243789Sdim 298243789Sdim let Opcode = SPECIAL3_OPCODE.V; 299243789Sdim 300243789Sdim let Inst{25-20} = shift; 301243789Sdim let Inst{19-13} = 0; 302243789Sdim let Inst{12-11} = ac; 303243789Sdim let Inst{10-6} = op; 304243789Sdim let Inst{5-0} = 0b111000; 305243789Sdim} 306243789Sdim 307243789Sdimclass SHILO_R2_FMT<bits<5> op> : DSPInst { 308243789Sdim bits<2> ac; 309243789Sdim bits<5> rs; 310243789Sdim 311243789Sdim let Opcode = SPECIAL3_OPCODE.V; 312243789Sdim 313243789Sdim let Inst{25-21} = rs; 314243789Sdim let Inst{20-13} = 0; 315243789Sdim let Inst{12-11} = ac; 316243789Sdim let Inst{10-6} = op; 317243789Sdim let Inst{5-0} = 0b111000; 318243789Sdim} 319243789Sdim 320243789Sdimclass RDDSP_FMT<bits<5> op> : DSPInst { 321243789Sdim bits<5> rd; 322243789Sdim bits<10> mask; 323243789Sdim 324243789Sdim let Opcode = SPECIAL3_OPCODE.V; 325243789Sdim 326243789Sdim let Inst{25-16} = mask; 327243789Sdim let Inst{15-11} = rd; 328243789Sdim let Inst{10-6} = op; 329243789Sdim let Inst{5-0} = 0b111000; 330243789Sdim} 331243789Sdim 332243789Sdimclass WRDSP_FMT<bits<5> op> : DSPInst { 333243789Sdim bits<5> rs; 334243789Sdim bits<10> mask; 335243789Sdim 336243789Sdim let Opcode = SPECIAL3_OPCODE.V; 337243789Sdim 338243789Sdim let Inst{25-21} = rs; 339243789Sdim let Inst{20-11} = mask; 340243789Sdim let Inst{10-6} = op; 341243789Sdim let Inst{5-0} = 0b111000; 342243789Sdim} 343243789Sdim 344243789Sdimclass BPOSGE32_FMT<bits<5> op> : DSPInst { 345243789Sdim bits<16> offset; 346243789Sdim 347243789Sdim let Opcode = REGIMM_OPCODE.V; 348243789Sdim 349243789Sdim let Inst{25-21} = 0; 350243789Sdim let Inst{20-16} = op; 351243789Sdim let Inst{15-0} = offset; 352243789Sdim} 353243789Sdim 354243789Sdim// INSV sub-class format. 355243789Sdimclass INSV_FMT<bits<6> op> : DSPInst { 356243789Sdim bits<5> rt; 357243789Sdim bits<5> rs; 358243789Sdim 359243789Sdim let Opcode = SPECIAL3_OPCODE.V; 360243789Sdim 361243789Sdim let Inst{25-21} = rs; 362243789Sdim let Inst{20-16} = rt; 363243789Sdim let Inst{15-6} = 0; 364243789Sdim let Inst{5-0} = op; 365243789Sdim} 366