11541Srgrimes//=- Mips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==// 21541Srgrimes// 31541Srgrimes// The LLVM Compiler Infrastructure 41541Srgrimes// 51541Srgrimes// This file is distributed under the University of Illinois Open Source 61541Srgrimes// License. See LICENSE.TXT for details. 71541Srgrimes// 81541Srgrimes//===----------------------------------------------------------------------===// 91541Srgrimes// 101541Srgrimes// This file describes Mips32r6 instruction formats. 111541Srgrimes// 121541Srgrimes//===----------------------------------------------------------------------===// 131541Srgrimes 141541Srgrimesclass R6MMR6Rel; 151541Srgrimes 161541Srgrimesdef MipsR62MicroMipsR6 : InstrMapping { 171541Srgrimes let FilterClass = "R6MMR6Rel"; 181541Srgrimes // Instructions with the same BaseOpcode and isNVStore values form a row. 191541Srgrimes let RowFields = ["BaseOpcode"]; 201541Srgrimes // Instructions with the same predicate sense form a column. 211541Srgrimes let ColFields = ["Arch"]; 221541Srgrimes // The key column is the unpredicated instructions. 231541Srgrimes let KeyCol = ["mipsr6"]; 241541Srgrimes // Value columns are PredSense=true and PredSense=false 251541Srgrimes let ValueCols = [["mipsr6"], ["micromipsr6"]]; 261541Srgrimes} 271541Srgrimes 281541Srgrimesclass MipsR6Arch<string opstr> { 291541Srgrimes string Arch = "mipsr6"; 301541Srgrimes string BaseOpcode = opstr; 311541Srgrimes} 321541Srgrimes 331541Srgrimesclass MipsR6Inst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, 341941Sdg PredicateControl { 351541Srgrimes let DecoderNamespace = "Mips32r6_64r6"; 361541Srgrimes let EncodingPredicates = [HasStdEnc]; 371541Srgrimes} 381541Srgrimes 391541Srgrimes//===----------------------------------------------------------------------===// 401541Srgrimes// 411541Srgrimes// Field Values 421541Srgrimes// 431541Srgrimes//===----------------------------------------------------------------------===// 441541Srgrimes 451541Srgrimesclass OPGROUP<bits<6> Val> { 461541Srgrimes bits<6> Value = Val; 471541Srgrimes} 481541Srgrimesdef OPGROUP_COP1 : OPGROUP<0b010001>; 491541Srgrimesdef OPGROUP_COP2 : OPGROUP<0b010010>; 501541Srgrimesdef OPGROUP_ADDI : OPGROUP<0b001000>; 511541Srgrimesdef OPGROUP_AUI : OPGROUP<0b001111>; 521541Srgrimesdef OPGROUP_BLEZ : OPGROUP<0b000110>; 531541Srgrimesdef OPGROUP_BGTZ : OPGROUP<0b000111>; 541541Srgrimesdef OPGROUP_BLEZL : OPGROUP<0b010110>; 551541Srgrimesdef OPGROUP_BGTZL : OPGROUP<0b010111>; 561541Srgrimesdef OPGROUP_DADDI : OPGROUP<0b011000>; 571541Srgrimesdef OPGROUP_DAUI : OPGROUP<0b011101>; 581541Srgrimesdef OPGROUP_PCREL : OPGROUP<0b111011>; 591541Srgrimesdef OPGROUP_REGIMM : OPGROUP<0b000001>; 601541Srgrimesdef OPGROUP_SPECIAL : OPGROUP<0b000000>; 611541Srgrimes// The spec occasionally names this value LL, LLD, SC, or SCD. 621541Srgrimesdef OPGROUP_SPECIAL3 : OPGROUP<0b011111>; 631541Srgrimes// The spec names this constant LWC2, LDC2, SWC2, and SDC2 in different places. 641541Srgrimesdef OPGROUP_COP2LDST : OPGROUP<0b010010>; 651541Srgrimes 661541Srgrimesclass OPCODE2<bits<2> Val> { 671541Srgrimes bits<2> Value = Val; 681541Srgrimes} 691541Srgrimesdef OPCODE2_ADDIUPC : OPCODE2<0b00>; 701541Srgrimesdef OPCODE2_LWPC : OPCODE2<0b01>; 711541Srgrimesdef OPCODE2_LWUPC : OPCODE2<0b10>; 721541Srgrimes 731541Srgrimesclass OPCODE3<bits<3> Val> { 741541Srgrimes bits<3> Value = Val; 751541Srgrimes} 761541Srgrimesdef OPCODE3_LDPC : OPCODE3<0b110>; 771541Srgrimes 781541Srgrimesclass OPCODE5<bits<5> Val> { 791541Srgrimes bits<5> Value = Val; 801541Srgrimes} 811541Srgrimesdef OPCODE5_ALUIPC : OPCODE5<0b11111>; 821541Srgrimesdef OPCODE5_AUIPC : OPCODE5<0b11110>; 831541Srgrimesdef OPCODE5_DAHI : OPCODE5<0b00110>; 841541Srgrimesdef OPCODE5_DATI : OPCODE5<0b11110>; 851541Srgrimesdef OPCODE5_BC1EQZ : OPCODE5<0b01001>; 861541Srgrimesdef OPCODE5_BC1NEZ : OPCODE5<0b01101>; 871541Srgrimesdef OPCODE5_BC2EQZ : OPCODE5<0b01001>; 881541Srgrimesdef OPCODE5_BC2NEZ : OPCODE5<0b01101>; 891541Srgrimesdef OPCODE5_BGEZAL : OPCODE5<0b10001>; 901541Srgrimes// The next four constants are unnamed in the spec. These names are taken from 911541Srgrimes// the OPGROUP names they are used with. 921541Srgrimesdef OPCODE5_LDC2 : OPCODE5<0b01110>; 931541Srgrimesdef OPCODE5_LWC2 : OPCODE5<0b01010>; 941541Srgrimesdef OPCODE5_SDC2 : OPCODE5<0b01111>; 951541Srgrimesdef OPCODE5_SWC2 : OPCODE5<0b01011>; 961541Srgrimes 971541Srgrimesclass OPCODE6<bits<6> Val> { 981541Srgrimes bits<6> Value = Val; 991541Srgrimes} 1001541Srgrimesdef OPCODE6_ALIGN : OPCODE6<0b100000>; 1011541Srgrimesdef OPCODE6_DALIGN : OPCODE6<0b100100>; 1021541Srgrimesdef OPCODE6_BITSWAP : OPCODE6<0b100000>; 1031541Srgrimesdef OPCODE6_DBITSWAP : OPCODE6<0b100100>; 1041541Srgrimesdef OPCODE6_JALR : OPCODE6<0b001001>; 1051541Srgrimesdef OPCODE6_CACHE : OPCODE6<0b100101>; 1061541Srgrimesdef OPCODE6_PREF : OPCODE6<0b110101>; 1071541Srgrimes// The next four constants are unnamed in the spec. These names are taken from 1081541Srgrimes// the OPGROUP names they are used with. 1091541Srgrimesdef OPCODE6_LL : OPCODE6<0b110110>; 1101541Srgrimesdef OPCODE6_LLD : OPCODE6<0b110111>; 1111541Srgrimesdef OPCODE6_SC : OPCODE6<0b100110>; 1121541Srgrimesdef OPCODE6_SCD : OPCODE6<0b100111>; 1131541Srgrimesdef OPCODE6_CLO : OPCODE6<0b010001>; 1141541Srgrimesdef OPCODE6_CLZ : OPCODE6<0b010000>; 1151541Srgrimesdef OPCODE6_DCLO : OPCODE6<0b010011>; 1161541Srgrimesdef OPCODE6_DCLZ : OPCODE6<0b010010>; 1171541Srgrimesdef OPCODE6_LSA : OPCODE6<0b000101>; 1181549Srgrimesdef OPCODE6_DLSA : OPCODE6<0b010101>; 1191541Srgrimesdef OPCODE6_SDBBP : OPCODE6<0b001110>; 1201541Srgrimes 1211541Srgrimesclass FIELD_FMT<bits<5> Val> { 1221541Srgrimes bits<5> Value = Val; 1231549Srgrimes} 1241541Srgrimesdef FIELD_FMT_S : FIELD_FMT<0b10000>; 1251541Srgrimesdef FIELD_FMT_D : FIELD_FMT<0b10001>; 1261541Srgrimes 1271541Srgrimesclass FIELD_CMP_COND<bits<5> Val> { 1281541Srgrimes bits<5> Value = Val; 1291549Srgrimes} 1301541Srgrimes// Note: The CMP_COND_FMT names differ from the C_COND_FMT names. 1311549Srgrimesdef FIELD_CMP_COND_AF : FIELD_CMP_COND<0b00000>; 1321541Srgrimesdef FIELD_CMP_COND_UN : FIELD_CMP_COND<0b00001>; 1331541Srgrimesdef FIELD_CMP_COND_EQ : FIELD_CMP_COND<0b00010>; 1341541Srgrimesdef FIELD_CMP_COND_UEQ : FIELD_CMP_COND<0b00011>; 1351541Srgrimesdef FIELD_CMP_COND_LT : FIELD_CMP_COND<0b00100>; 1361541Srgrimesdef FIELD_CMP_COND_ULT : FIELD_CMP_COND<0b00101>; 1371541Srgrimesdef FIELD_CMP_COND_LE : FIELD_CMP_COND<0b00110>; 1381541Srgrimesdef FIELD_CMP_COND_ULE : FIELD_CMP_COND<0b00111>; 1391541Srgrimesdef FIELD_CMP_COND_SAF : FIELD_CMP_COND<0b01000>; 1401541Srgrimesdef FIELD_CMP_COND_SUN : FIELD_CMP_COND<0b01001>; 1411541Srgrimesdef FIELD_CMP_COND_SEQ : FIELD_CMP_COND<0b01010>; 1421541Srgrimesdef FIELD_CMP_COND_SUEQ : FIELD_CMP_COND<0b01011>; 1431541Srgrimesdef FIELD_CMP_COND_SLT : FIELD_CMP_COND<0b01100>; 1441541Srgrimesdef FIELD_CMP_COND_SULT : FIELD_CMP_COND<0b01101>; 1451541Srgrimesdef FIELD_CMP_COND_SLE : FIELD_CMP_COND<0b01110>; 1461541Srgrimesdef FIELD_CMP_COND_SULE : FIELD_CMP_COND<0b01111>; 1471541Srgrimes 1481541Srgrimesclass FIELD_CMP_FORMAT<bits<5> Val> { 1491541Srgrimes bits<5> Value = Val; 1501541Srgrimes} 1511541Srgrimesdef FIELD_CMP_FORMAT_S : FIELD_CMP_FORMAT<0b10100>; 1521541Srgrimesdef FIELD_CMP_FORMAT_D : FIELD_CMP_FORMAT<0b10101>; 1531541Srgrimes 1541541Srgrimes//===----------------------------------------------------------------------===// 1551541Srgrimes// 1561541Srgrimes// Disambiguators 1571541Srgrimes// 1581541Srgrimes//===----------------------------------------------------------------------===// 1591541Srgrimes// 1601541Srgrimes// Some encodings are ambiguous except by comparing field values. 1611541Srgrimes 1621541Srgrimesclass DecodeDisambiguates<string Name> { 1631541Srgrimes string DecoderMethod = !strconcat("Decode", Name); 1641541Srgrimes} 1651541Srgrimes 1661541Srgrimesclass DecodeDisambiguatedBy<string Name> : DecodeDisambiguates<Name> { 1671541Srgrimes string DecoderNamespace = "Mips32r6_64r6_Ambiguous"; 1681541Srgrimes} 1691541Srgrimes 1701541Srgrimes//===----------------------------------------------------------------------===// 1711541Srgrimes// 1721541Srgrimes// Encoding Formats 1731541Srgrimes// 1741541Srgrimes//===----------------------------------------------------------------------===// 1751541Srgrimes 1761541Srgrimesclass AUI_FM : MipsR6Inst { 1771541Srgrimes bits<5> rs; 1781541Srgrimes bits<5> rt; 1791541Srgrimes bits<16> imm; 1801541Srgrimes 1811541Srgrimes bits<32> Inst; 1821541Srgrimes 1831541Srgrimes let Inst{31-26} = OPGROUP_AUI.Value; 1841541Srgrimes let Inst{25-21} = rs; 1851541Srgrimes let Inst{20-16} = rt; 1861541Srgrimes let Inst{15-0} = imm; 1871541Srgrimes} 1881541Srgrimes 1891541Srgrimesclass DAUI_FM : AUI_FM { 1901541Srgrimes let Inst{31-26} = OPGROUP_DAUI.Value; 1911541Srgrimes} 1921541Srgrimes 1931541Srgrimesclass BAL_FM : MipsR6Inst { 1941541Srgrimes bits<16> offset; 1951541Srgrimes 1961541Srgrimes bits<32> Inst; 1971541Srgrimes 1981541Srgrimes let Inst{31-26} = OPGROUP_REGIMM.Value; 1991541Srgrimes let Inst{25-21} = 0b00000; 2001541Srgrimes let Inst{20-16} = OPCODE5_BGEZAL.Value; 2011541Srgrimes let Inst{15-0} = offset; 2021541Srgrimes} 2031541Srgrimes 2041541Srgrimesclass COP1_2R_FM<bits<6> funct, FIELD_FMT Format> : MipsR6Inst { 2051541Srgrimes bits<5> fs; 2061541Srgrimes bits<5> fd; 2071541Srgrimes 2081541Srgrimes bits<32> Inst; 2091541Srgrimes 2101541Srgrimes let Inst{31-26} = OPGROUP_COP1.Value; 2111541Srgrimes let Inst{25-21} = Format.Value; 2121541Srgrimes let Inst{20-16} = 0b00000; 2131541Srgrimes let Inst{15-11} = fs; 2141541Srgrimes let Inst{10-6} = fd; 2151541Srgrimes let Inst{5-0} = funct; 2161541Srgrimes} 2171541Srgrimes 2181541Srgrimesclass COP1_3R_FM<bits<6> funct, FIELD_FMT Format> : MipsR6Inst { 2191541Srgrimes bits<5> ft; 2201541Srgrimes bits<5> fs; 2211541Srgrimes bits<5> fd; 2221541Srgrimes 2231541Srgrimes bits<32> Inst; 2241541Srgrimes 2251541Srgrimes let Inst{31-26} = OPGROUP_COP1.Value; 2261541Srgrimes let Inst{25-21} = Format.Value; 2271541Srgrimes let Inst{20-16} = ft; 2281541Srgrimes let Inst{15-11} = fs; 2291541Srgrimes let Inst{10-6} = fd; 2301541Srgrimes let Inst{5-0} = funct; 2311541Srgrimes} 2321541Srgrimes 2331541Srgrimesclass COP1_BCCZ_FM<OPCODE5 Operation> : MipsR6Inst { 2341541Srgrimes bits<5> ft; 2351541Srgrimes bits<16> offset; 2361541Srgrimes 2371541Srgrimes bits<32> Inst; 2381541Srgrimes 2391541Srgrimes let Inst{31-26} = OPGROUP_COP1.Value; 2401541Srgrimes let Inst{25-21} = Operation.Value; 2411541Srgrimes let Inst{20-16} = ft; 2421541Srgrimes let Inst{15-0} = offset; 2431541Srgrimes} 2441541Srgrimes 2451541Srgrimesclass COP2_BCCZ_FM<OPCODE5 Operation> : MipsR6Inst { 2461541Srgrimes bits<5> ct; 2471541Srgrimes bits<16> offset; 2481541Srgrimes 2491541Srgrimes bits<32> Inst; 2501541Srgrimes 2511541Srgrimes let Inst{31-26} = OPGROUP_COP2.Value; 2521541Srgrimes let Inst{25-21} = Operation.Value; 2531541Srgrimes let Inst{20-16} = ct; 2541541Srgrimes let Inst{15-0} = offset; 2551541Srgrimes} 2561541Srgrimes 2571541Srgrimesclass PCREL16_FM<OPCODE5 Operation> : MipsR6Inst { 2581541Srgrimes bits<5> rs; 2591541Srgrimes bits<16> imm; 2601541Srgrimes 2611541Srgrimes bits<32> Inst; 2621541Srgrimes 2631541Srgrimes let Inst{31-26} = OPGROUP_PCREL.Value; 2641541Srgrimes let Inst{25-21} = rs; 2651541Srgrimes let Inst{20-16} = Operation.Value; 2661541Srgrimes let Inst{15-0} = imm; 2671541Srgrimes} 2681541Srgrimes 2691541Srgrimesclass PCREL19_FM<OPCODE2 Operation> : MipsR6Inst { 2701541Srgrimes bits<5> rs; 2711541Srgrimes bits<19> imm; 2721541Srgrimes 2731541Srgrimes bits<32> Inst; 2741541Srgrimes 2751541Srgrimes let Inst{31-26} = OPGROUP_PCREL.Value; 2761541Srgrimes let Inst{25-21} = rs; 2771541Srgrimes let Inst{20-19} = Operation.Value; 2781541Srgrimes let Inst{18-0} = imm; 2791541Srgrimes} 2801541Srgrimes 2811541Srgrimesclass PCREL18_FM<OPCODE3 Operation> : MipsR6Inst { 2821541Srgrimes bits<5> rs; 2831541Srgrimes bits<18> imm; 2841541Srgrimes 2851941Sdg bits<32> Inst; 2861541Srgrimes 2871541Srgrimes let Inst{31-26} = OPGROUP_PCREL.Value; 2881541Srgrimes let Inst{25-21} = rs; 2891541Srgrimes let Inst{20-18} = Operation.Value; 2901541Srgrimes let Inst{17-0} = imm; 2911541Srgrimes} 2921541Srgrimes 2931941Sdgclass SPECIAL3_2R_FM<OPCODE6 Operation> : MipsR6Inst { 2941541Srgrimes bits<5> rd; 2951541Srgrimes bits<5> rt; 2961541Srgrimes 2971541Srgrimes bits<32> Inst; 2981541Srgrimes 2991541Srgrimes let Inst{31-26} = OPGROUP_SPECIAL3.Value; 3001541Srgrimes let Inst{25-21} = 0b00000; 3011541Srgrimes let Inst{20-16} = rt; 3021541Srgrimes let Inst{15-11} = rd; 3031541Srgrimes let Inst{10-6} = 0b00000; 3041541Srgrimes let Inst{5-0} = Operation.Value; 3051541Srgrimes} 3061541Srgrimes 3071541Srgrimesclass SPECIAL3_MEM_FM<OPCODE6 Operation> : MipsR6Inst { 3081541Srgrimes bits<21> addr; 3091541Srgrimes bits<5> hint; 3101541Srgrimes bits<5> base = addr{20-16}; 3111541Srgrimes bits<9> offset = addr{8-0}; 3121541Srgrimes 3131541Srgrimes bits<32> Inst; 3141541Srgrimes 3151541Srgrimes let Inst{31-26} = OPGROUP_SPECIAL3.Value; 3161541Srgrimes let Inst{25-21} = base; 3171541Srgrimes let Inst{20-16} = hint; 3181541Srgrimes let Inst{15-7} = offset; 3191541Srgrimes let Inst{6} = 0; 3201541Srgrimes let Inst{5-0} = Operation.Value; 3211541Srgrimes} 3221541Srgrimes 3231541Srgrimesclass SPECIAL_2R_FM<OPCODE6 Operation> : MipsR6Inst { 3241541Srgrimes bits<5> rd; 3251541Srgrimes bits<5> rs; 3261541Srgrimes 3271541Srgrimes bits<32> Inst; 3281541Srgrimes 3291541Srgrimes let Inst{31-26} = OPGROUP_SPECIAL.Value; 3301541Srgrimes let Inst{25-21} = rs; 3311541Srgrimes let Inst{20-16} = 0b00000; 3321541Srgrimes let Inst{15-11} = rd; 3331541Srgrimes let Inst{10-6} = 0b00001; 3341541Srgrimes let Inst{5-0} = Operation.Value; 3351541Srgrimes} 3361541Srgrimes 3371541Srgrimesclass SPECIAL_3R_FM<bits<5> mulop, bits<6> funct> : MipsR6Inst { 3381541Srgrimes bits<5> rd; 3391541Srgrimes bits<5> rs; 3401541Srgrimes bits<5> rt; 3411541Srgrimes 3421541Srgrimes bits<32> Inst; 3431541Srgrimes 3441541Srgrimes let Inst{31-26} = OPGROUP_SPECIAL.Value; 3451541Srgrimes let Inst{25-21} = rs; 3461541Srgrimes let Inst{20-16} = rt; 3471541Srgrimes let Inst{15-11} = rd; 3481541Srgrimes let Inst{10-6} = mulop; 3491541Srgrimes let Inst{5-0} = funct; 3501541Srgrimes} 3511541Srgrimes 3521541Srgrimesclass SPECIAL_SDBBP_FM : MipsR6Inst { 3531541Srgrimes bits<20> code_; 3541541Srgrimes 3551541Srgrimes bits<32> Inst; 3561541Srgrimes 3571541Srgrimes let Inst{31-26} = OPGROUP_SPECIAL.Value; 3581541Srgrimes let Inst{25-6} = code_; 3591541Srgrimes let Inst{5-0} = OPCODE6_SDBBP.Value; 3601541Srgrimes} 3611541Srgrimes 3621549Srgrimes// This class is ambiguous with other branches: 3631541Srgrimes// BEQC/BNEC require that rs > rt 3641541Srgrimesclass CMP_BRANCH_2R_OFF16_FM<OPGROUP funct> : MipsR6Inst { 3651541Srgrimes bits<5> rs; 3661541Srgrimes bits<5> rt; 367 bits<16> offset; 368 369 bits<32> Inst; 370 371 let Inst{31-26} = funct.Value; 372 let Inst{25-21} = rs; 373 let Inst{20-16} = rt; 374 let Inst{15-0} = offset; 375} 376 377// This class is ambiguous with other branches: 378// BLEZC/BGEZC/BEQZALC/BNEZALC/BGTZALC require that rs == 0 && rt != 0 379// The '1R_RT' in the name means 1 register in the rt field. 380class CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP funct> : MipsR6Inst { 381 bits<5> rt; 382 bits<16> offset; 383 384 bits<32> Inst; 385 386 let Inst{31-26} = funct.Value; 387 let Inst{25-21} = 0b00000; 388 let Inst{20-16} = rt; 389 let Inst{15-0} = offset; 390} 391 392// This class is ambiguous with other branches: 393// BLTZC/BGTZC/BLTZALC/BGEZALC require that rs == rt && rt != 0 394// The '1R_BOTH' in the name means 1 register in both the rs and rt fields. 395class CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP funct> : MipsR6Inst { 396 bits<5> rt; 397 bits<16> offset; 398 399 bits<32> Inst; 400 401 let Inst{31-26} = funct.Value; 402 let Inst{25-21} = rt; 403 let Inst{20-16} = rt; 404 let Inst{15-0} = offset; 405} 406 407class CMP_BRANCH_OFF21_FM<bits<6> funct> : MipsR6Inst { 408 bits<5> rs; // rs != 0 409 bits<21> offset; 410 411 bits<32> Inst; 412 413 let Inst{31-26} = funct; 414 let Inst{25-21} = rs; 415 let Inst{20-0} = offset; 416} 417 418class JMP_IDX_COMPACT_FM<bits<6> funct> : MipsR6Inst { 419 bits<5> rt; 420 bits<16> offset; 421 422 bits<32> Inst; 423 424 let Inst{31-26} = funct; 425 let Inst{25-21} = 0b00000; 426 let Inst{20-16} = rt; 427 let Inst{15-0} = offset; 428} 429 430class BRANCH_OFF26_FM<bits<6> funct> : MipsR6Inst { 431 bits<32> Inst; 432 bits<26> offset; 433 434 let Inst{31-26} = funct; 435 let Inst{25-0} = offset; 436} 437 438class SPECIAL3_ALIGN_FM<OPCODE6 Operation> : MipsR6Inst { 439 bits<5> rd; 440 bits<5> rs; 441 bits<5> rt; 442 bits<2> bp; 443 444 bits<32> Inst; 445 446 let Inst{31-26} = OPGROUP_SPECIAL3.Value; 447 let Inst{25-21} = rs; 448 let Inst{20-16} = rt; 449 let Inst{15-11} = rd; 450 let Inst{10-8} = 0b010; 451 let Inst{7-6} = bp; 452 let Inst{5-0} = Operation.Value; 453} 454 455class SPECIAL3_DALIGN_FM<OPCODE6 Operation> : MipsR6Inst { 456 bits<5> rd; 457 bits<5> rs; 458 bits<5> rt; 459 bits<3> bp; 460 461 bits<32> Inst; 462 463 let Inst{31-26} = OPGROUP_SPECIAL3.Value; 464 let Inst{25-21} = rs; 465 let Inst{20-16} = rt; 466 let Inst{15-11} = rd; 467 let Inst{10-9} = 0b01; 468 let Inst{8-6} = bp; 469 let Inst{5-0} = Operation.Value; 470} 471 472class SPECIAL3_LL_SC_FM<OPCODE6 Operation> : MipsR6Inst { 473 bits<5> rt; 474 bits<21> addr; 475 bits<5> base = addr{20-16}; 476 bits<9> offset = addr{8-0}; 477 478 bits<32> Inst; 479 480 let Inst{31-26} = OPGROUP_SPECIAL3.Value; 481 let Inst{25-21} = base; 482 let Inst{20-16} = rt; 483 let Inst{15-7} = offset; 484 let Inst{5-0} = Operation.Value; 485 486 string DecoderMethod = "DecodeSpecial3LlSc"; 487} 488 489class SPECIAL_LSA_FM<OPCODE6 Operation> : MipsR6Inst { 490 bits<5> rd; 491 bits<5> rs; 492 bits<5> rt; 493 bits<2> imm2; 494 495 bits<32> Inst; 496 497 let Inst{31-26} = OPGROUP_SPECIAL.Value; 498 let Inst{25-21} = rs; 499 let Inst{20-16} = rt; 500 let Inst{15-11} = rd; 501 let Inst{10-8} = 0b000; 502 let Inst{7-6} = imm2; 503 let Inst{5-0} = Operation.Value; 504} 505 506class REGIMM_FM<OPCODE5 Operation> : MipsR6Inst { 507 bits<5> rs; 508 bits<16> imm; 509 510 bits<32> Inst; 511 512 let Inst{31-26} = OPGROUP_REGIMM.Value; 513 let Inst{25-21} = rs; 514 let Inst{20-16} = Operation.Value; 515 let Inst{15-0} = imm; 516} 517 518class COP1_CMP_CONDN_FM<FIELD_CMP_FORMAT Format, 519 FIELD_CMP_COND Cond> : MipsR6Inst { 520 bits<5> fd; 521 bits<5> fs; 522 bits<5> ft; 523 524 bits<32> Inst; 525 526 let Inst{31-26} = OPGROUP_COP1.Value; 527 let Inst{25-21} = Format.Value; 528 let Inst{20-16} = ft; 529 let Inst{15-11} = fs; 530 let Inst{10-6} = fd; 531 let Inst{5} = 0; 532 let Inst{4-0} = Cond.Value; 533} 534 535class JR_HB_R6_FM<OPCODE6 Operation> : MipsR6Inst { 536 bits<5> rs; 537 538 bits<32> Inst; 539 540 let Inst{31-26} = OPGROUP_SPECIAL.Value; 541 let Inst{25-21} = rs; 542 let Inst{20-16} = 0; 543 let Inst{15-11} = 0; 544 let Inst{10} = 1; 545 let Inst{9-6} = 0; 546 let Inst{5-0} = Operation.Value; 547} 548 549class COP2LDST_FM<OPCODE5 Operation> : MipsR6Inst { 550 bits<5> rt; 551 bits<21> addr; 552 bits<5> base = addr{20-16}; 553 bits<11> offset = addr{10-0}; 554 555 bits<32> Inst; 556 557 let Inst{31-26} = OPGROUP_COP2LDST.Value; 558 let Inst{25-21} = Operation.Value; 559 let Inst{20-16} = rt; 560 let Inst{15-11} = base; 561 let Inst{10-0} = offset; 562} 563