Mips.td revision 261991
1//===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// This is the top level entry point for the Mips target. 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// Register File, Calling Conv, Instruction Descriptions 20//===----------------------------------------------------------------------===// 21 22include "MipsRegisterInfo.td" 23include "MipsSchedule.td" 24include "MipsInstrInfo.td" 25include "MipsCallingConv.td" 26 27def MipsInstrInfo : InstrInfo; 28 29//===----------------------------------------------------------------------===// 30// Mips Subtarget features // 31//===----------------------------------------------------------------------===// 32 33def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", 34 "General Purpose Registers are 64-bit wide.">; 35def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", 36 "Support 64-bit FP registers.">; 37def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", 38 "true", "Only supports single precision float">; 39def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32", 40 "Enable o32 ABI">; 41def FeatureN32 : SubtargetFeature<"n32", "MipsABI", "N32", 42 "Enable n32 ABI">; 43def FeatureN64 : SubtargetFeature<"n64", "MipsABI", "N64", 44 "Enable n64 ABI">; 45def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI", 46 "Enable eabi ABI">; 47def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU", 48 "true", "Enable vector FPU instructions.">; 49def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true", 50 "Enable 'signext in register' instructions.">; 51def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true", 52 "Enable 'conditional move' instructions.">; 53def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true", 54 "Enable 'byte/half swap' instructions.">; 55def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true", 56 "Enable 'count leading bits' instructions.">; 57def FeatureFPIdx : SubtargetFeature<"FPIdx", "HasFPIdx", "true", 58 "Enable 'FP indexed load/store' instructions.">; 59def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32", 60 "Mips32 ISA Support", 61 [FeatureCondMov, FeatureBitCount]>; 62def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", 63 "Mips32r2", "Mips32r2 ISA Support", 64 [FeatureMips32, FeatureSEInReg, FeatureSwap, 65 FeatureFPIdx]>; 66def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion", 67 "Mips64", "Mips64 ISA Support", 68 [FeatureGP64Bit, FeatureFP64Bit, 69 FeatureMips32, FeatureFPIdx]>; 70def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion", 71 "Mips64r2", "Mips64r2 ISA Support", 72 [FeatureMips64, FeatureMips32r2]>; 73 74def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true", 75 "Mips16 mode">; 76 77def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">; 78def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true", 79 "Mips DSP-R2 ASE", [FeatureDSP]>; 80 81def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">; 82 83def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true", 84 "microMips mode">; 85 86//===----------------------------------------------------------------------===// 87// Mips processors supported. 88//===----------------------------------------------------------------------===// 89 90class Proc<string Name, list<SubtargetFeature> Features> 91 : Processor<Name, MipsGenericItineraries, Features>; 92 93def : Proc<"mips32", [FeatureMips32]>; 94def : Proc<"mips32r2", [FeatureMips32r2]>; 95def : Proc<"mips64", [FeatureMips64]>; 96def : Proc<"mips64r2", [FeatureMips64r2]>; 97def : Proc<"mips16", [FeatureMips16]>; 98 99def MipsAsmWriter : AsmWriter { 100 string AsmWriterClassName = "InstPrinter"; 101 bit isMCAsmWriter = 1; 102} 103 104def MipsAsmParser : AsmParser { 105 let ShouldEmitMatchRegisterName = 0; 106 let MnemonicContainsDot = 1; 107} 108 109def MipsAsmParserVariant : AsmParserVariant { 110 int Variant = 0; 111 112 // Recognize hard coded registers. 113 string RegisterPrefix = "$"; 114} 115 116def Mips : Target { 117 let InstructionSet = MipsInstrInfo; 118 let AssemblyParsers = [MipsAsmParser]; 119 let AssemblyWriters = [MipsAsmWriter]; 120 let AssemblyParserVariants = [MipsAsmParserVariant]; 121} 122