Mips.td revision 224145 
1//===- Mips.td - Describe the Mips Target Machine ----------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This is the top level entry point for the Mips target.
10//===----------------------------------------------------------------------===//
11
12//===----------------------------------------------------------------------===//
13// Target-independent interfaces
14//===----------------------------------------------------------------------===//
15
16include "llvm/Target/Target.td"
17
18//===----------------------------------------------------------------------===//
19// Register File, Calling Conv, Instruction Descriptions
20//===----------------------------------------------------------------------===//
21
22include "MipsRegisterInfo.td"
23include "MipsSchedule.td"
24include "MipsInstrInfo.td"
25include "MipsCallingConv.td"
26
27def MipsInstrInfo : InstrInfo;
28
29//===----------------------------------------------------------------------===//
30// Mips Subtarget features                                                    //
31//===----------------------------------------------------------------------===//
32
33def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
34                                "General Purpose Registers are 64-bit wide.">;
35def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
36                                "Support 64-bit FP registers.">;
37def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
38                                "true", "Only supports single precision float">;
39def FeatureO32         : SubtargetFeature<"o32", "MipsABI", "O32",
40                                "Enable o32 ABI">;
41def FeatureEABI        : SubtargetFeature<"eabi", "MipsABI", "EABI",
42                                "Enable eabi ABI">;
43def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU",
44                                "true", "Enable vector FPU instructions.">;
45def FeatureSEInReg     : SubtargetFeature<"seinreg", "HasSEInReg", "true",
46                                "Enable 'signext in register' instructions.">;
47def FeatureCondMov     : SubtargetFeature<"condmov", "HasCondMov", "true",
48                                "Enable 'conditional move' instructions.">;
49def FeatureMulDivAdd   : SubtargetFeature<"muldivadd", "HasMulDivAdd", "true",
50                                "Enable 'multiply add/sub' instructions.">;
51def FeatureMinMax      : SubtargetFeature<"minmax", "HasMinMax", "true",
52                                "Enable 'min/max' instructions.">;
53def FeatureSwap        : SubtargetFeature<"swap", "HasSwap", "true",
54                                "Enable 'byte/half swap' instructions.">;
55def FeatureBitCount    : SubtargetFeature<"bitcount", "HasBitCount", "true",
56                                "Enable 'count leading bits' instructions.">;
57def FeatureMips1       : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
58                                "Mips1 ISA Support">;
59def FeatureMips2       : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
60                                "Mips2 ISA Support">;
61def FeatureMips32      : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
62                                "Mips32 ISA Support",
63                                [FeatureCondMov, FeatureBitCount]>;
64def FeatureMips32r2    : SubtargetFeature<"mips32r2", "MipsArchVersion",
65                                "Mips32r2", "Mips32r2 ISA Support",
66                                [FeatureMips32, FeatureSEInReg]>;
67
68//===----------------------------------------------------------------------===//
69// Mips processors supported.
70//===----------------------------------------------------------------------===//
71
72class Proc<string Name, list<SubtargetFeature> Features>
73 : Processor<Name, MipsGenericItineraries, Features>;
74
75def : Proc<"mips1", [FeatureMips1]>;
76def : Proc<"r2000", [FeatureMips1]>;
77def : Proc<"r3000", [FeatureMips1]>;
78
79def : Proc<"mips2", [FeatureMips2]>;
80def : Proc<"r6000", [FeatureMips2]>;
81
82def : Proc<"4ke", [FeatureMips32r2]>;
83
84// Allegrex is a 32bit subset of r4000, both for integer and fp registers,
85// but much more similar to Mips2 than Mips3. It also contains some of
86// Mips32/Mips32r2 instructions and a custom vector fpu processor.
87def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI,
88      FeatureVFPU, FeatureSEInReg, FeatureCondMov, FeatureMulDivAdd,
89      FeatureMinMax, FeatureSwap, FeatureBitCount]>;
90
91def MipsAsmWriter : AsmWriter {
92  string AsmWriterClassName  = "InstPrinter";
93  bit isMCAsmWriter = 1;
94}
95
96def Mips : Target {
97  let InstructionSet = MipsInstrInfo;
98
99  let AssemblyWriters = [MipsAsmWriter];
100}
101
102