Mips.td revision 208954 
1//===- Mips.td - Describe the Mips Target Machine ---------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This is the top level entry point for the Mips target.
10//===----------------------------------------------------------------------===//
11
12//===----------------------------------------------------------------------===//
13// Target-independent interfaces
14//===----------------------------------------------------------------------===//
15
16include "llvm/Target/Target.td"
17
18//===----------------------------------------------------------------------===//
19// Register File, Calling Conv, Instruction Descriptions
20//===----------------------------------------------------------------------===//
21
22include "MipsRegisterInfo.td"
23include "MipsSchedule.td"
24include "MipsInstrInfo.td"
25include "MipsCallingConv.td"
26
27def MipsInstrInfo : InstrInfo;
28
29//===----------------------------------------------------------------------===//
30// Mips Subtarget features                                                    //
31//===----------------------------------------------------------------------===//
32
33def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
34                                "General Purpose Registers are 64-bit wide.">;
35def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
36                                "Support 64-bit FP registers.">;
37def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
38                                "true", "Only supports single precision float">;
39def FeatureMips1       : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
40                                "Mips1 ISA Support">;
41def FeatureMips2       : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
42                                "Mips2 ISA Support">;
43def FeatureO32         : SubtargetFeature<"o32", "MipsABI", "O32",
44                                "Enable o32 ABI">;
45def FeatureEABI        : SubtargetFeature<"eabi", "MipsABI", "EABI",
46                                "Enable eabi ABI">;
47def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU", 
48                                "true", "Enable vector FPU instructions.">;
49def FeatureSEInReg     : SubtargetFeature<"seinreg", "HasSEInReg", "true", 
50                                "Enable 'signext in register' instructions.">;
51def FeatureCondMov     : SubtargetFeature<"condmov", "HasCondMov", "true", 
52                                "Enable 'conditional move' instructions.">;
53def FeatureMulDivAdd   : SubtargetFeature<"muldivadd", "HasMulDivAdd", "true",
54                                "Enable 'multiply add/sub' instructions.">;
55def FeatureMinMax      : SubtargetFeature<"minmax", "HasMinMax", "true",
56                                "Enable 'min/max' instructions.">;
57def FeatureSwap        : SubtargetFeature<"swap", "HasSwap", "true",
58                                "Enable 'byte/half swap' instructions.">;
59def FeatureBitCount    : SubtargetFeature<"bitcount", "HasBitCount", "true",
60                                "Enable 'count leading bits' instructions.">;
61
62//===----------------------------------------------------------------------===//
63// Mips processors supported.
64//===----------------------------------------------------------------------===//
65
66class Proc<string Name, list<SubtargetFeature> Features>
67 : Processor<Name, MipsGenericItineraries, Features>;
68
69def : Proc<"mips1", [FeatureMips1]>;
70def : Proc<"r2000", [FeatureMips1]>;
71def : Proc<"r3000", [FeatureMips1]>;
72
73def : Proc<"mips2", [FeatureMips2]>;
74def : Proc<"r6000", [FeatureMips2]>;
75
76// Allegrex is a 32bit subset of r4000, both for interger and fp registers, 
77// but much more similar to Mips2 than Mips3. It also contains some of 
78// Mips32/Mips32r2 instructions and a custom vector fpu processor. 
79def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI, 
80      FeatureVFPU, FeatureSEInReg, FeatureCondMov, FeatureMulDivAdd,
81      FeatureMinMax, FeatureSwap, FeatureBitCount]>;
82
83def Mips : Target {
84  let InstructionSet = MipsInstrInfo;
85}
86