Mips.td revision 193323 
1//===- Mips.td - Describe the Mips Target Machine ---------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This is the top level entry point for the Mips target.
10//===----------------------------------------------------------------------===//
11
12//===----------------------------------------------------------------------===//
13// Target-independent interfaces
14//===----------------------------------------------------------------------===//
15
16include "llvm/Target/Target.td"
17
18//===----------------------------------------------------------------------===//
19// Register File, Calling Conv, Instruction Descriptions
20//===----------------------------------------------------------------------===//
21
22include "MipsRegisterInfo.td"
23include "MipsSchedule.td"
24include "MipsInstrInfo.td"
25include "MipsCallingConv.td"
26
27def MipsInstrInfo : InstrInfo {
28  let TSFlagsFields = [];
29  let TSFlagsShifts = [];
30}
31
32//===----------------------------------------------------------------------===//
33// Mips Subtarget features                                                    //
34//===----------------------------------------------------------------------===//
35
36def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
37                                "General Purpose Registers are 64-bit wide.">;
38def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
39                                "Support 64-bit FP registers.">;
40def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
41                                "true", "Only supports single precision float">;
42def FeatureMips1       : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
43                                "Mips1 ISA Support">;
44def FeatureMips2       : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
45                                "Mips2 ISA Support">;
46def FeatureO32         : SubtargetFeature<"o32", "MipsABI", "O32",
47                                "Enable o32 ABI">;
48def FeatureEABI        : SubtargetFeature<"eabi", "MipsABI", "EABI",
49                                "Enable eabi ABI">;
50def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU", 
51                                "true", "Enable vector FPU instructions.">;
52def FeatureSEInReg     : SubtargetFeature<"seinreg", "HasSEInReg", "true", 
53                                "Enable 'signext in register' instructions.">;
54def FeatureCondMov     : SubtargetFeature<"condmov", "HasCondMov", "true", 
55                                "Enable 'conditional move' instructions.">;
56def FeatureMulDivAdd   : SubtargetFeature<"muldivadd", "HasMulDivAdd", "true",
57                                "Enable 'multiply add/sub' instructions.">;
58def FeatureMinMax      : SubtargetFeature<"minmax", "HasMinMax", "true",
59                                "Enable 'min/max' instructions.">;
60def FeatureSwap        : SubtargetFeature<"swap", "HasSwap", "true",
61                                "Enable 'byte/half swap' instructions.">;
62def FeatureBitCount    : SubtargetFeature<"bitcount", "HasBitCount", "true",
63                                "Enable 'count leading bits' instructions.">;
64
65//===----------------------------------------------------------------------===//
66// Mips processors supported.
67//===----------------------------------------------------------------------===//
68
69class Proc<string Name, list<SubtargetFeature> Features>
70 : Processor<Name, MipsGenericItineraries, Features>;
71
72def : Proc<"mips1", [FeatureMips1]>;
73def : Proc<"r2000", [FeatureMips1]>;
74def : Proc<"r3000", [FeatureMips1]>;
75
76def : Proc<"mips2", [FeatureMips2]>;
77def : Proc<"r6000", [FeatureMips2]>;
78
79// Allegrex is a 32bit subset of r4000, both for interger and fp registers, 
80// but much more similar to Mips2 than Mips3. It also contains some of 
81// Mips32/Mips32r2 instructions and a custom vector fpu processor. 
82def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI, 
83      FeatureVFPU, FeatureSEInReg, FeatureCondMov, FeatureMulDivAdd,
84      FeatureMinMax, FeatureSwap, FeatureBitCount]>;
85
86def Mips : Target {
87  let InstructionSet = MipsInstrInfo;
88}
89