1226633Sdim//===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===// 2224133Sdim// 3224133Sdim// The LLVM Compiler Infrastructure 4224133Sdim// 5224133Sdim// This file is distributed under the University of Illinois Open Source 6224133Sdim// License. See LICENSE.TXT for details. 7224133Sdim// 8224133Sdim//===----------------------------------------------------------------------===// 9224133Sdim// 10226633Sdim// This file provides Mips specific target descriptions. 11224133Sdim// 12224133Sdim//===----------------------------------------------------------------------===// 13224133Sdim 14280031Sdim#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H 15280031Sdim#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H 16224133Sdim 17234353Sdim#include "llvm/Support/DataTypes.h" 18234353Sdim 19224133Sdimnamespace llvm { 20226633Sdimclass MCAsmBackend; 21226633Sdimclass MCCodeEmitter; 22226633Sdimclass MCContext; 23234353Sdimclass MCInstrInfo; 24234353Sdimclass MCObjectWriter; 25239462Sdimclass MCRegisterInfo; 26224133Sdimclass MCSubtargetInfo; 27226633Sdimclass StringRef; 28224133Sdimclass Target; 29288943Sdimclass Triple; 30234353Sdimclass raw_ostream; 31288943Sdimclass raw_pwrite_stream; 32224133Sdim 33224133Sdimextern Target TheMipsTarget; 34224133Sdimextern Target TheMipselTarget; 35226633Sdimextern Target TheMips64Target; 36226633Sdimextern Target TheMips64elTarget; 37224133Sdim 38234353SdimMCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, 39239462Sdim const MCRegisterInfo &MRI, 40234353Sdim MCContext &Ctx); 41234353SdimMCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, 42239462Sdim const MCRegisterInfo &MRI, 43234353Sdim MCContext &Ctx); 44226633Sdim 45276479SdimMCAsmBackend *createMipsAsmBackendEB32(const Target &T, 46288943Sdim const MCRegisterInfo &MRI, 47288943Sdim const Triple &TT, StringRef CPU); 48276479SdimMCAsmBackend *createMipsAsmBackendEL32(const Target &T, 49288943Sdim const MCRegisterInfo &MRI, 50288943Sdim const Triple &TT, StringRef CPU); 51276479SdimMCAsmBackend *createMipsAsmBackendEB64(const Target &T, 52288943Sdim const MCRegisterInfo &MRI, 53288943Sdim const Triple &TT, StringRef CPU); 54276479SdimMCAsmBackend *createMipsAsmBackendEL64(const Target &T, 55288943Sdim const MCRegisterInfo &MRI, 56288943Sdim const Triple &TT, StringRef CPU); 57234353Sdim 58288943SdimMCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, 59288943Sdim bool IsLittleEndian, bool Is64Bit); 60288943Sdim 61288943Sdimnamespace MIPS_MC { 62288943SdimStringRef selectMipsCPU(const Triple &TT, StringRef CPU); 63288943Sdim} 64288943Sdim 65224133Sdim} // End llvm namespace 66224133Sdim 67224133Sdim// Defines symbolic names for Mips registers. This defines a mapping from 68224133Sdim// register name to register number. 69224133Sdim#define GET_REGINFO_ENUM 70224133Sdim#include "MipsGenRegisterInfo.inc" 71224133Sdim 72224133Sdim// Defines symbolic names for the Mips instructions. 73224133Sdim#define GET_INSTRINFO_ENUM 74224133Sdim#include "MipsGenInstrInfo.inc" 75224133Sdim 76224133Sdim#define GET_SUBTARGETINFO_ENUM 77224133Sdim#include "MipsGenSubtargetInfo.inc" 78224133Sdim 79224133Sdim#endif 80