MipsMCCodeEmitter.h revision 288943
1//===-- MipsMCCodeEmitter.h - Convert Mips Code to Machine Code -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the MipsMCCodeEmitter class. 11// 12//===----------------------------------------------------------------------===// 13// 14 15#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H 16#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H 17 18#include "llvm/MC/MCCodeEmitter.h" 19#include "llvm/Support/DataTypes.h" 20 21using namespace llvm; 22 23namespace llvm { 24class MCContext; 25class MCExpr; 26class MCInst; 27class MCInstrInfo; 28class MCFixup; 29class MCOperand; 30class MCSubtargetInfo; 31class raw_ostream; 32 33class MipsMCCodeEmitter : public MCCodeEmitter { 34 MipsMCCodeEmitter(const MipsMCCodeEmitter &) = delete; 35 void operator=(const MipsMCCodeEmitter &) = delete; 36 const MCInstrInfo &MCII; 37 MCContext &Ctx; 38 bool IsLittleEndian; 39 40 bool isMicroMips(const MCSubtargetInfo &STI) const; 41 bool isMips32r6(const MCSubtargetInfo &STI) const; 42 43public: 44 MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle) 45 : MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) {} 46 47 ~MipsMCCodeEmitter() override {} 48 49 void EmitByte(unsigned char C, raw_ostream &OS) const; 50 51 void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, 52 raw_ostream &OS) const; 53 54 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 55 SmallVectorImpl<MCFixup> &Fixups, 56 const MCSubtargetInfo &STI) const override; 57 58 // getBinaryCodeForInstr - TableGen'erated function for getting the 59 // binary encoding for an instruction. 60 uint64_t getBinaryCodeForInstr(const MCInst &MI, 61 SmallVectorImpl<MCFixup> &Fixups, 62 const MCSubtargetInfo &STI) const; 63 64 // getJumpTargetOpValue - Return binary encoding of the jump 65 // target operand. If the machine operand requires relocation, 66 // record the relocation and return zero. 67 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, 68 SmallVectorImpl<MCFixup> &Fixups, 69 const MCSubtargetInfo &STI) const; 70 71 // getBranchJumpOpValueMM - Return binary encoding of the microMIPS jump 72 // target operand. If the machine operand requires relocation, 73 // record the relocation and return zero. 74 unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, 75 SmallVectorImpl<MCFixup> &Fixups, 76 const MCSubtargetInfo &STI) const; 77 78 // getUImm5Lsl2Encoding - Return binary encoding of the microMIPS jump 79 // target operand. 80 unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo, 81 SmallVectorImpl<MCFixup> &Fixups, 82 const MCSubtargetInfo &STI) const; 83 84 unsigned getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo, 85 SmallVectorImpl<MCFixup> &Fixups, 86 const MCSubtargetInfo &STI) const; 87 88 unsigned getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo, 89 SmallVectorImpl<MCFixup> &Fixups, 90 const MCSubtargetInfo &STI) const; 91 92 // getSImm9AddiuspValue - Return binary encoding of the microMIPS addiusp 93 // instruction immediate operand. 94 unsigned getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo, 95 SmallVectorImpl<MCFixup> &Fixups, 96 const MCSubtargetInfo &STI) const; 97 98 // getBranchTargetOpValue - Return binary encoding of the branch 99 // target operand. If the machine operand requires relocation, 100 // record the relocation and return zero. 101 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, 102 SmallVectorImpl<MCFixup> &Fixups, 103 const MCSubtargetInfo &STI) const; 104 105 // getBranchTarget7OpValue - Return binary encoding of the microMIPS branch 106 // target operand. If the machine operand requires relocation, 107 // record the relocation and return zero. 108 unsigned getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo, 109 SmallVectorImpl<MCFixup> &Fixups, 110 const MCSubtargetInfo &STI) const; 111 112 // getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS 113 // 10-bit branch target operand. If the machine operand requires relocation, 114 // record the relocation and return zero. 115 unsigned getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo, 116 SmallVectorImpl<MCFixup> &Fixups, 117 const MCSubtargetInfo &STI) const; 118 119 // getBranchTargetOpValue - Return binary encoding of the microMIPS branch 120 // target operand. If the machine operand requires relocation, 121 // record the relocation and return zero. 122 unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, 123 SmallVectorImpl<MCFixup> &Fixups, 124 const MCSubtargetInfo &STI) const; 125 126 // getBranchTarget21OpValue - Return binary encoding of the branch 127 // offset operand. If the machine operand requires relocation, 128 // record the relocation and return zero. 129 unsigned getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo, 130 SmallVectorImpl<MCFixup> &Fixups, 131 const MCSubtargetInfo &STI) const; 132 133 // getBranchTarget26OpValue - Return binary encoding of the branch 134 // offset operand. If the machine operand requires relocation, 135 // record the relocation and return zero. 136 unsigned getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo, 137 SmallVectorImpl<MCFixup> &Fixups, 138 const MCSubtargetInfo &STI) const; 139 140 // getJumpOffset16OpValue - Return binary encoding of the jump 141 // offset operand. If the machine operand requires relocation, 142 // record the relocation and return zero. 143 unsigned getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo, 144 SmallVectorImpl<MCFixup> &Fixups, 145 const MCSubtargetInfo &STI) const; 146 147 // getMachineOpValue - Return binary encoding of operand. If the machin 148 // operand requires relocation, record the relocation and return zero. 149 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 150 SmallVectorImpl<MCFixup> &Fixups, 151 const MCSubtargetInfo &STI) const; 152 153 unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo, 154 SmallVectorImpl<MCFixup> &Fixups, 155 const MCSubtargetInfo &STI) const; 156 157 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo, 158 SmallVectorImpl<MCFixup> &Fixups, 159 const MCSubtargetInfo &STI) const; 160 unsigned getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo, 161 SmallVectorImpl<MCFixup> &Fixups, 162 const MCSubtargetInfo &STI) const; 163 unsigned getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo, 164 SmallVectorImpl<MCFixup> &Fixups, 165 const MCSubtargetInfo &STI) const; 166 unsigned getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo, 167 SmallVectorImpl<MCFixup> &Fixups, 168 const MCSubtargetInfo &STI) const; 169 unsigned getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo, 170 SmallVectorImpl<MCFixup> &Fixups, 171 const MCSubtargetInfo &STI) const; 172 unsigned getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo, 173 SmallVectorImpl<MCFixup> &Fixups, 174 const MCSubtargetInfo &STI) const; 175 unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, 176 SmallVectorImpl<MCFixup> &Fixups, 177 const MCSubtargetInfo &STI) const; 178 unsigned getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, 179 SmallVectorImpl<MCFixup> &Fixups, 180 const MCSubtargetInfo &STI) const; 181 unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo, 182 SmallVectorImpl<MCFixup> &Fixups, 183 const MCSubtargetInfo &STI) const; 184 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo, 185 SmallVectorImpl<MCFixup> &Fixups, 186 const MCSubtargetInfo &STI) const; 187 188 // getLSAImmEncoding - Return binary encoding of LSA immediate. 189 unsigned getLSAImmEncoding(const MCInst &MI, unsigned OpNo, 190 SmallVectorImpl<MCFixup> &Fixups, 191 const MCSubtargetInfo &STI) const; 192 193 unsigned getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo, 194 SmallVectorImpl<MCFixup> &Fixups, 195 const MCSubtargetInfo &STI) const; 196 197 unsigned getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo, 198 SmallVectorImpl<MCFixup> &Fixups, 199 const MCSubtargetInfo &STI) const; 200 201 unsigned getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo, 202 SmallVectorImpl<MCFixup> &Fixups, 203 const MCSubtargetInfo &STI) const; 204 unsigned getUImm4AndValue(const MCInst &MI, unsigned OpNo, 205 SmallVectorImpl<MCFixup> &Fixups, 206 const MCSubtargetInfo &STI) const; 207 208 unsigned getRegisterPairOpValue(const MCInst &MI, unsigned OpNo, 209 SmallVectorImpl<MCFixup> &Fixups, 210 const MCSubtargetInfo &STI) const; 211 212 unsigned getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo, 213 SmallVectorImpl<MCFixup> &Fixups, 214 const MCSubtargetInfo &STI) const; 215 216 unsigned getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo, 217 SmallVectorImpl<MCFixup> &Fixups, 218 const MCSubtargetInfo &STI) const; 219 220 unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups, 221 const MCSubtargetInfo &STI) const; 222 223 unsigned getRegisterListOpValue(const MCInst &MI, unsigned OpNo, 224 SmallVectorImpl<MCFixup> &Fixups, 225 const MCSubtargetInfo &STI) const; 226 227 unsigned getRegisterListOpValue16(const MCInst &MI, unsigned OpNo, 228 SmallVectorImpl<MCFixup> &Fixups, 229 const MCSubtargetInfo &STI) const; 230}; // class MipsMCCodeEmitter 231} // namespace llvm. 232 233#endif 234