MSP430RegisterInfo.td revision 280031
1207618Srdivacky//===-- MSP430RegisterInfo.td - MSP430 Register defs -------*- tablegen -*-===// 2207618Srdivacky// 3207618Srdivacky// The LLVM Compiler Infrastructure 4207618Srdivacky// 5207618Srdivacky// This file is distributed under the University of Illinois Open Source 6207618Srdivacky// License. See LICENSE.TXT for details. 7207618Srdivacky// 8207618Srdivacky//===----------------------------------------------------------------------===// 9207618Srdivacky 10207618Srdivacky//===----------------------------------------------------------------------===// 11207618Srdivacky// Declarations that describe the MSP430 register file 12207618Srdivacky//===----------------------------------------------------------------------===// 13207618Srdivacky 14207618Srdivackyclass MSP430Reg<bits<4> num, string n> : Register<n> { 15207618Srdivacky field bits<4> Num = num; 16207618Srdivacky let Namespace = "MSP430"; 17207618Srdivacky} 18207618Srdivacky 19207618Srdivackyclass MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs> 20207618Srdivacky : RegisterWithSubRegs<n, subregs> { 21208599Srdivacky field bits<4> Num = num; 22208599Srdivacky let Namespace = "MSP430"; 23207618Srdivacky} 24207618Srdivacky 25208599Srdivacky//===----------------------------------------------------------------------===// 26207618Srdivacky// Registers 27207618Srdivacky//===----------------------------------------------------------------------===// 28207618Srdivacky 29207618Srdivackydef PCB : MSP430Reg<0, "r0">; 30207618Srdivackydef SPB : MSP430Reg<1, "r1">; 31207618Srdivackydef SRB : MSP430Reg<2, "r2">; 32def CGB : MSP430Reg<3, "r3">; 33def FPB : MSP430Reg<4, "r4">; 34def R5B : MSP430Reg<5, "r5">; 35def R6B : MSP430Reg<6, "r6">; 36def R7B : MSP430Reg<7, "r7">; 37def R8B : MSP430Reg<8, "r8">; 38def R9B : MSP430Reg<9, "r9">; 39def R10B : MSP430Reg<10, "r10">; 40def R11B : MSP430Reg<11, "r11">; 41def R12B : MSP430Reg<12, "r12">; 42def R13B : MSP430Reg<13, "r13">; 43def R14B : MSP430Reg<14, "r14">; 44def R15B : MSP430Reg<15, "r15">; 45 46def subreg_8bit : SubRegIndex<8> { let Namespace = "MSP430"; } 47 48let SubRegIndices = [subreg_8bit] in { 49def PC : MSP430RegWithSubregs<0, "r0", [PCB]>; 50def SP : MSP430RegWithSubregs<1, "r1", [SPB]>; 51def SR : MSP430RegWithSubregs<2, "r2", [SRB]>; 52def CG : MSP430RegWithSubregs<3, "r3", [CGB]>; 53def FP : MSP430RegWithSubregs<4, "r4", [FPB]>; 54def R5 : MSP430RegWithSubregs<5, "r5", [R5B]>; 55def R6 : MSP430RegWithSubregs<6, "r6", [R6B]>; 56def R7 : MSP430RegWithSubregs<7, "r7", [R7B]>; 57def R8 : MSP430RegWithSubregs<8, "r8", [R8B]>; 58def R9 : MSP430RegWithSubregs<9, "r9", [R9B]>; 59def R10 : MSP430RegWithSubregs<10, "r10", [R10B]>; 60def R11 : MSP430RegWithSubregs<11, "r11", [R11B]>; 61def R12 : MSP430RegWithSubregs<12, "r12", [R12B]>; 62def R13 : MSP430RegWithSubregs<13, "r13", [R13B]>; 63def R14 : MSP430RegWithSubregs<14, "r14", [R14B]>; 64def R15 : MSP430RegWithSubregs<15, "r15", [R15B]>; 65} 66 67def GR8 : RegisterClass<"MSP430", [i8], 8, 68 // Volatile registers 69 (add R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B, 70 // Frame pointer, sometimes allocable 71 FPB, 72 // Volatile, but not allocable 73 PCB, SPB, SRB, CGB)>; 74 75def GR16 : RegisterClass<"MSP430", [i16], 16, 76 // Volatile registers 77 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5, 78 // Frame pointer, sometimes allocable 79 FP, 80 // Volatile, but not allocable 81 PC, SP, SR, CG)>; 82