1234353Sdim//===-- MSP430RegisterInfo.td - MSP430 Register defs -------*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed// Declarations that describe the MSP430 register file 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sedclass MSP430Reg<bits<4> num, string n> : Register<n> { 15193323Sed field bits<4> Num = num; 16193323Sed let Namespace = "MSP430"; 17193323Sed} 18193323Sed 19193323Sedclass MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs> 20193323Sed : RegisterWithSubRegs<n, subregs> { 21193323Sed field bits<4> Num = num; 22193323Sed let Namespace = "MSP430"; 23193323Sed} 24193323Sed 25193323Sed//===----------------------------------------------------------------------===// 26193323Sed// Registers 27193323Sed//===----------------------------------------------------------------------===// 28193323Sed 29193323Seddef PCB : MSP430Reg<0, "r0">; 30193323Seddef SPB : MSP430Reg<1, "r1">; 31193323Seddef SRB : MSP430Reg<2, "r2">; 32193323Seddef CGB : MSP430Reg<3, "r3">; 33193323Seddef FPB : MSP430Reg<4, "r4">; 34193323Seddef R5B : MSP430Reg<5, "r5">; 35193323Seddef R6B : MSP430Reg<6, "r6">; 36193323Seddef R7B : MSP430Reg<7, "r7">; 37193323Seddef R8B : MSP430Reg<8, "r8">; 38193323Seddef R9B : MSP430Reg<9, "r9">; 39193323Seddef R10B : MSP430Reg<10, "r10">; 40193323Seddef R11B : MSP430Reg<11, "r11">; 41193323Seddef R12B : MSP430Reg<12, "r12">; 42193323Seddef R13B : MSP430Reg<13, "r13">; 43193323Seddef R14B : MSP430Reg<14, "r14">; 44193323Seddef R15B : MSP430Reg<15, "r15">; 45193323Sed 46261991Sdimdef subreg_8bit : SubRegIndex<8> { let Namespace = "MSP430"; } 47208599Srdivacky 48208599Srdivackylet SubRegIndices = [subreg_8bit] in { 49280031Sdimdef PC : MSP430RegWithSubregs<0, "r0", [PCB]>; 50280031Sdimdef SP : MSP430RegWithSubregs<1, "r1", [SPB]>; 51280031Sdimdef SR : MSP430RegWithSubregs<2, "r2", [SRB]>; 52280031Sdimdef CG : MSP430RegWithSubregs<3, "r3", [CGB]>; 53280031Sdimdef FP : MSP430RegWithSubregs<4, "r4", [FPB]>; 54280031Sdimdef R5 : MSP430RegWithSubregs<5, "r5", [R5B]>; 55280031Sdimdef R6 : MSP430RegWithSubregs<6, "r6", [R6B]>; 56280031Sdimdef R7 : MSP430RegWithSubregs<7, "r7", [R7B]>; 57280031Sdimdef R8 : MSP430RegWithSubregs<8, "r8", [R8B]>; 58280031Sdimdef R9 : MSP430RegWithSubregs<9, "r9", [R9B]>; 59280031Sdimdef R10 : MSP430RegWithSubregs<10, "r10", [R10B]>; 60280031Sdimdef R11 : MSP430RegWithSubregs<11, "r11", [R11B]>; 61280031Sdimdef R12 : MSP430RegWithSubregs<12, "r12", [R12B]>; 62280031Sdimdef R13 : MSP430RegWithSubregs<13, "r13", [R13B]>; 63280031Sdimdef R14 : MSP430RegWithSubregs<14, "r14", [R14B]>; 64280031Sdimdef R15 : MSP430RegWithSubregs<15, "r15", [R15B]>; 65208599Srdivacky} 66193323Sed 67193323Seddef GR8 : RegisterClass<"MSP430", [i8], 8, 68193323Sed // Volatile registers 69224145Sdim (add R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B, 70193323Sed // Frame pointer, sometimes allocable 71193323Sed FPB, 72193323Sed // Volatile, but not allocable 73224145Sdim PCB, SPB, SRB, CGB)>; 74193323Sed 75193323Seddef GR16 : RegisterClass<"MSP430", [i16], 16, 76193323Sed // Volatile registers 77280031Sdim (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5, 78193323Sed // Frame pointer, sometimes allocable 79280031Sdim FP, 80193323Sed // Volatile, but not allocable 81280031Sdim PC, SP, SR, CG)>; 82