HexagonRegisterInfo.h revision 249423
1255570Strasz//==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==// 2255570Strasz// 3255570Strasz// The LLVM Compiler Infrastructure 4255570Strasz// 5255570Strasz// This file is distributed under the University of Illinois Open Source 6255570Strasz// License. See LICENSE.TXT for details. 7255570Strasz// 8255570Strasz//===----------------------------------------------------------------------===// 9255570Strasz// 10255570Strasz// This file contains the Hexagon implementation of the TargetRegisterInfo 11255570Strasz// class. 12255570Strasz// 13255570Strasz//===----------------------------------------------------------------------===// 14255570Strasz 15255570Strasz#ifndef HexagonREGISTERINFO_H 16255570Strasz#define HexagonREGISTERINFO_H 17255570Strasz 18255570Strasz#include "llvm/MC/MachineLocation.h" 19255570Strasz#include "llvm/Target/TargetRegisterInfo.h" 20255570Strasz 21255570Strasz#define GET_REGINFO_HEADER 22255570Strasz#include "HexagonGenRegisterInfo.inc" 23255570Strasz 24255570Strasz// 25255570Strasz// We try not to hard code the reserved registers in our code, 26255570Strasz// so the following two macros were defined. However, there 27255570Strasz// are still a few places that R11 and R10 are hard wired. 28255570Strasz// See below. If, in the future, we decided to change the reserved 29255570Strasz// register. Don't forget changing the following places. 30255570Strasz// 31255570Strasz// 1. the "Defs" set of STriw_pred in HexagonInstrInfo.td 32255570Strasz// 2. the "Defs" set of LDri_pred in HexagonInstrInfo.td 33255570Strasz// 3. the definition of "IntRegs" in HexagonRegisterInfo.td 34255570Strasz// 4. the definition of "DoubleRegs" in HexagonRegisterInfo.td 35255570Strasz// 36255570Strasz#define HEXAGON_RESERVED_REG_1 Hexagon::R10 37255570Strasz#define HEXAGON_RESERVED_REG_2 Hexagon::R11 38255570Strasz 39255570Strasznamespace llvm { 40255570Strasz 41255570Straszclass HexagonSubtarget; 42255570Straszclass HexagonInstrInfo; 43255570Straszclass Type; 44255570Strasz 45255570Straszstruct HexagonRegisterInfo : public HexagonGenRegisterInfo { 46255570Strasz HexagonSubtarget &Subtarget; 47255570Strasz const HexagonInstrInfo &TII; 48255570Strasz 49255570Strasz HexagonRegisterInfo(HexagonSubtarget &st, const HexagonInstrInfo &tii); 50255570Strasz 51255570Strasz /// Code Generation virtual methods... 52255570Strasz const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const; 53255570Strasz 54255570Strasz const TargetRegisterClass* const* getCalleeSavedRegClasses( 55255570Strasz const MachineFunction *MF = 0) const; 56255570Strasz 57255570Strasz BitVector getReservedRegs(const MachineFunction &MF) const; 58255570Strasz 59255570Strasz void eliminateFrameIndex(MachineBasicBlock::iterator II, 60255570Strasz int SPAdj, unsigned FIOperandNum, 61255570Strasz RegScavenger *RS = NULL) const; 62256163Strasz 63255570Strasz /// determineFrameLayout - Determine the size of the frame and maximum call 64255570Strasz /// frame size. 65255570Strasz void determineFrameLayout(MachineFunction &MF) const; 66255570Strasz 67255570Strasz /// requiresRegisterScavenging - returns true since we may need scavenging for 68255570Strasz /// a temporary register when generating hardware loop instructions. 69255570Strasz bool requiresRegisterScavenging(const MachineFunction &MF) const { 70255570Strasz return true; 71255570Strasz } 72255570Strasz 73255570Strasz bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 74255570Strasz return true; 75255570Strasz } 76255570Strasz 77255570Strasz // Debug information queries. 78265508Strasz unsigned getRARegister() const; 79265508Strasz unsigned getFrameRegister(const MachineFunction &MF) const; 80265508Strasz unsigned getFrameRegister() const; 81265508Strasz void getInitialFrameState(std::vector<MachineMove> &Moves) const; 82255570Strasz unsigned getStackRegister() const; 83255570Strasz 84255570Strasz // Exception handling queries. 85255570Strasz unsigned getEHExceptionRegister() const; 86255570Strasz unsigned getEHHandlerRegister() const; 87255570Strasz}; 88255570Strasz 89265501Strasz} // end namespace llvm 90255570Strasz 91255570Strasz#endif 92255570Strasz