1293838Sdim//===--- HexagonRDF.cpp ---------------------------------------------------===//
2293838Sdim//
3293838Sdim//                     The LLVM Compiler Infrastructure
4293838Sdim//
5293838Sdim// This file is distributed under the University of Illinois Open Source
6293838Sdim// License. See LICENSE.TXT for details.
7293838Sdim//
8293838Sdim//===----------------------------------------------------------------------===//
9293838Sdim
10293838Sdim#include "HexagonRDF.h"
11293838Sdim#include "HexagonInstrInfo.h"
12293838Sdim#include "HexagonRegisterInfo.h"
13293838Sdim
14293838Sdim#include "llvm/CodeGen/MachineInstr.h"
15293838Sdim
16293838Sdimusing namespace llvm;
17293838Sdimusing namespace rdf;
18293838Sdim
19293838Sdimbool HexagonRegisterAliasInfo::covers(RegisterRef RA, RegisterRef RB) const {
20293838Sdim  if (RA == RB)
21293838Sdim    return true;
22293838Sdim
23293838Sdim  if (TargetRegisterInfo::isVirtualRegister(RA.Reg) &&
24293838Sdim      TargetRegisterInfo::isVirtualRegister(RB.Reg)) {
25293838Sdim    // Hexagon-specific cases.
26293838Sdim    if (RA.Reg == RB.Reg) {
27293838Sdim      if (RA.Sub == 0)
28293838Sdim        return true;
29293838Sdim      if (RB.Sub == 0)
30293838Sdim        return false;
31293838Sdim    }
32293838Sdim  }
33293838Sdim
34293838Sdim  return RegisterAliasInfo::covers(RA, RB);
35293838Sdim}
36293838Sdim
37293838Sdimbool HexagonRegisterAliasInfo::covers(const RegisterSet &RRs, RegisterRef RR)
38293838Sdim      const {
39293838Sdim  if (RRs.count(RR))
40293838Sdim    return true;
41293838Sdim
42293838Sdim  if (!TargetRegisterInfo::isPhysicalRegister(RR.Reg)) {
43293838Sdim    assert(TargetRegisterInfo::isVirtualRegister(RR.Reg));
44293838Sdim    // Check if both covering subregisters are present.
45293838Sdim    bool HasLo = RRs.count({RR.Reg, Hexagon::subreg_loreg});
46293838Sdim    bool HasHi = RRs.count({RR.Reg, Hexagon::subreg_hireg});
47293838Sdim    if (HasLo && HasHi)
48293838Sdim      return true;
49293838Sdim  }
50293838Sdim
51293838Sdim  if (RR.Sub == 0) {
52293838Sdim    // Check if both covering subregisters are present.
53293838Sdim    unsigned Lo = TRI.getSubReg(RR.Reg, Hexagon::subreg_loreg);
54293838Sdim    unsigned Hi = TRI.getSubReg(RR.Reg, Hexagon::subreg_hireg);
55293838Sdim    if (RRs.count({Lo, 0}) && RRs.count({Hi, 0}))
56293838Sdim      return true;
57293838Sdim  }
58293838Sdim
59293838Sdim  return RegisterAliasInfo::covers(RRs, RR);
60293838Sdim}
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