HexagonInstrInfo.cpp revision 234285 
1//===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Hexagon implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "HexagonInstrInfo.h"
15#include "HexagonRegisterInfo.h"
16#include "HexagonSubtarget.h"
17#include "Hexagon.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/ADT/SmallVector.h"
20#include "llvm/CodeGen/DFAPacketizer.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineMemOperand.h"
25#include "llvm/CodeGen/PseudoSourceValue.h"
26#include "llvm/Support/MathExtras.h"
27#define GET_INSTRINFO_CTOR
28#include "HexagonGenInstrInfo.inc"
29#include "HexagonGenDFAPacketizer.inc"
30
31using namespace llvm;
32
33///
34/// Constants for Hexagon instructions.
35///
36const int Hexagon_MEMW_OFFSET_MAX = 4095;
37const int Hexagon_MEMW_OFFSET_MIN = 4096;
38const int Hexagon_MEMD_OFFSET_MAX = 8191;
39const int Hexagon_MEMD_OFFSET_MIN = 8192;
40const int Hexagon_MEMH_OFFSET_MAX = 2047;
41const int Hexagon_MEMH_OFFSET_MIN = 2048;
42const int Hexagon_MEMB_OFFSET_MAX = 1023;
43const int Hexagon_MEMB_OFFSET_MIN = 1024;
44const int Hexagon_ADDI_OFFSET_MAX = 32767;
45const int Hexagon_ADDI_OFFSET_MIN = 32768;
46const int Hexagon_MEMD_AUTOINC_MAX = 56;
47const int Hexagon_MEMD_AUTOINC_MIN = 64;
48const int Hexagon_MEMW_AUTOINC_MAX = 28;
49const int Hexagon_MEMW_AUTOINC_MIN = 32;
50const int Hexagon_MEMH_AUTOINC_MAX = 14;
51const int Hexagon_MEMH_AUTOINC_MIN = 16;
52const int Hexagon_MEMB_AUTOINC_MAX = 7;
53const int Hexagon_MEMB_AUTOINC_MIN = 8;
54
55
56
57HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
58  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
59    RI(ST, *this), Subtarget(ST) {
60}
61
62
63/// isLoadFromStackSlot - If the specified machine instruction is a direct
64/// load from a stack slot, return the virtual or physical register number of
65/// the destination along with the FrameIndex of the loaded stack slot.  If
66/// not, return 0.  This predicate must return 0 if the instruction has
67/// any side effects other than loading from the stack slot.
68unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
69                                             int &FrameIndex) const {
70
71
72  switch (MI->getOpcode()) {
73  case Hexagon::LDriw:
74  case Hexagon::LDrid:
75  case Hexagon::LDrih:
76  case Hexagon::LDrib:
77  case Hexagon::LDriub:
78    if (MI->getOperand(2).isFI() &&
79        MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
80      FrameIndex = MI->getOperand(2).getIndex();
81      return MI->getOperand(0).getReg();
82    }
83    break;
84
85  default:
86    break;
87  }
88
89  return 0;
90}
91
92
93/// isStoreToStackSlot - If the specified machine instruction is a direct
94/// store to a stack slot, return the virtual or physical register number of
95/// the source reg along with the FrameIndex of the loaded stack slot.  If
96/// not, return 0.  This predicate must return 0 if the instruction has
97/// any side effects other than storing to the stack slot.
98unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
99                                            int &FrameIndex) const {
100  switch (MI->getOpcode()) {
101  case Hexagon::STriw:
102  case Hexagon::STrid:
103  case Hexagon::STrih:
104  case Hexagon::STrib:
105    if (MI->getOperand(2).isFI() &&
106        MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
107      FrameIndex = MI->getOperand(2).getIndex();
108      return MI->getOperand(0).getReg();
109    }
110    break;
111
112  default:
113    break;
114  }
115
116  return 0;
117}
118
119
120unsigned
121HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
122                             MachineBasicBlock *FBB,
123                             const SmallVectorImpl<MachineOperand> &Cond,
124                             DebugLoc DL) const{
125
126    int BOpc   = Hexagon::JMP;
127    int BccOpc = Hexagon::JMP_c;
128
129    assert(TBB && "InsertBranch must not be told to insert a fallthrough");
130
131    int regPos = 0;
132    // Check if ReverseBranchCondition has asked to reverse this branch
133    // If we want to reverse the branch an odd number of times, we want
134    // JMP_cNot.
135    if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
136      BccOpc = Hexagon::JMP_cNot;
137      regPos = 1;
138    }
139
140    if (FBB == 0) {
141      if (Cond.empty()) {
142        // Due to a bug in TailMerging/CFG Optimization, we need to add a
143        // special case handling of a predicated jump followed by an
144        // unconditional jump. If not, Tail Merging and CFG Optimization go
145        // into an infinite loop.
146        MachineBasicBlock *NewTBB, *NewFBB;
147        SmallVector<MachineOperand, 4> Cond;
148        MachineInstr *Term = MBB.getFirstTerminator();
149        if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
150                                                 false)) {
151          MachineBasicBlock *NextBB =
152            llvm::next(MachineFunction::iterator(&MBB));
153          if (NewTBB == NextBB) {
154            ReverseBranchCondition(Cond);
155            RemoveBranch(MBB);
156            return InsertBranch(MBB, TBB, 0, Cond, DL);
157          }
158        }
159        BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
160      } else {
161        BuildMI(&MBB, DL,
162                get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
163      }
164      return 1;
165    }
166
167    BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
168    BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
169
170    return 2;
171}
172
173
174bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
175                                     MachineBasicBlock *&TBB,
176                                 MachineBasicBlock *&FBB,
177                                 SmallVectorImpl<MachineOperand> &Cond,
178                                 bool AllowModify) const {
179  FBB = NULL;
180
181  // If the block has no terminators, it just falls into the block after it.
182  MachineBasicBlock::iterator I = MBB.end();
183  if (I == MBB.begin())
184    return false;
185
186  // A basic block may looks like this:
187  //
188  //  [   insn
189  //     EH_LABEL
190  //      insn
191  //      insn
192  //      insn
193  //     EH_LABEL
194  //      insn     ]
195  //
196  // It has two succs but does not have a terminator
197  // Don't know how to handle it.
198  do {
199    --I;
200    if (I->isEHLabel())
201      return true;
202  } while (I != MBB.begin());
203
204  I = MBB.end();
205  --I;
206
207  while (I->isDebugValue()) {
208    if (I == MBB.begin())
209      return false;
210    --I;
211  }
212  if (!isUnpredicatedTerminator(I))
213    return false;
214
215  // Get the last instruction in the block.
216  MachineInstr *LastInst = I;
217
218  // If there is only one terminator instruction, process it.
219  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
220    if (LastInst->getOpcode() == Hexagon::JMP) {
221      TBB = LastInst->getOperand(0).getMBB();
222      return false;
223    }
224    if (LastInst->getOpcode() == Hexagon::JMP_c) {
225      // Block ends with fall-through true condbranch.
226      TBB = LastInst->getOperand(1).getMBB();
227      Cond.push_back(LastInst->getOperand(0));
228      return false;
229    }
230    if (LastInst->getOpcode() == Hexagon::JMP_cNot) {
231      // Block ends with fall-through false condbranch.
232      TBB = LastInst->getOperand(1).getMBB();
233      Cond.push_back(MachineOperand::CreateImm(0));
234      Cond.push_back(LastInst->getOperand(0));
235      return false;
236    }
237    // Otherwise, don't know what this is.
238    return true;
239  }
240
241  // Get the instruction before it if it's a terminator.
242  MachineInstr *SecondLastInst = I;
243
244  // If there are three terminators, we don't know what sort of block this is.
245  if (SecondLastInst && I != MBB.begin() &&
246      isUnpredicatedTerminator(--I))
247    return true;
248
249  // If the block ends with Hexagon::BRCOND and Hexagon:JMP, handle it.
250  if (((SecondLastInst->getOpcode() == Hexagon::BRCOND) ||
251      (SecondLastInst->getOpcode() == Hexagon::JMP_c)) &&
252      LastInst->getOpcode() == Hexagon::JMP) {
253    TBB =  SecondLastInst->getOperand(1).getMBB();
254    Cond.push_back(SecondLastInst->getOperand(0));
255    FBB = LastInst->getOperand(0).getMBB();
256    return false;
257  }
258
259  // If the block ends with Hexagon::JMP_cNot and Hexagon:JMP, handle it.
260  if ((SecondLastInst->getOpcode() == Hexagon::JMP_cNot) &&
261      LastInst->getOpcode() == Hexagon::JMP) {
262    TBB =  SecondLastInst->getOperand(1).getMBB();
263    Cond.push_back(MachineOperand::CreateImm(0));
264    Cond.push_back(SecondLastInst->getOperand(0));
265    FBB = LastInst->getOperand(0).getMBB();
266    return false;
267  }
268
269  // If the block ends with two Hexagon:JMPs, handle it.  The second one is not
270  // executed, so remove it.
271  if (SecondLastInst->getOpcode() == Hexagon::JMP &&
272      LastInst->getOpcode() == Hexagon::JMP) {
273    TBB = SecondLastInst->getOperand(0).getMBB();
274    I = LastInst;
275    if (AllowModify)
276      I->eraseFromParent();
277    return false;
278  }
279
280  // Otherwise, can't handle this.
281  return true;
282}
283
284
285unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
286  int BOpc   = Hexagon::JMP;
287  int BccOpc = Hexagon::JMP_c;
288  int BccOpcNot = Hexagon::JMP_cNot;
289
290  MachineBasicBlock::iterator I = MBB.end();
291  if (I == MBB.begin()) return 0;
292  --I;
293  if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
294      I->getOpcode() != BccOpcNot)
295    return 0;
296
297  // Remove the branch.
298  I->eraseFromParent();
299
300  I = MBB.end();
301
302  if (I == MBB.begin()) return 1;
303  --I;
304  if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
305    return 1;
306
307  // Remove the branch.
308  I->eraseFromParent();
309  return 2;
310}
311
312
313void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
314                                 MachineBasicBlock::iterator I, DebugLoc DL,
315                                 unsigned DestReg, unsigned SrcReg,
316                                 bool KillSrc) const {
317  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
318    BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
319    return;
320  }
321  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
322    BuildMI(MBB, I, DL, get(Hexagon::TFR_64), DestReg).addReg(SrcReg);
323    return;
324  }
325  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
326    // Map Pd = Ps to Pd = or(Ps, Ps).
327    BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
328            DestReg).addReg(SrcReg).addReg(SrcReg);
329    return;
330  }
331  if (Hexagon::DoubleRegsRegClass.contains(DestReg, SrcReg)) {
332    // We can have an overlap between single and double reg: r1:0 = r0.
333    if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
334        // r1:0 = r0
335        BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
336                Hexagon::subreg_hireg))).addImm(0);
337    } else {
338        // r1:0 = r1 or no overlap.
339        BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
340                Hexagon::subreg_loreg))).addReg(SrcReg);
341        BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
342                Hexagon::subreg_hireg))).addImm(0);
343    }
344    return;
345  }
346  if (Hexagon::CRRegsRegClass.contains(DestReg, SrcReg)) {
347    BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
348    return;
349  }
350
351  llvm_unreachable("Unimplemented");
352}
353
354
355void HexagonInstrInfo::
356storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
357                    unsigned SrcReg, bool isKill, int FI,
358                    const TargetRegisterClass *RC,
359                    const TargetRegisterInfo *TRI) const {
360
361  DebugLoc DL = MBB.findDebugLoc(I);
362  MachineFunction &MF = *MBB.getParent();
363  MachineFrameInfo &MFI = *MF.getFrameInfo();
364  unsigned Align = MFI.getObjectAlignment(FI);
365
366  MachineMemOperand *MMO =
367      MF.getMachineMemOperand(
368                      MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
369                      MachineMemOperand::MOStore,
370                      MFI.getObjectSize(FI),
371                      Align);
372
373  if (Hexagon::IntRegsRegisterClass->hasSubClassEq(RC)) {
374    BuildMI(MBB, I, DL, get(Hexagon::STriw))
375          .addFrameIndex(FI).addImm(0)
376          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
377  } else if (Hexagon::DoubleRegsRegisterClass->hasSubClassEq(RC)) {
378    BuildMI(MBB, I, DL, get(Hexagon::STrid))
379          .addFrameIndex(FI).addImm(0)
380          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
381  } else if (Hexagon::PredRegsRegisterClass->hasSubClassEq(RC)) {
382    BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
383          .addFrameIndex(FI).addImm(0)
384          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
385  } else {
386    llvm_unreachable("Unimplemented");
387  }
388}
389
390
391void HexagonInstrInfo::storeRegToAddr(
392                                 MachineFunction &MF, unsigned SrcReg,
393                                 bool isKill,
394                                 SmallVectorImpl<MachineOperand> &Addr,
395                                 const TargetRegisterClass *RC,
396                                 SmallVectorImpl<MachineInstr*> &NewMIs) const
397{
398  llvm_unreachable("Unimplemented");
399}
400
401
402void HexagonInstrInfo::
403loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
404                     unsigned DestReg, int FI,
405                     const TargetRegisterClass *RC,
406                     const TargetRegisterInfo *TRI) const {
407  DebugLoc DL = MBB.findDebugLoc(I);
408  MachineFunction &MF = *MBB.getParent();
409  MachineFrameInfo &MFI = *MF.getFrameInfo();
410  unsigned Align = MFI.getObjectAlignment(FI);
411
412  MachineMemOperand *MMO =
413      MF.getMachineMemOperand(
414                      MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
415                      MachineMemOperand::MOLoad,
416                      MFI.getObjectSize(FI),
417                      Align);
418
419  if (RC == Hexagon::IntRegsRegisterClass) {
420    BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
421          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
422  } else if (RC == Hexagon::DoubleRegsRegisterClass) {
423    BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
424          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
425  } else if (RC == Hexagon::PredRegsRegisterClass) {
426    BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
427          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
428  } else {
429    llvm_unreachable("Can't store this register to stack slot");
430  }
431}
432
433
434void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
435                                        SmallVectorImpl<MachineOperand> &Addr,
436                                        const TargetRegisterClass *RC,
437                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
438  llvm_unreachable("Unimplemented");
439}
440
441
442MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
443                                                    MachineInstr* MI,
444                                          const SmallVectorImpl<unsigned> &Ops,
445                                                    int FI) const {
446  // Hexagon_TODO: Implement.
447  return(0);
448}
449
450
451unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
452
453  MachineRegisterInfo &RegInfo = MF->getRegInfo();
454  const TargetRegisterClass *TRC;
455  if (VT == MVT::i1) {
456    TRC =  Hexagon::PredRegsRegisterClass;
457  } else if (VT == MVT::i32) {
458    TRC =  Hexagon::IntRegsRegisterClass;
459  } else if (VT == MVT::i64) {
460    TRC =  Hexagon::DoubleRegsRegisterClass;
461  } else {
462    llvm_unreachable("Cannot handle this register class");
463  }
464
465  unsigned NewReg = RegInfo.createVirtualRegister(TRC);
466  return NewReg;
467}
468
469bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
470  switch(MI->getOpcode()) {
471    // JMP_EQri
472    case Hexagon::JMP_EQriPt_nv_V4:
473    case Hexagon::JMP_EQriPnt_nv_V4:
474    case Hexagon::JMP_EQriNotPt_nv_V4:
475    case Hexagon::JMP_EQriNotPnt_nv_V4:
476
477    // JMP_EQri - with -1
478    case Hexagon::JMP_EQriPtneg_nv_V4:
479    case Hexagon::JMP_EQriPntneg_nv_V4:
480    case Hexagon::JMP_EQriNotPtneg_nv_V4:
481    case Hexagon::JMP_EQriNotPntneg_nv_V4:
482
483    // JMP_EQrr
484    case Hexagon::JMP_EQrrPt_nv_V4:
485    case Hexagon::JMP_EQrrPnt_nv_V4:
486    case Hexagon::JMP_EQrrNotPt_nv_V4:
487    case Hexagon::JMP_EQrrNotPnt_nv_V4:
488
489    // JMP_GTri
490    case Hexagon::JMP_GTriPt_nv_V4:
491    case Hexagon::JMP_GTriPnt_nv_V4:
492    case Hexagon::JMP_GTriNotPt_nv_V4:
493    case Hexagon::JMP_GTriNotPnt_nv_V4:
494
495    // JMP_GTri - with -1
496    case Hexagon::JMP_GTriPtneg_nv_V4:
497    case Hexagon::JMP_GTriPntneg_nv_V4:
498    case Hexagon::JMP_GTriNotPtneg_nv_V4:
499    case Hexagon::JMP_GTriNotPntneg_nv_V4:
500
501    // JMP_GTrr
502    case Hexagon::JMP_GTrrPt_nv_V4:
503    case Hexagon::JMP_GTrrPnt_nv_V4:
504    case Hexagon::JMP_GTrrNotPt_nv_V4:
505    case Hexagon::JMP_GTrrNotPnt_nv_V4:
506
507    // JMP_GTrrdn
508    case Hexagon::JMP_GTrrdnPt_nv_V4:
509    case Hexagon::JMP_GTrrdnPnt_nv_V4:
510    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
511    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
512
513    // JMP_GTUri
514    case Hexagon::JMP_GTUriPt_nv_V4:
515    case Hexagon::JMP_GTUriPnt_nv_V4:
516    case Hexagon::JMP_GTUriNotPt_nv_V4:
517    case Hexagon::JMP_GTUriNotPnt_nv_V4:
518
519    // JMP_GTUrr
520    case Hexagon::JMP_GTUrrPt_nv_V4:
521    case Hexagon::JMP_GTUrrPnt_nv_V4:
522    case Hexagon::JMP_GTUrrNotPt_nv_V4:
523    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
524
525    // JMP_GTUrrdn
526    case Hexagon::JMP_GTUrrdnPt_nv_V4:
527    case Hexagon::JMP_GTUrrdnPnt_nv_V4:
528    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
529    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
530      return true;
531
532    // TFR_FI
533    case Hexagon::TFR_FI:
534      return true;
535
536
537    default:
538      return false;
539  }
540  return  false;
541}
542
543bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
544  switch(MI->getOpcode()) {
545    // JMP_EQri
546    case Hexagon::JMP_EQriPt_ie_nv_V4:
547    case Hexagon::JMP_EQriPnt_ie_nv_V4:
548    case Hexagon::JMP_EQriNotPt_ie_nv_V4:
549    case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
550
551    // JMP_EQri - with -1
552    case Hexagon::JMP_EQriPtneg_ie_nv_V4:
553    case Hexagon::JMP_EQriPntneg_ie_nv_V4:
554    case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
555    case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
556
557    // JMP_EQrr
558    case Hexagon::JMP_EQrrPt_ie_nv_V4:
559    case Hexagon::JMP_EQrrPnt_ie_nv_V4:
560    case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
561    case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
562
563    // JMP_GTri
564    case Hexagon::JMP_GTriPt_ie_nv_V4:
565    case Hexagon::JMP_GTriPnt_ie_nv_V4:
566    case Hexagon::JMP_GTriNotPt_ie_nv_V4:
567    case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
568
569    // JMP_GTri - with -1
570    case Hexagon::JMP_GTriPtneg_ie_nv_V4:
571    case Hexagon::JMP_GTriPntneg_ie_nv_V4:
572    case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
573    case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
574
575    // JMP_GTrr
576    case Hexagon::JMP_GTrrPt_ie_nv_V4:
577    case Hexagon::JMP_GTrrPnt_ie_nv_V4:
578    case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
579    case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
580
581    // JMP_GTrrdn
582    case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
583    case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
584    case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
585    case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
586
587    // JMP_GTUri
588    case Hexagon::JMP_GTUriPt_ie_nv_V4:
589    case Hexagon::JMP_GTUriPnt_ie_nv_V4:
590    case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
591    case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
592
593    // JMP_GTUrr
594    case Hexagon::JMP_GTUrrPt_ie_nv_V4:
595    case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
596    case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
597    case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
598
599    // JMP_GTUrrdn
600    case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
601    case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
602    case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
603    case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
604
605    // V4 absolute set addressing.
606    case Hexagon::LDrid_abs_setimm_V4:
607    case Hexagon::LDriw_abs_setimm_V4:
608    case Hexagon::LDrih_abs_setimm_V4:
609    case Hexagon::LDrib_abs_setimm_V4:
610    case Hexagon::LDriuh_abs_setimm_V4:
611    case Hexagon::LDriub_abs_setimm_V4:
612
613    case Hexagon::STrid_abs_setimm_V4:
614    case Hexagon::STrib_abs_setimm_V4:
615    case Hexagon::STrih_abs_setimm_V4:
616    case Hexagon::STriw_abs_setimm_V4:
617
618    // V4 global address load.
619    case Hexagon::LDrid_GP_cPt_V4 :
620    case Hexagon::LDrid_GP_cNotPt_V4 :
621    case Hexagon::LDrid_GP_cdnPt_V4 :
622    case Hexagon::LDrid_GP_cdnNotPt_V4 :
623    case Hexagon::LDrib_GP_cPt_V4 :
624    case Hexagon::LDrib_GP_cNotPt_V4 :
625    case Hexagon::LDrib_GP_cdnPt_V4 :
626    case Hexagon::LDrib_GP_cdnNotPt_V4 :
627    case Hexagon::LDriub_GP_cPt_V4 :
628    case Hexagon::LDriub_GP_cNotPt_V4 :
629    case Hexagon::LDriub_GP_cdnPt_V4 :
630    case Hexagon::LDriub_GP_cdnNotPt_V4 :
631    case Hexagon::LDrih_GP_cPt_V4 :
632    case Hexagon::LDrih_GP_cNotPt_V4 :
633    case Hexagon::LDrih_GP_cdnPt_V4 :
634    case Hexagon::LDrih_GP_cdnNotPt_V4 :
635    case Hexagon::LDriuh_GP_cPt_V4 :
636    case Hexagon::LDriuh_GP_cNotPt_V4 :
637    case Hexagon::LDriuh_GP_cdnPt_V4 :
638    case Hexagon::LDriuh_GP_cdnNotPt_V4 :
639    case Hexagon::LDriw_GP_cPt_V4 :
640    case Hexagon::LDriw_GP_cNotPt_V4 :
641    case Hexagon::LDriw_GP_cdnPt_V4 :
642    case Hexagon::LDriw_GP_cdnNotPt_V4 :
643    case Hexagon::LDd_GP_cPt_V4 :
644    case Hexagon::LDd_GP_cNotPt_V4 :
645    case Hexagon::LDd_GP_cdnPt_V4 :
646    case Hexagon::LDd_GP_cdnNotPt_V4 :
647    case Hexagon::LDb_GP_cPt_V4 :
648    case Hexagon::LDb_GP_cNotPt_V4 :
649    case Hexagon::LDb_GP_cdnPt_V4 :
650    case Hexagon::LDb_GP_cdnNotPt_V4 :
651    case Hexagon::LDub_GP_cPt_V4 :
652    case Hexagon::LDub_GP_cNotPt_V4 :
653    case Hexagon::LDub_GP_cdnPt_V4 :
654    case Hexagon::LDub_GP_cdnNotPt_V4 :
655    case Hexagon::LDh_GP_cPt_V4 :
656    case Hexagon::LDh_GP_cNotPt_V4 :
657    case Hexagon::LDh_GP_cdnPt_V4 :
658    case Hexagon::LDh_GP_cdnNotPt_V4 :
659    case Hexagon::LDuh_GP_cPt_V4 :
660    case Hexagon::LDuh_GP_cNotPt_V4 :
661    case Hexagon::LDuh_GP_cdnPt_V4 :
662    case Hexagon::LDuh_GP_cdnNotPt_V4 :
663    case Hexagon::LDw_GP_cPt_V4 :
664    case Hexagon::LDw_GP_cNotPt_V4 :
665    case Hexagon::LDw_GP_cdnPt_V4 :
666    case Hexagon::LDw_GP_cdnNotPt_V4 :
667
668    // V4 global address store.
669    case Hexagon::STrid_GP_cPt_V4 :
670    case Hexagon::STrid_GP_cNotPt_V4 :
671    case Hexagon::STrid_GP_cdnPt_V4 :
672    case Hexagon::STrid_GP_cdnNotPt_V4 :
673    case Hexagon::STrib_GP_cPt_V4 :
674    case Hexagon::STrib_GP_cNotPt_V4 :
675    case Hexagon::STrib_GP_cdnPt_V4 :
676    case Hexagon::STrib_GP_cdnNotPt_V4 :
677    case Hexagon::STrih_GP_cPt_V4 :
678    case Hexagon::STrih_GP_cNotPt_V4 :
679    case Hexagon::STrih_GP_cdnPt_V4 :
680    case Hexagon::STrih_GP_cdnNotPt_V4 :
681    case Hexagon::STriw_GP_cPt_V4 :
682    case Hexagon::STriw_GP_cNotPt_V4 :
683    case Hexagon::STriw_GP_cdnPt_V4 :
684    case Hexagon::STriw_GP_cdnNotPt_V4 :
685    case Hexagon::STd_GP_cPt_V4 :
686    case Hexagon::STd_GP_cNotPt_V4 :
687    case Hexagon::STd_GP_cdnPt_V4 :
688    case Hexagon::STd_GP_cdnNotPt_V4 :
689    case Hexagon::STb_GP_cPt_V4 :
690    case Hexagon::STb_GP_cNotPt_V4 :
691    case Hexagon::STb_GP_cdnPt_V4 :
692    case Hexagon::STb_GP_cdnNotPt_V4 :
693    case Hexagon::STh_GP_cPt_V4 :
694    case Hexagon::STh_GP_cNotPt_V4 :
695    case Hexagon::STh_GP_cdnPt_V4 :
696    case Hexagon::STh_GP_cdnNotPt_V4 :
697    case Hexagon::STw_GP_cPt_V4 :
698    case Hexagon::STw_GP_cNotPt_V4 :
699    case Hexagon::STw_GP_cdnPt_V4 :
700    case Hexagon::STw_GP_cdnNotPt_V4 :
701
702    // V4 predicated global address new value store.
703    case Hexagon::STrib_GP_cPt_nv_V4 :
704    case Hexagon::STrib_GP_cNotPt_nv_V4 :
705    case Hexagon::STrib_GP_cdnPt_nv_V4 :
706    case Hexagon::STrib_GP_cdnNotPt_nv_V4 :
707    case Hexagon::STrih_GP_cPt_nv_V4 :
708    case Hexagon::STrih_GP_cNotPt_nv_V4 :
709    case Hexagon::STrih_GP_cdnPt_nv_V4 :
710    case Hexagon::STrih_GP_cdnNotPt_nv_V4 :
711    case Hexagon::STriw_GP_cPt_nv_V4 :
712    case Hexagon::STriw_GP_cNotPt_nv_V4 :
713    case Hexagon::STriw_GP_cdnPt_nv_V4 :
714    case Hexagon::STriw_GP_cdnNotPt_nv_V4 :
715    case Hexagon::STb_GP_cPt_nv_V4 :
716    case Hexagon::STb_GP_cNotPt_nv_V4 :
717    case Hexagon::STb_GP_cdnPt_nv_V4 :
718    case Hexagon::STb_GP_cdnNotPt_nv_V4 :
719    case Hexagon::STh_GP_cPt_nv_V4 :
720    case Hexagon::STh_GP_cNotPt_nv_V4 :
721    case Hexagon::STh_GP_cdnPt_nv_V4 :
722    case Hexagon::STh_GP_cdnNotPt_nv_V4 :
723    case Hexagon::STw_GP_cPt_nv_V4 :
724    case Hexagon::STw_GP_cNotPt_nv_V4 :
725    case Hexagon::STw_GP_cdnPt_nv_V4 :
726    case Hexagon::STw_GP_cdnNotPt_nv_V4 :
727
728    // TFR_FI
729    case Hexagon::TFR_FI_immext_V4:
730      return true;
731
732    default:
733      return false;
734  }
735  return  false;
736}
737
738bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
739  switch (MI->getOpcode()) {
740    // JMP_EQri
741    case Hexagon::JMP_EQriPt_nv_V4:
742    case Hexagon::JMP_EQriPnt_nv_V4:
743    case Hexagon::JMP_EQriNotPt_nv_V4:
744    case Hexagon::JMP_EQriNotPnt_nv_V4:
745    case Hexagon::JMP_EQriPt_ie_nv_V4:
746    case Hexagon::JMP_EQriPnt_ie_nv_V4:
747    case Hexagon::JMP_EQriNotPt_ie_nv_V4:
748    case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
749
750    // JMP_EQri - with -1
751    case Hexagon::JMP_EQriPtneg_nv_V4:
752    case Hexagon::JMP_EQriPntneg_nv_V4:
753    case Hexagon::JMP_EQriNotPtneg_nv_V4:
754    case Hexagon::JMP_EQriNotPntneg_nv_V4:
755    case Hexagon::JMP_EQriPtneg_ie_nv_V4:
756    case Hexagon::JMP_EQriPntneg_ie_nv_V4:
757    case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
758    case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
759
760    // JMP_EQrr
761    case Hexagon::JMP_EQrrPt_nv_V4:
762    case Hexagon::JMP_EQrrPnt_nv_V4:
763    case Hexagon::JMP_EQrrNotPt_nv_V4:
764    case Hexagon::JMP_EQrrNotPnt_nv_V4:
765    case Hexagon::JMP_EQrrPt_ie_nv_V4:
766    case Hexagon::JMP_EQrrPnt_ie_nv_V4:
767    case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
768    case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
769
770    // JMP_GTri
771    case Hexagon::JMP_GTriPt_nv_V4:
772    case Hexagon::JMP_GTriPnt_nv_V4:
773    case Hexagon::JMP_GTriNotPt_nv_V4:
774    case Hexagon::JMP_GTriNotPnt_nv_V4:
775    case Hexagon::JMP_GTriPt_ie_nv_V4:
776    case Hexagon::JMP_GTriPnt_ie_nv_V4:
777    case Hexagon::JMP_GTriNotPt_ie_nv_V4:
778    case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
779
780    // JMP_GTri - with -1
781    case Hexagon::JMP_GTriPtneg_nv_V4:
782    case Hexagon::JMP_GTriPntneg_nv_V4:
783    case Hexagon::JMP_GTriNotPtneg_nv_V4:
784    case Hexagon::JMP_GTriNotPntneg_nv_V4:
785    case Hexagon::JMP_GTriPtneg_ie_nv_V4:
786    case Hexagon::JMP_GTriPntneg_ie_nv_V4:
787    case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
788    case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
789
790    // JMP_GTrr
791    case Hexagon::JMP_GTrrPt_nv_V4:
792    case Hexagon::JMP_GTrrPnt_nv_V4:
793    case Hexagon::JMP_GTrrNotPt_nv_V4:
794    case Hexagon::JMP_GTrrNotPnt_nv_V4:
795    case Hexagon::JMP_GTrrPt_ie_nv_V4:
796    case Hexagon::JMP_GTrrPnt_ie_nv_V4:
797    case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
798    case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
799
800    // JMP_GTrrdn
801    case Hexagon::JMP_GTrrdnPt_nv_V4:
802    case Hexagon::JMP_GTrrdnPnt_nv_V4:
803    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
804    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
805    case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
806    case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
807    case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
808    case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
809
810    // JMP_GTUri
811    case Hexagon::JMP_GTUriPt_nv_V4:
812    case Hexagon::JMP_GTUriPnt_nv_V4:
813    case Hexagon::JMP_GTUriNotPt_nv_V4:
814    case Hexagon::JMP_GTUriNotPnt_nv_V4:
815    case Hexagon::JMP_GTUriPt_ie_nv_V4:
816    case Hexagon::JMP_GTUriPnt_ie_nv_V4:
817    case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
818    case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
819
820    // JMP_GTUrr
821    case Hexagon::JMP_GTUrrPt_nv_V4:
822    case Hexagon::JMP_GTUrrPnt_nv_V4:
823    case Hexagon::JMP_GTUrrNotPt_nv_V4:
824    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
825    case Hexagon::JMP_GTUrrPt_ie_nv_V4:
826    case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
827    case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
828    case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
829
830    // JMP_GTUrrdn
831    case Hexagon::JMP_GTUrrdnPt_nv_V4:
832    case Hexagon::JMP_GTUrrdnPnt_nv_V4:
833    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
834    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
835    case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
836    case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
837    case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
838    case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
839      return true;
840
841    default:
842      return false;
843  }
844  return false;
845}
846
847unsigned HexagonInstrInfo::getImmExtForm(const MachineInstr* MI) const {
848  switch(MI->getOpcode()) {
849  default: llvm_unreachable("Unknown type of instruction");
850
851  // JMP_EQri
852  case Hexagon::JMP_EQriPt_nv_V4:
853    return Hexagon::JMP_EQriPt_ie_nv_V4;
854  case Hexagon::JMP_EQriNotPt_nv_V4:
855    return Hexagon::JMP_EQriNotPt_ie_nv_V4;
856  case Hexagon::JMP_EQriPnt_nv_V4:
857    return Hexagon::JMP_EQriPnt_ie_nv_V4;
858  case Hexagon::JMP_EQriNotPnt_nv_V4:
859    return Hexagon::JMP_EQriNotPnt_ie_nv_V4;
860
861  // JMP_EQri -- with -1
862  case Hexagon::JMP_EQriPtneg_nv_V4:
863    return Hexagon::JMP_EQriPtneg_ie_nv_V4;
864  case Hexagon::JMP_EQriNotPtneg_nv_V4:
865    return Hexagon::JMP_EQriNotPtneg_ie_nv_V4;
866  case Hexagon::JMP_EQriPntneg_nv_V4:
867    return Hexagon::JMP_EQriPntneg_ie_nv_V4;
868  case Hexagon::JMP_EQriNotPntneg_nv_V4:
869    return Hexagon::JMP_EQriNotPntneg_ie_nv_V4;
870
871  // JMP_EQrr
872  case Hexagon::JMP_EQrrPt_nv_V4:
873    return Hexagon::JMP_EQrrPt_ie_nv_V4;
874  case Hexagon::JMP_EQrrNotPt_nv_V4:
875    return Hexagon::JMP_EQrrNotPt_ie_nv_V4;
876  case Hexagon::JMP_EQrrPnt_nv_V4:
877    return Hexagon::JMP_EQrrPnt_ie_nv_V4;
878  case Hexagon::JMP_EQrrNotPnt_nv_V4:
879    return Hexagon::JMP_EQrrNotPnt_ie_nv_V4;
880
881  // JMP_GTri
882  case Hexagon::JMP_GTriPt_nv_V4:
883    return Hexagon::JMP_GTriPt_ie_nv_V4;
884  case Hexagon::JMP_GTriNotPt_nv_V4:
885    return Hexagon::JMP_GTriNotPt_ie_nv_V4;
886  case Hexagon::JMP_GTriPnt_nv_V4:
887    return Hexagon::JMP_GTriPnt_ie_nv_V4;
888  case Hexagon::JMP_GTriNotPnt_nv_V4:
889    return Hexagon::JMP_GTriNotPnt_ie_nv_V4;
890
891  // JMP_GTri -- with -1
892  case Hexagon::JMP_GTriPtneg_nv_V4:
893    return Hexagon::JMP_GTriPtneg_ie_nv_V4;
894  case Hexagon::JMP_GTriNotPtneg_nv_V4:
895    return Hexagon::JMP_GTriNotPtneg_ie_nv_V4;
896  case Hexagon::JMP_GTriPntneg_nv_V4:
897    return Hexagon::JMP_GTriPntneg_ie_nv_V4;
898  case Hexagon::JMP_GTriNotPntneg_nv_V4:
899    return Hexagon::JMP_GTriNotPntneg_ie_nv_V4;
900
901  // JMP_GTrr
902  case Hexagon::JMP_GTrrPt_nv_V4:
903    return Hexagon::JMP_GTrrPt_ie_nv_V4;
904  case Hexagon::JMP_GTrrNotPt_nv_V4:
905    return Hexagon::JMP_GTrrNotPt_ie_nv_V4;
906  case Hexagon::JMP_GTrrPnt_nv_V4:
907    return Hexagon::JMP_GTrrPnt_ie_nv_V4;
908  case Hexagon::JMP_GTrrNotPnt_nv_V4:
909    return Hexagon::JMP_GTrrNotPnt_ie_nv_V4;
910
911  // JMP_GTrrdn
912  case Hexagon::JMP_GTrrdnPt_nv_V4:
913    return Hexagon::JMP_GTrrdnPt_ie_nv_V4;
914  case Hexagon::JMP_GTrrdnNotPt_nv_V4:
915    return Hexagon::JMP_GTrrdnNotPt_ie_nv_V4;
916  case Hexagon::JMP_GTrrdnPnt_nv_V4:
917    return Hexagon::JMP_GTrrdnPnt_ie_nv_V4;
918  case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
919    return Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4;
920
921  // JMP_GTUri
922  case Hexagon::JMP_GTUriPt_nv_V4:
923    return Hexagon::JMP_GTUriPt_ie_nv_V4;
924  case Hexagon::JMP_GTUriNotPt_nv_V4:
925    return Hexagon::JMP_GTUriNotPt_ie_nv_V4;
926  case Hexagon::JMP_GTUriPnt_nv_V4:
927    return Hexagon::JMP_GTUriPnt_ie_nv_V4;
928  case Hexagon::JMP_GTUriNotPnt_nv_V4:
929    return Hexagon::JMP_GTUriNotPnt_ie_nv_V4;
930
931  // JMP_GTUrr
932  case Hexagon::JMP_GTUrrPt_nv_V4:
933    return Hexagon::JMP_GTUrrPt_ie_nv_V4;
934  case Hexagon::JMP_GTUrrNotPt_nv_V4:
935    return Hexagon::JMP_GTUrrNotPt_ie_nv_V4;
936  case Hexagon::JMP_GTUrrPnt_nv_V4:
937    return Hexagon::JMP_GTUrrPnt_ie_nv_V4;
938  case Hexagon::JMP_GTUrrNotPnt_nv_V4:
939    return Hexagon::JMP_GTUrrNotPnt_ie_nv_V4;
940
941  // JMP_GTUrrdn
942  case Hexagon::JMP_GTUrrdnPt_nv_V4:
943    return Hexagon::JMP_GTUrrdnPt_ie_nv_V4;
944  case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
945    return Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4;
946  case Hexagon::JMP_GTUrrdnPnt_nv_V4:
947    return Hexagon::JMP_GTUrrdnPnt_ie_nv_V4;
948  case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
949    return Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4;
950
951  case Hexagon::TFR_FI:
952      return Hexagon::TFR_FI_immext_V4;
953
954  case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
955  case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
956  case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
957  case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
958  case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
959  case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
960  case Hexagon::MEMw_ORr_indexed_MEM_V4 :
961  case Hexagon::MEMw_ADDSUBi_MEM_V4 :
962  case Hexagon::MEMw_ADDi_MEM_V4 :
963  case Hexagon::MEMw_SUBi_MEM_V4 :
964  case Hexagon::MEMw_ADDr_MEM_V4 :
965  case Hexagon::MEMw_SUBr_MEM_V4 :
966  case Hexagon::MEMw_ANDr_MEM_V4 :
967  case Hexagon::MEMw_ORr_MEM_V4 :
968  case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
969  case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
970  case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
971  case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
972  case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
973  case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
974  case Hexagon::MEMh_ORr_indexed_MEM_V4 :
975  case Hexagon::MEMh_ADDSUBi_MEM_V4 :
976  case Hexagon::MEMh_ADDi_MEM_V4 :
977  case Hexagon::MEMh_SUBi_MEM_V4 :
978  case Hexagon::MEMh_ADDr_MEM_V4 :
979  case Hexagon::MEMh_SUBr_MEM_V4 :
980  case Hexagon::MEMh_ANDr_MEM_V4 :
981  case Hexagon::MEMh_ORr_MEM_V4 :
982  case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
983  case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
984  case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
985  case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
986  case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
987  case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
988  case Hexagon::MEMb_ORr_indexed_MEM_V4 :
989  case Hexagon::MEMb_ADDSUBi_MEM_V4 :
990  case Hexagon::MEMb_ADDi_MEM_V4 :
991  case Hexagon::MEMb_SUBi_MEM_V4 :
992  case Hexagon::MEMb_ADDr_MEM_V4 :
993  case Hexagon::MEMb_SUBr_MEM_V4 :
994  case Hexagon::MEMb_ANDr_MEM_V4 :
995  case Hexagon::MEMb_ORr_MEM_V4 :
996    llvm_unreachable("Needs implementing");
997  }
998}
999
1000unsigned HexagonInstrInfo::getNormalBranchForm(const MachineInstr* MI) const {
1001  switch(MI->getOpcode()) {
1002  default: llvm_unreachable("Unknown type of jump instruction");
1003
1004  // JMP_EQri
1005  case Hexagon::JMP_EQriPt_ie_nv_V4:
1006    return Hexagon::JMP_EQriPt_nv_V4;
1007  case Hexagon::JMP_EQriNotPt_ie_nv_V4:
1008    return Hexagon::JMP_EQriNotPt_nv_V4;
1009  case Hexagon::JMP_EQriPnt_ie_nv_V4:
1010    return Hexagon::JMP_EQriPnt_nv_V4;
1011  case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
1012    return Hexagon::JMP_EQriNotPnt_nv_V4;
1013
1014  // JMP_EQri -- with -1
1015  case Hexagon::JMP_EQriPtneg_ie_nv_V4:
1016    return Hexagon::JMP_EQriPtneg_nv_V4;
1017  case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
1018    return Hexagon::JMP_EQriNotPtneg_nv_V4;
1019  case Hexagon::JMP_EQriPntneg_ie_nv_V4:
1020    return Hexagon::JMP_EQriPntneg_nv_V4;
1021  case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
1022    return Hexagon::JMP_EQriNotPntneg_nv_V4;
1023
1024  // JMP_EQrr
1025  case Hexagon::JMP_EQrrPt_ie_nv_V4:
1026    return Hexagon::JMP_EQrrPt_nv_V4;
1027  case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
1028    return Hexagon::JMP_EQrrNotPt_nv_V4;
1029  case Hexagon::JMP_EQrrPnt_ie_nv_V4:
1030    return Hexagon::JMP_EQrrPnt_nv_V4;
1031  case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
1032    return Hexagon::JMP_EQrrNotPnt_nv_V4;
1033
1034  // JMP_GTri
1035  case Hexagon::JMP_GTriPt_ie_nv_V4:
1036    return Hexagon::JMP_GTriPt_nv_V4;
1037  case Hexagon::JMP_GTriNotPt_ie_nv_V4:
1038    return Hexagon::JMP_GTriNotPt_nv_V4;
1039  case Hexagon::JMP_GTriPnt_ie_nv_V4:
1040    return Hexagon::JMP_GTriPnt_nv_V4;
1041  case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
1042    return Hexagon::JMP_GTriNotPnt_nv_V4;
1043
1044  // JMP_GTri -- with -1
1045  case Hexagon::JMP_GTriPtneg_ie_nv_V4:
1046    return Hexagon::JMP_GTriPtneg_nv_V4;
1047  case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
1048    return Hexagon::JMP_GTriNotPtneg_nv_V4;
1049  case Hexagon::JMP_GTriPntneg_ie_nv_V4:
1050    return Hexagon::JMP_GTriPntneg_nv_V4;
1051  case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
1052    return Hexagon::JMP_GTriNotPntneg_nv_V4;
1053
1054  // JMP_GTrr
1055  case Hexagon::JMP_GTrrPt_ie_nv_V4:
1056    return Hexagon::JMP_GTrrPt_nv_V4;
1057  case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
1058    return Hexagon::JMP_GTrrNotPt_nv_V4;
1059  case Hexagon::JMP_GTrrPnt_ie_nv_V4:
1060    return Hexagon::JMP_GTrrPnt_nv_V4;
1061  case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
1062    return Hexagon::JMP_GTrrNotPnt_nv_V4;
1063
1064  // JMP_GTrrdn
1065  case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
1066    return Hexagon::JMP_GTrrdnPt_nv_V4;
1067  case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
1068    return Hexagon::JMP_GTrrdnNotPt_nv_V4;
1069  case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
1070    return Hexagon::JMP_GTrrdnPnt_nv_V4;
1071  case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
1072    return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
1073
1074  // JMP_GTUri
1075  case Hexagon::JMP_GTUriPt_ie_nv_V4:
1076    return Hexagon::JMP_GTUriPt_nv_V4;
1077  case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
1078    return Hexagon::JMP_GTUriNotPt_nv_V4;
1079  case Hexagon::JMP_GTUriPnt_ie_nv_V4:
1080    return Hexagon::JMP_GTUriPnt_nv_V4;
1081  case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
1082    return Hexagon::JMP_GTUriNotPnt_nv_V4;
1083
1084  // JMP_GTUrr
1085  case Hexagon::JMP_GTUrrPt_ie_nv_V4:
1086    return Hexagon::JMP_GTUrrPt_nv_V4;
1087  case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
1088    return Hexagon::JMP_GTUrrNotPt_nv_V4;
1089  case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
1090    return Hexagon::JMP_GTUrrPnt_nv_V4;
1091  case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
1092    return Hexagon::JMP_GTUrrNotPnt_nv_V4;
1093
1094  // JMP_GTUrrdn
1095  case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
1096    return Hexagon::JMP_GTUrrdnPt_nv_V4;
1097  case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
1098    return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
1099  case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
1100    return Hexagon::JMP_GTUrrdnPnt_nv_V4;
1101  case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
1102    return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
1103  }
1104}
1105
1106
1107bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
1108  switch (MI->getOpcode()) {
1109
1110    // Store Byte
1111    case Hexagon::STrib_nv_V4:
1112    case Hexagon::STrib_indexed_nv_V4:
1113    case Hexagon::STrib_indexed_shl_nv_V4:
1114    case Hexagon::STrib_shl_nv_V4:
1115    case Hexagon::STrib_GP_nv_V4:
1116    case Hexagon::STb_GP_nv_V4:
1117    case Hexagon::POST_STbri_nv_V4:
1118    case Hexagon::STrib_cPt_nv_V4:
1119    case Hexagon::STrib_cdnPt_nv_V4:
1120    case Hexagon::STrib_cNotPt_nv_V4:
1121    case Hexagon::STrib_cdnNotPt_nv_V4:
1122    case Hexagon::STrib_indexed_cPt_nv_V4:
1123    case Hexagon::STrib_indexed_cdnPt_nv_V4:
1124    case Hexagon::STrib_indexed_cNotPt_nv_V4:
1125    case Hexagon::STrib_indexed_cdnNotPt_nv_V4:
1126    case Hexagon::STrib_indexed_shl_cPt_nv_V4:
1127    case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
1128    case Hexagon::STrib_indexed_shl_cNotPt_nv_V4:
1129    case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
1130    case Hexagon::POST_STbri_cPt_nv_V4:
1131    case Hexagon::POST_STbri_cdnPt_nv_V4:
1132    case Hexagon::POST_STbri_cNotPt_nv_V4:
1133    case Hexagon::POST_STbri_cdnNotPt_nv_V4:
1134    case Hexagon::STb_GP_cPt_nv_V4:
1135    case Hexagon::STb_GP_cNotPt_nv_V4:
1136    case Hexagon::STb_GP_cdnPt_nv_V4:
1137    case Hexagon::STb_GP_cdnNotPt_nv_V4:
1138    case Hexagon::STrib_GP_cPt_nv_V4:
1139    case Hexagon::STrib_GP_cNotPt_nv_V4:
1140    case Hexagon::STrib_GP_cdnPt_nv_V4:
1141    case Hexagon::STrib_GP_cdnNotPt_nv_V4:
1142    case Hexagon::STrib_abs_nv_V4:
1143    case Hexagon::STrib_abs_cPt_nv_V4:
1144    case Hexagon::STrib_abs_cdnPt_nv_V4:
1145    case Hexagon::STrib_abs_cNotPt_nv_V4:
1146    case Hexagon::STrib_abs_cdnNotPt_nv_V4:
1147    case Hexagon::STrib_imm_abs_nv_V4:
1148    case Hexagon::STrib_imm_abs_cPt_nv_V4:
1149    case Hexagon::STrib_imm_abs_cdnPt_nv_V4:
1150    case Hexagon::STrib_imm_abs_cNotPt_nv_V4:
1151    case Hexagon::STrib_imm_abs_cdnNotPt_nv_V4:
1152
1153    // Store Halfword
1154    case Hexagon::STrih_nv_V4:
1155    case Hexagon::STrih_indexed_nv_V4:
1156    case Hexagon::STrih_indexed_shl_nv_V4:
1157    case Hexagon::STrih_shl_nv_V4:
1158    case Hexagon::STrih_GP_nv_V4:
1159    case Hexagon::STh_GP_nv_V4:
1160    case Hexagon::POST_SThri_nv_V4:
1161    case Hexagon::STrih_cPt_nv_V4:
1162    case Hexagon::STrih_cdnPt_nv_V4:
1163    case Hexagon::STrih_cNotPt_nv_V4:
1164    case Hexagon::STrih_cdnNotPt_nv_V4:
1165    case Hexagon::STrih_indexed_cPt_nv_V4:
1166    case Hexagon::STrih_indexed_cdnPt_nv_V4:
1167    case Hexagon::STrih_indexed_cNotPt_nv_V4:
1168    case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
1169    case Hexagon::STrih_indexed_shl_cPt_nv_V4:
1170    case Hexagon::STrih_indexed_shl_cdnPt_nv_V4:
1171    case Hexagon::STrih_indexed_shl_cNotPt_nv_V4:
1172    case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4:
1173    case Hexagon::POST_SThri_cPt_nv_V4:
1174    case Hexagon::POST_SThri_cdnPt_nv_V4:
1175    case Hexagon::POST_SThri_cNotPt_nv_V4:
1176    case Hexagon::POST_SThri_cdnNotPt_nv_V4:
1177    case Hexagon::STh_GP_cPt_nv_V4:
1178    case Hexagon::STh_GP_cNotPt_nv_V4:
1179    case Hexagon::STh_GP_cdnPt_nv_V4:
1180    case Hexagon::STh_GP_cdnNotPt_nv_V4:
1181    case Hexagon::STrih_GP_cPt_nv_V4:
1182    case Hexagon::STrih_GP_cNotPt_nv_V4:
1183    case Hexagon::STrih_GP_cdnPt_nv_V4:
1184    case Hexagon::STrih_GP_cdnNotPt_nv_V4:
1185    case Hexagon::STrih_abs_nv_V4:
1186    case Hexagon::STrih_abs_cPt_nv_V4:
1187    case Hexagon::STrih_abs_cdnPt_nv_V4:
1188    case Hexagon::STrih_abs_cNotPt_nv_V4:
1189    case Hexagon::STrih_abs_cdnNotPt_nv_V4:
1190    case Hexagon::STrih_imm_abs_nv_V4:
1191    case Hexagon::STrih_imm_abs_cPt_nv_V4:
1192    case Hexagon::STrih_imm_abs_cdnPt_nv_V4:
1193    case Hexagon::STrih_imm_abs_cNotPt_nv_V4:
1194    case Hexagon::STrih_imm_abs_cdnNotPt_nv_V4:
1195
1196    // Store Word
1197    case Hexagon::STriw_nv_V4:
1198    case Hexagon::STriw_indexed_nv_V4:
1199    case Hexagon::STriw_indexed_shl_nv_V4:
1200    case Hexagon::STriw_shl_nv_V4:
1201    case Hexagon::STriw_GP_nv_V4:
1202    case Hexagon::STw_GP_nv_V4:
1203    case Hexagon::POST_STwri_nv_V4:
1204    case Hexagon::STriw_cPt_nv_V4:
1205    case Hexagon::STriw_cdnPt_nv_V4:
1206    case Hexagon::STriw_cNotPt_nv_V4:
1207    case Hexagon::STriw_cdnNotPt_nv_V4:
1208    case Hexagon::STriw_indexed_cPt_nv_V4:
1209    case Hexagon::STriw_indexed_cdnPt_nv_V4:
1210    case Hexagon::STriw_indexed_cNotPt_nv_V4:
1211    case Hexagon::STriw_indexed_cdnNotPt_nv_V4:
1212    case Hexagon::STriw_indexed_shl_cPt_nv_V4:
1213    case Hexagon::STriw_indexed_shl_cdnPt_nv_V4:
1214    case Hexagon::STriw_indexed_shl_cNotPt_nv_V4:
1215    case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4:
1216    case Hexagon::POST_STwri_cPt_nv_V4:
1217    case Hexagon::POST_STwri_cdnPt_nv_V4:
1218    case Hexagon::POST_STwri_cNotPt_nv_V4:
1219    case Hexagon::POST_STwri_cdnNotPt_nv_V4:
1220    case Hexagon::STw_GP_cPt_nv_V4:
1221    case Hexagon::STw_GP_cNotPt_nv_V4:
1222    case Hexagon::STw_GP_cdnPt_nv_V4:
1223    case Hexagon::STw_GP_cdnNotPt_nv_V4:
1224    case Hexagon::STriw_GP_cPt_nv_V4:
1225    case Hexagon::STriw_GP_cNotPt_nv_V4:
1226    case Hexagon::STriw_GP_cdnPt_nv_V4:
1227    case Hexagon::STriw_GP_cdnNotPt_nv_V4:
1228    case Hexagon::STriw_abs_nv_V4:
1229    case Hexagon::STriw_abs_cPt_nv_V4:
1230    case Hexagon::STriw_abs_cdnPt_nv_V4:
1231    case Hexagon::STriw_abs_cNotPt_nv_V4:
1232    case Hexagon::STriw_abs_cdnNotPt_nv_V4:
1233    case Hexagon::STriw_imm_abs_nv_V4:
1234    case Hexagon::STriw_imm_abs_cPt_nv_V4:
1235    case Hexagon::STriw_imm_abs_cdnPt_nv_V4:
1236    case Hexagon::STriw_imm_abs_cNotPt_nv_V4:
1237    case Hexagon::STriw_imm_abs_cdnNotPt_nv_V4:
1238      return true;
1239
1240    default:
1241      return false;
1242  }
1243  return false;
1244}
1245
1246bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
1247  switch (MI->getOpcode())
1248  {
1249    // Load Byte
1250    case Hexagon::POST_LDrib:
1251    case Hexagon::POST_LDrib_cPt:
1252    case Hexagon::POST_LDrib_cNotPt:
1253    case Hexagon::POST_LDrib_cdnPt_V4:
1254    case Hexagon::POST_LDrib_cdnNotPt_V4:
1255
1256    // Load unsigned byte
1257    case Hexagon::POST_LDriub:
1258    case Hexagon::POST_LDriub_cPt:
1259    case Hexagon::POST_LDriub_cNotPt:
1260    case Hexagon::POST_LDriub_cdnPt_V4:
1261    case Hexagon::POST_LDriub_cdnNotPt_V4:
1262
1263    // Load halfword
1264    case Hexagon::POST_LDrih:
1265    case Hexagon::POST_LDrih_cPt:
1266    case Hexagon::POST_LDrih_cNotPt:
1267    case Hexagon::POST_LDrih_cdnPt_V4:
1268    case Hexagon::POST_LDrih_cdnNotPt_V4:
1269
1270    // Load unsigned halfword
1271    case Hexagon::POST_LDriuh:
1272    case Hexagon::POST_LDriuh_cPt:
1273    case Hexagon::POST_LDriuh_cNotPt:
1274    case Hexagon::POST_LDriuh_cdnPt_V4:
1275    case Hexagon::POST_LDriuh_cdnNotPt_V4:
1276
1277    // Load word
1278    case Hexagon::POST_LDriw:
1279    case Hexagon::POST_LDriw_cPt:
1280    case Hexagon::POST_LDriw_cNotPt:
1281    case Hexagon::POST_LDriw_cdnPt_V4:
1282    case Hexagon::POST_LDriw_cdnNotPt_V4:
1283
1284    // Load double word
1285    case Hexagon::POST_LDrid:
1286    case Hexagon::POST_LDrid_cPt:
1287    case Hexagon::POST_LDrid_cNotPt:
1288    case Hexagon::POST_LDrid_cdnPt_V4:
1289    case Hexagon::POST_LDrid_cdnNotPt_V4:
1290
1291    // Store byte
1292    case Hexagon::POST_STbri:
1293    case Hexagon::POST_STbri_cPt:
1294    case Hexagon::POST_STbri_cNotPt:
1295    case Hexagon::POST_STbri_cdnPt_V4:
1296    case Hexagon::POST_STbri_cdnNotPt_V4:
1297
1298    // Store halfword
1299    case Hexagon::POST_SThri:
1300    case Hexagon::POST_SThri_cPt:
1301    case Hexagon::POST_SThri_cNotPt:
1302    case Hexagon::POST_SThri_cdnPt_V4:
1303    case Hexagon::POST_SThri_cdnNotPt_V4:
1304
1305    // Store word
1306    case Hexagon::POST_STwri:
1307    case Hexagon::POST_STwri_cPt:
1308    case Hexagon::POST_STwri_cNotPt:
1309    case Hexagon::POST_STwri_cdnPt_V4:
1310    case Hexagon::POST_STwri_cdnNotPt_V4:
1311
1312    // Store double word
1313    case Hexagon::POST_STdri:
1314    case Hexagon::POST_STdri_cPt:
1315    case Hexagon::POST_STdri_cNotPt:
1316    case Hexagon::POST_STdri_cdnPt_V4:
1317    case Hexagon::POST_STdri_cdnNotPt_V4:
1318      return true;
1319
1320    default:
1321      return false;
1322  }
1323}
1324
1325bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
1326  return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
1327}
1328
1329bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
1330  bool isPred = MI->getDesc().isPredicable();
1331
1332  if (!isPred)
1333    return false;
1334
1335  const int Opc = MI->getOpcode();
1336
1337  switch(Opc) {
1338  case Hexagon::TFRI:
1339    return isInt<12>(MI->getOperand(1).getImm());
1340
1341  case Hexagon::STrid:
1342  case Hexagon::STrid_indexed:
1343    return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
1344
1345  case Hexagon::STriw:
1346  case Hexagon::STriw_indexed:
1347  case Hexagon::STriw_nv_V4:
1348    return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
1349
1350  case Hexagon::STrih:
1351  case Hexagon::STrih_indexed:
1352  case Hexagon::STrih_nv_V4:
1353    return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
1354
1355  case Hexagon::STrib:
1356  case Hexagon::STrib_indexed:
1357  case Hexagon::STrib_nv_V4:
1358    return isUInt<6>(MI->getOperand(1).getImm());
1359
1360  case Hexagon::LDrid:
1361  case Hexagon::LDrid_indexed:
1362    return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
1363
1364  case Hexagon::LDriw:
1365  case Hexagon::LDriw_indexed:
1366    return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
1367
1368  case Hexagon::LDrih:
1369  case Hexagon::LDriuh:
1370  case Hexagon::LDrih_indexed:
1371  case Hexagon::LDriuh_indexed:
1372    return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
1373
1374  case Hexagon::LDrib:
1375  case Hexagon::LDriub:
1376  case Hexagon::LDrib_indexed:
1377  case Hexagon::LDriub_indexed:
1378    return isUInt<6>(MI->getOperand(2).getImm());
1379
1380  case Hexagon::POST_LDrid:
1381    return isShiftedInt<4,3>(MI->getOperand(3).getImm());
1382
1383  case Hexagon::POST_LDriw:
1384    return isShiftedInt<4,2>(MI->getOperand(3).getImm());
1385
1386  case Hexagon::POST_LDrih:
1387  case Hexagon::POST_LDriuh:
1388    return isShiftedInt<4,1>(MI->getOperand(3).getImm());
1389
1390  case Hexagon::POST_LDrib:
1391  case Hexagon::POST_LDriub:
1392    return isInt<4>(MI->getOperand(3).getImm());
1393
1394  case Hexagon::STrib_imm_V4:
1395  case Hexagon::STrih_imm_V4:
1396  case Hexagon::STriw_imm_V4:
1397    return (isUInt<6>(MI->getOperand(1).getImm()) &&
1398            isInt<6>(MI->getOperand(2).getImm()));
1399
1400  case Hexagon::ADD_ri:
1401    return isInt<8>(MI->getOperand(2).getImm());
1402
1403  case Hexagon::ASLH:
1404  case Hexagon::ASRH:
1405  case Hexagon::SXTB:
1406  case Hexagon::SXTH:
1407  case Hexagon::ZXTB:
1408  case Hexagon::ZXTH:
1409    return Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
1410
1411  case Hexagon::JMPR:
1412    return false;
1413  }
1414
1415  return true;
1416}
1417
1418unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
1419  switch(Opc) {
1420    case Hexagon::TFR_cPt:
1421      return Hexagon::TFR_cNotPt;
1422    case Hexagon::TFR_cNotPt:
1423      return Hexagon::TFR_cPt;
1424
1425    case Hexagon::TFRI_cPt:
1426      return Hexagon::TFRI_cNotPt;
1427    case Hexagon::TFRI_cNotPt:
1428      return Hexagon::TFRI_cPt;
1429
1430    case Hexagon::JMP_c:
1431      return Hexagon::JMP_cNot;
1432    case Hexagon::JMP_cNot:
1433      return Hexagon::JMP_c;
1434
1435    case Hexagon::ADD_ri_cPt:
1436      return Hexagon::ADD_ri_cNotPt;
1437    case Hexagon::ADD_ri_cNotPt:
1438      return Hexagon::ADD_ri_cPt;
1439
1440    case Hexagon::ADD_rr_cPt:
1441      return Hexagon::ADD_rr_cNotPt;
1442    case Hexagon::ADD_rr_cNotPt:
1443      return Hexagon::ADD_rr_cPt;
1444
1445    case Hexagon::XOR_rr_cPt:
1446      return Hexagon::XOR_rr_cNotPt;
1447    case Hexagon::XOR_rr_cNotPt:
1448      return Hexagon::XOR_rr_cPt;
1449
1450    case Hexagon::AND_rr_cPt:
1451      return Hexagon::AND_rr_cNotPt;
1452    case Hexagon::AND_rr_cNotPt:
1453      return Hexagon::AND_rr_cPt;
1454
1455    case Hexagon::OR_rr_cPt:
1456      return Hexagon::OR_rr_cNotPt;
1457    case Hexagon::OR_rr_cNotPt:
1458      return Hexagon::OR_rr_cPt;
1459
1460    case Hexagon::SUB_rr_cPt:
1461      return Hexagon::SUB_rr_cNotPt;
1462    case Hexagon::SUB_rr_cNotPt:
1463      return Hexagon::SUB_rr_cPt;
1464
1465    case Hexagon::COMBINE_rr_cPt:
1466      return Hexagon::COMBINE_rr_cNotPt;
1467    case Hexagon::COMBINE_rr_cNotPt:
1468      return Hexagon::COMBINE_rr_cPt;
1469
1470    case Hexagon::ASLH_cPt_V4:
1471      return Hexagon::ASLH_cNotPt_V4;
1472    case Hexagon::ASLH_cNotPt_V4:
1473      return Hexagon::ASLH_cPt_V4;
1474
1475    case Hexagon::ASRH_cPt_V4:
1476      return Hexagon::ASRH_cNotPt_V4;
1477    case Hexagon::ASRH_cNotPt_V4:
1478      return Hexagon::ASRH_cPt_V4;
1479
1480    case Hexagon::SXTB_cPt_V4:
1481      return Hexagon::SXTB_cNotPt_V4;
1482    case Hexagon::SXTB_cNotPt_V4:
1483      return Hexagon::SXTB_cPt_V4;
1484
1485    case Hexagon::SXTH_cPt_V4:
1486      return Hexagon::SXTH_cNotPt_V4;
1487    case Hexagon::SXTH_cNotPt_V4:
1488      return Hexagon::SXTH_cPt_V4;
1489
1490    case Hexagon::ZXTB_cPt_V4:
1491      return Hexagon::ZXTB_cNotPt_V4;
1492    case Hexagon::ZXTB_cNotPt_V4:
1493      return Hexagon::ZXTB_cPt_V4;
1494
1495    case Hexagon::ZXTH_cPt_V4:
1496      return Hexagon::ZXTH_cNotPt_V4;
1497    case Hexagon::ZXTH_cNotPt_V4:
1498      return Hexagon::ZXTH_cPt_V4;
1499
1500
1501    case Hexagon::JMPR_cPt:
1502      return Hexagon::JMPR_cNotPt;
1503    case Hexagon::JMPR_cNotPt:
1504      return Hexagon::JMPR_cPt;
1505
1506  // V4 indexed+scaled load.
1507    case Hexagon::LDrid_indexed_cPt_V4:
1508      return Hexagon::LDrid_indexed_cNotPt_V4;
1509    case Hexagon::LDrid_indexed_cNotPt_V4:
1510      return Hexagon::LDrid_indexed_cPt_V4;
1511
1512    case Hexagon::LDrid_indexed_shl_cPt_V4:
1513      return Hexagon::LDrid_indexed_shl_cNotPt_V4;
1514    case Hexagon::LDrid_indexed_shl_cNotPt_V4:
1515      return Hexagon::LDrid_indexed_shl_cPt_V4;
1516
1517    case Hexagon::LDrib_indexed_cPt_V4:
1518      return Hexagon::LDrib_indexed_cNotPt_V4;
1519    case Hexagon::LDrib_indexed_cNotPt_V4:
1520      return Hexagon::LDrib_indexed_cPt_V4;
1521
1522    case Hexagon::LDriub_indexed_cPt_V4:
1523      return Hexagon::LDriub_indexed_cNotPt_V4;
1524    case Hexagon::LDriub_indexed_cNotPt_V4:
1525      return Hexagon::LDriub_indexed_cPt_V4;
1526
1527    case Hexagon::LDrib_indexed_shl_cPt_V4:
1528      return Hexagon::LDrib_indexed_shl_cNotPt_V4;
1529    case Hexagon::LDrib_indexed_shl_cNotPt_V4:
1530      return Hexagon::LDrib_indexed_shl_cPt_V4;
1531
1532    case Hexagon::LDriub_indexed_shl_cPt_V4:
1533      return Hexagon::LDriub_indexed_shl_cNotPt_V4;
1534    case Hexagon::LDriub_indexed_shl_cNotPt_V4:
1535      return Hexagon::LDriub_indexed_shl_cPt_V4;
1536
1537    case Hexagon::LDrih_indexed_cPt_V4:
1538      return Hexagon::LDrih_indexed_cNotPt_V4;
1539    case Hexagon::LDrih_indexed_cNotPt_V4:
1540      return Hexagon::LDrih_indexed_cPt_V4;
1541
1542    case Hexagon::LDriuh_indexed_cPt_V4:
1543      return Hexagon::LDriuh_indexed_cNotPt_V4;
1544    case Hexagon::LDriuh_indexed_cNotPt_V4:
1545      return Hexagon::LDriuh_indexed_cPt_V4;
1546
1547    case Hexagon::LDrih_indexed_shl_cPt_V4:
1548      return Hexagon::LDrih_indexed_shl_cNotPt_V4;
1549    case Hexagon::LDrih_indexed_shl_cNotPt_V4:
1550      return Hexagon::LDrih_indexed_shl_cPt_V4;
1551
1552    case Hexagon::LDriuh_indexed_shl_cPt_V4:
1553      return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1554    case Hexagon::LDriuh_indexed_shl_cNotPt_V4:
1555      return Hexagon::LDriuh_indexed_shl_cPt_V4;
1556
1557    case Hexagon::LDriw_indexed_cPt_V4:
1558      return Hexagon::LDriw_indexed_cNotPt_V4;
1559    case Hexagon::LDriw_indexed_cNotPt_V4:
1560      return Hexagon::LDriw_indexed_cPt_V4;
1561
1562    case Hexagon::LDriw_indexed_shl_cPt_V4:
1563      return Hexagon::LDriw_indexed_shl_cNotPt_V4;
1564    case Hexagon::LDriw_indexed_shl_cNotPt_V4:
1565      return Hexagon::LDriw_indexed_shl_cPt_V4;
1566
1567    // Byte.
1568    case Hexagon::POST_STbri_cPt:
1569      return Hexagon::POST_STbri_cNotPt;
1570    case Hexagon::POST_STbri_cNotPt:
1571      return Hexagon::POST_STbri_cPt;
1572
1573    case Hexagon::STrib_cPt:
1574      return Hexagon::STrib_cNotPt;
1575    case Hexagon::STrib_cNotPt:
1576      return Hexagon::STrib_cPt;
1577
1578    case Hexagon::STrib_indexed_cPt:
1579      return Hexagon::STrib_indexed_cNotPt;
1580    case Hexagon::STrib_indexed_cNotPt:
1581      return Hexagon::STrib_indexed_cPt;
1582
1583    case Hexagon::STrib_imm_cPt_V4:
1584      return Hexagon::STrib_imm_cNotPt_V4;
1585    case Hexagon::STrib_imm_cNotPt_V4:
1586      return Hexagon::STrib_imm_cPt_V4;
1587
1588    case Hexagon::STrib_indexed_shl_cPt_V4:
1589      return Hexagon::STrib_indexed_shl_cNotPt_V4;
1590    case Hexagon::STrib_indexed_shl_cNotPt_V4:
1591      return Hexagon::STrib_indexed_shl_cPt_V4;
1592
1593  // Halfword.
1594    case Hexagon::POST_SThri_cPt:
1595      return Hexagon::POST_SThri_cNotPt;
1596    case Hexagon::POST_SThri_cNotPt:
1597      return Hexagon::POST_SThri_cPt;
1598
1599    case Hexagon::STrih_cPt:
1600      return Hexagon::STrih_cNotPt;
1601    case Hexagon::STrih_cNotPt:
1602      return Hexagon::STrih_cPt;
1603
1604    case Hexagon::STrih_indexed_cPt:
1605      return Hexagon::STrih_indexed_cNotPt;
1606    case Hexagon::STrih_indexed_cNotPt:
1607      return Hexagon::STrih_indexed_cPt;
1608
1609    case Hexagon::STrih_imm_cPt_V4:
1610      return Hexagon::STrih_imm_cNotPt_V4;
1611    case Hexagon::STrih_imm_cNotPt_V4:
1612      return Hexagon::STrih_imm_cPt_V4;
1613
1614    case Hexagon::STrih_indexed_shl_cPt_V4:
1615      return Hexagon::STrih_indexed_shl_cNotPt_V4;
1616    case Hexagon::STrih_indexed_shl_cNotPt_V4:
1617      return Hexagon::STrih_indexed_shl_cPt_V4;
1618
1619  // Word.
1620    case Hexagon::POST_STwri_cPt:
1621      return Hexagon::POST_STwri_cNotPt;
1622    case Hexagon::POST_STwri_cNotPt:
1623      return Hexagon::POST_STwri_cPt;
1624
1625    case Hexagon::STriw_cPt:
1626      return Hexagon::STriw_cNotPt;
1627    case Hexagon::STriw_cNotPt:
1628      return Hexagon::STriw_cPt;
1629
1630    case Hexagon::STriw_indexed_cPt:
1631      return Hexagon::STriw_indexed_cNotPt;
1632    case Hexagon::STriw_indexed_cNotPt:
1633      return Hexagon::STriw_indexed_cPt;
1634
1635    case Hexagon::STriw_indexed_shl_cPt_V4:
1636      return Hexagon::STriw_indexed_shl_cNotPt_V4;
1637    case Hexagon::STriw_indexed_shl_cNotPt_V4:
1638      return Hexagon::STriw_indexed_shl_cPt_V4;
1639
1640    case Hexagon::STriw_imm_cPt_V4:
1641      return Hexagon::STriw_imm_cNotPt_V4;
1642    case Hexagon::STriw_imm_cNotPt_V4:
1643      return Hexagon::STriw_imm_cPt_V4;
1644
1645  // Double word.
1646    case Hexagon::POST_STdri_cPt:
1647      return Hexagon::POST_STdri_cNotPt;
1648    case Hexagon::POST_STdri_cNotPt:
1649      return Hexagon::POST_STdri_cPt;
1650
1651    case Hexagon::STrid_cPt:
1652      return Hexagon::STrid_cNotPt;
1653    case Hexagon::STrid_cNotPt:
1654      return Hexagon::STrid_cPt;
1655
1656    case Hexagon::STrid_indexed_cPt:
1657      return Hexagon::STrid_indexed_cNotPt;
1658    case Hexagon::STrid_indexed_cNotPt:
1659      return Hexagon::STrid_indexed_cPt;
1660
1661    case Hexagon::STrid_indexed_shl_cPt_V4:
1662      return Hexagon::STrid_indexed_shl_cNotPt_V4;
1663    case Hexagon::STrid_indexed_shl_cNotPt_V4:
1664      return Hexagon::STrid_indexed_shl_cPt_V4;
1665
1666  // Load.
1667    case Hexagon::LDrid_cPt:
1668      return Hexagon::LDrid_cNotPt;
1669    case Hexagon::LDrid_cNotPt:
1670      return Hexagon::LDrid_cPt;
1671
1672    case Hexagon::LDriw_cPt:
1673      return Hexagon::LDriw_cNotPt;
1674    case Hexagon::LDriw_cNotPt:
1675      return Hexagon::LDriw_cPt;
1676
1677    case Hexagon::LDrih_cPt:
1678      return Hexagon::LDrih_cNotPt;
1679    case Hexagon::LDrih_cNotPt:
1680      return Hexagon::LDrih_cPt;
1681
1682    case Hexagon::LDriuh_cPt:
1683      return Hexagon::LDriuh_cNotPt;
1684    case Hexagon::LDriuh_cNotPt:
1685      return Hexagon::LDriuh_cPt;
1686
1687    case Hexagon::LDrib_cPt:
1688      return Hexagon::LDrib_cNotPt;
1689    case Hexagon::LDrib_cNotPt:
1690      return Hexagon::LDrib_cPt;
1691
1692    case Hexagon::LDriub_cPt:
1693      return Hexagon::LDriub_cNotPt;
1694    case Hexagon::LDriub_cNotPt:
1695      return Hexagon::LDriub_cPt;
1696
1697 // Load Indexed.
1698    case Hexagon::LDrid_indexed_cPt:
1699      return Hexagon::LDrid_indexed_cNotPt;
1700    case Hexagon::LDrid_indexed_cNotPt:
1701      return Hexagon::LDrid_indexed_cPt;
1702
1703    case Hexagon::LDriw_indexed_cPt:
1704      return Hexagon::LDriw_indexed_cNotPt;
1705    case Hexagon::LDriw_indexed_cNotPt:
1706      return Hexagon::LDriw_indexed_cPt;
1707
1708    case Hexagon::LDrih_indexed_cPt:
1709      return Hexagon::LDrih_indexed_cNotPt;
1710    case Hexagon::LDrih_indexed_cNotPt:
1711      return Hexagon::LDrih_indexed_cPt;
1712
1713    case Hexagon::LDriuh_indexed_cPt:
1714      return Hexagon::LDriuh_indexed_cNotPt;
1715    case Hexagon::LDriuh_indexed_cNotPt:
1716      return Hexagon::LDriuh_indexed_cPt;
1717
1718    case Hexagon::LDrib_indexed_cPt:
1719      return Hexagon::LDrib_indexed_cNotPt;
1720    case Hexagon::LDrib_indexed_cNotPt:
1721      return Hexagon::LDrib_indexed_cPt;
1722
1723    case Hexagon::LDriub_indexed_cPt:
1724      return Hexagon::LDriub_indexed_cNotPt;
1725    case Hexagon::LDriub_indexed_cNotPt:
1726      return Hexagon::LDriub_indexed_cPt;
1727
1728  // Post Inc Load.
1729    case Hexagon::POST_LDrid_cPt:
1730      return Hexagon::POST_LDrid_cNotPt;
1731    case Hexagon::POST_LDriw_cNotPt:
1732      return Hexagon::POST_LDriw_cPt;
1733
1734    case Hexagon::POST_LDrih_cPt:
1735      return Hexagon::POST_LDrih_cNotPt;
1736    case Hexagon::POST_LDrih_cNotPt:
1737      return Hexagon::POST_LDrih_cPt;
1738
1739    case Hexagon::POST_LDriuh_cPt:
1740      return Hexagon::POST_LDriuh_cNotPt;
1741    case Hexagon::POST_LDriuh_cNotPt:
1742      return Hexagon::POST_LDriuh_cPt;
1743
1744    case Hexagon::POST_LDrib_cPt:
1745      return Hexagon::POST_LDrib_cNotPt;
1746    case Hexagon::POST_LDrib_cNotPt:
1747      return Hexagon::POST_LDrib_cPt;
1748
1749    case Hexagon::POST_LDriub_cPt:
1750      return Hexagon::POST_LDriub_cNotPt;
1751    case Hexagon::POST_LDriub_cNotPt:
1752      return Hexagon::POST_LDriub_cPt;
1753
1754  // Dealloc_return.
1755    case Hexagon::DEALLOC_RET_cPt_V4:
1756      return Hexagon::DEALLOC_RET_cNotPt_V4;
1757    case Hexagon::DEALLOC_RET_cNotPt_V4:
1758      return Hexagon::DEALLOC_RET_cPt_V4;
1759
1760   // New Value Jump.
1761   // JMPEQ_ri - with -1.
1762    case Hexagon::JMP_EQriPtneg_nv_V4:
1763      return Hexagon::JMP_EQriNotPtneg_nv_V4;
1764    case Hexagon::JMP_EQriNotPtneg_nv_V4:
1765      return Hexagon::JMP_EQriPtneg_nv_V4;
1766
1767    case Hexagon::JMP_EQriPntneg_nv_V4:
1768      return Hexagon::JMP_EQriNotPntneg_nv_V4;
1769    case Hexagon::JMP_EQriNotPntneg_nv_V4:
1770      return Hexagon::JMP_EQriPntneg_nv_V4;
1771
1772   // JMPEQ_ri.
1773     case Hexagon::JMP_EQriPt_nv_V4:
1774      return Hexagon::JMP_EQriNotPt_nv_V4;
1775    case Hexagon::JMP_EQriNotPt_nv_V4:
1776      return Hexagon::JMP_EQriPt_nv_V4;
1777
1778     case Hexagon::JMP_EQriPnt_nv_V4:
1779      return Hexagon::JMP_EQriNotPnt_nv_V4;
1780    case Hexagon::JMP_EQriNotPnt_nv_V4:
1781      return Hexagon::JMP_EQriPnt_nv_V4;
1782
1783   // JMPEQ_rr.
1784     case Hexagon::JMP_EQrrPt_nv_V4:
1785      return Hexagon::JMP_EQrrNotPt_nv_V4;
1786    case Hexagon::JMP_EQrrNotPt_nv_V4:
1787      return Hexagon::JMP_EQrrPt_nv_V4;
1788
1789     case Hexagon::JMP_EQrrPnt_nv_V4:
1790      return Hexagon::JMP_EQrrNotPnt_nv_V4;
1791    case Hexagon::JMP_EQrrNotPnt_nv_V4:
1792      return Hexagon::JMP_EQrrPnt_nv_V4;
1793
1794   // JMPGT_ri - with -1.
1795    case Hexagon::JMP_GTriPtneg_nv_V4:
1796      return Hexagon::JMP_GTriNotPtneg_nv_V4;
1797    case Hexagon::JMP_GTriNotPtneg_nv_V4:
1798      return Hexagon::JMP_GTriPtneg_nv_V4;
1799
1800    case Hexagon::JMP_GTriPntneg_nv_V4:
1801      return Hexagon::JMP_GTriNotPntneg_nv_V4;
1802    case Hexagon::JMP_GTriNotPntneg_nv_V4:
1803      return Hexagon::JMP_GTriPntneg_nv_V4;
1804
1805   // JMPGT_ri.
1806     case Hexagon::JMP_GTriPt_nv_V4:
1807      return Hexagon::JMP_GTriNotPt_nv_V4;
1808    case Hexagon::JMP_GTriNotPt_nv_V4:
1809      return Hexagon::JMP_GTriPt_nv_V4;
1810
1811     case Hexagon::JMP_GTriPnt_nv_V4:
1812      return Hexagon::JMP_GTriNotPnt_nv_V4;
1813    case Hexagon::JMP_GTriNotPnt_nv_V4:
1814      return Hexagon::JMP_GTriPnt_nv_V4;
1815
1816   // JMPGT_rr.
1817     case Hexagon::JMP_GTrrPt_nv_V4:
1818      return Hexagon::JMP_GTrrNotPt_nv_V4;
1819    case Hexagon::JMP_GTrrNotPt_nv_V4:
1820      return Hexagon::JMP_GTrrPt_nv_V4;
1821
1822     case Hexagon::JMP_GTrrPnt_nv_V4:
1823      return Hexagon::JMP_GTrrNotPnt_nv_V4;
1824    case Hexagon::JMP_GTrrNotPnt_nv_V4:
1825      return Hexagon::JMP_GTrrPnt_nv_V4;
1826
1827   // JMPGT_rrdn.
1828     case Hexagon::JMP_GTrrdnPt_nv_V4:
1829      return Hexagon::JMP_GTrrdnNotPt_nv_V4;
1830    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
1831      return Hexagon::JMP_GTrrdnPt_nv_V4;
1832
1833     case Hexagon::JMP_GTrrdnPnt_nv_V4:
1834      return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
1835    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
1836      return Hexagon::JMP_GTrrdnPnt_nv_V4;
1837
1838   // JMPGTU_ri.
1839     case Hexagon::JMP_GTUriPt_nv_V4:
1840      return Hexagon::JMP_GTUriNotPt_nv_V4;
1841    case Hexagon::JMP_GTUriNotPt_nv_V4:
1842      return Hexagon::JMP_GTUriPt_nv_V4;
1843
1844     case Hexagon::JMP_GTUriPnt_nv_V4:
1845      return Hexagon::JMP_GTUriNotPnt_nv_V4;
1846    case Hexagon::JMP_GTUriNotPnt_nv_V4:
1847      return Hexagon::JMP_GTUriPnt_nv_V4;
1848
1849   // JMPGTU_rr.
1850     case Hexagon::JMP_GTUrrPt_nv_V4:
1851      return Hexagon::JMP_GTUrrNotPt_nv_V4;
1852    case Hexagon::JMP_GTUrrNotPt_nv_V4:
1853      return Hexagon::JMP_GTUrrPt_nv_V4;
1854
1855     case Hexagon::JMP_GTUrrPnt_nv_V4:
1856      return Hexagon::JMP_GTUrrNotPnt_nv_V4;
1857    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
1858      return Hexagon::JMP_GTUrrPnt_nv_V4;
1859
1860   // JMPGTU_rrdn.
1861     case Hexagon::JMP_GTUrrdnPt_nv_V4:
1862      return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
1863    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
1864      return Hexagon::JMP_GTUrrdnPt_nv_V4;
1865
1866     case Hexagon::JMP_GTUrrdnPnt_nv_V4:
1867      return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
1868    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
1869      return Hexagon::JMP_GTUrrdnPnt_nv_V4;
1870
1871  default:
1872    llvm_unreachable("Unexpected predicated instruction");
1873  }
1874}
1875
1876
1877int HexagonInstrInfo::
1878getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
1879  switch(Opc) {
1880  case Hexagon::TFR:
1881    return !invertPredicate ? Hexagon::TFR_cPt :
1882                              Hexagon::TFR_cNotPt;
1883  case Hexagon::TFRI:
1884    return !invertPredicate ? Hexagon::TFRI_cPt :
1885                              Hexagon::TFRI_cNotPt;
1886  case Hexagon::JMP:
1887    return !invertPredicate ? Hexagon::JMP_c :
1888                              Hexagon::JMP_cNot;
1889  case Hexagon::ADD_ri:
1890    return !invertPredicate ? Hexagon::ADD_ri_cPt :
1891                              Hexagon::ADD_ri_cNotPt;
1892  case Hexagon::ADD_rr:
1893    return !invertPredicate ? Hexagon::ADD_rr_cPt :
1894                              Hexagon::ADD_rr_cNotPt;
1895  case Hexagon::XOR_rr:
1896    return !invertPredicate ? Hexagon::XOR_rr_cPt :
1897                              Hexagon::XOR_rr_cNotPt;
1898  case Hexagon::AND_rr:
1899    return !invertPredicate ? Hexagon::AND_rr_cPt :
1900                              Hexagon::AND_rr_cNotPt;
1901  case Hexagon::OR_rr:
1902    return !invertPredicate ? Hexagon::OR_rr_cPt :
1903                              Hexagon::OR_rr_cNotPt;
1904  case Hexagon::SUB_rr:
1905    return !invertPredicate ? Hexagon::SUB_rr_cPt :
1906                              Hexagon::SUB_rr_cNotPt;
1907  case Hexagon::COMBINE_rr:
1908    return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
1909                              Hexagon::COMBINE_rr_cNotPt;
1910  case Hexagon::ASLH:
1911    return !invertPredicate ? Hexagon::ASLH_cPt_V4 :
1912                              Hexagon::ASLH_cNotPt_V4;
1913  case Hexagon::ASRH:
1914    return !invertPredicate ? Hexagon::ASRH_cPt_V4 :
1915                              Hexagon::ASRH_cNotPt_V4;
1916  case Hexagon::SXTB:
1917    return !invertPredicate ? Hexagon::SXTB_cPt_V4 :
1918                              Hexagon::SXTB_cNotPt_V4;
1919  case Hexagon::SXTH:
1920    return !invertPredicate ? Hexagon::SXTH_cPt_V4 :
1921                              Hexagon::SXTH_cNotPt_V4;
1922  case Hexagon::ZXTB:
1923    return !invertPredicate ? Hexagon::ZXTB_cPt_V4 :
1924                              Hexagon::ZXTB_cNotPt_V4;
1925  case Hexagon::ZXTH:
1926    return !invertPredicate ? Hexagon::ZXTH_cPt_V4 :
1927                              Hexagon::ZXTH_cNotPt_V4;
1928
1929  case Hexagon::JMPR:
1930    return !invertPredicate ? Hexagon::JMPR_cPt :
1931                              Hexagon::JMPR_cNotPt;
1932
1933  // V4 indexed+scaled load.
1934  case Hexagon::LDrid_indexed_V4:
1935    return !invertPredicate ? Hexagon::LDrid_indexed_cPt_V4 :
1936                              Hexagon::LDrid_indexed_cNotPt_V4;
1937  case Hexagon::LDrid_indexed_shl_V4:
1938    return !invertPredicate ? Hexagon::LDrid_indexed_shl_cPt_V4 :
1939                              Hexagon::LDrid_indexed_shl_cNotPt_V4;
1940  case Hexagon::LDrib_indexed_V4:
1941    return !invertPredicate ? Hexagon::LDrib_indexed_cPt_V4 :
1942                              Hexagon::LDrib_indexed_cNotPt_V4;
1943  case Hexagon::LDriub_indexed_V4:
1944    return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 :
1945                              Hexagon::LDriub_indexed_cNotPt_V4;
1946  case Hexagon::LDriub_ae_indexed_V4:
1947    return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 :
1948                              Hexagon::LDriub_indexed_cNotPt_V4;
1949  case Hexagon::LDrib_indexed_shl_V4:
1950    return !invertPredicate ? Hexagon::LDrib_indexed_shl_cPt_V4 :
1951                              Hexagon::LDrib_indexed_shl_cNotPt_V4;
1952  case Hexagon::LDriub_indexed_shl_V4:
1953    return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
1954                              Hexagon::LDriub_indexed_shl_cNotPt_V4;
1955  case Hexagon::LDriub_ae_indexed_shl_V4:
1956    return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
1957                              Hexagon::LDriub_indexed_shl_cNotPt_V4;
1958  case Hexagon::LDrih_indexed_V4:
1959    return !invertPredicate ? Hexagon::LDrih_indexed_cPt_V4 :
1960                              Hexagon::LDrih_indexed_cNotPt_V4;
1961  case Hexagon::LDriuh_indexed_V4:
1962    return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 :
1963                              Hexagon::LDriuh_indexed_cNotPt_V4;
1964  case Hexagon::LDriuh_ae_indexed_V4:
1965    return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 :
1966                              Hexagon::LDriuh_indexed_cNotPt_V4;
1967  case Hexagon::LDrih_indexed_shl_V4:
1968    return !invertPredicate ? Hexagon::LDrih_indexed_shl_cPt_V4 :
1969                              Hexagon::LDrih_indexed_shl_cNotPt_V4;
1970  case Hexagon::LDriuh_indexed_shl_V4:
1971    return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
1972                              Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1973  case Hexagon::LDriuh_ae_indexed_shl_V4:
1974    return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
1975                              Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1976  case Hexagon::LDriw_indexed_V4:
1977    return !invertPredicate ? Hexagon::LDriw_indexed_cPt_V4 :
1978                              Hexagon::LDriw_indexed_cNotPt_V4;
1979  case Hexagon::LDriw_indexed_shl_V4:
1980    return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 :
1981                              Hexagon::LDriw_indexed_shl_cNotPt_V4;
1982    // Byte.
1983  case Hexagon::POST_STbri:
1984    return !invertPredicate ? Hexagon::POST_STbri_cPt :
1985                              Hexagon::POST_STbri_cNotPt;
1986  case Hexagon::STrib:
1987    return !invertPredicate ? Hexagon::STrib_cPt :
1988                              Hexagon::STrib_cNotPt;
1989  case Hexagon::STrib_indexed:
1990    return !invertPredicate ? Hexagon::STrib_indexed_cPt :
1991                              Hexagon::STrib_indexed_cNotPt;
1992  case Hexagon::STrib_imm_V4:
1993    return !invertPredicate ? Hexagon::STrib_imm_cPt_V4 :
1994                              Hexagon::STrib_imm_cNotPt_V4;
1995  case Hexagon::STrib_indexed_shl_V4:
1996    return !invertPredicate ? Hexagon::STrib_indexed_shl_cPt_V4 :
1997                              Hexagon::STrib_indexed_shl_cNotPt_V4;
1998  // Halfword.
1999  case Hexagon::POST_SThri:
2000    return !invertPredicate ? Hexagon::POST_SThri_cPt :
2001                              Hexagon::POST_SThri_cNotPt;
2002  case Hexagon::STrih:
2003    return !invertPredicate ? Hexagon::STrih_cPt :
2004                              Hexagon::STrih_cNotPt;
2005  case Hexagon::STrih_indexed:
2006    return !invertPredicate ? Hexagon::STrih_indexed_cPt :
2007                              Hexagon::STrih_indexed_cNotPt;
2008  case Hexagon::STrih_imm_V4:
2009    return !invertPredicate ? Hexagon::STrih_imm_cPt_V4 :
2010                              Hexagon::STrih_imm_cNotPt_V4;
2011  case Hexagon::STrih_indexed_shl_V4:
2012    return !invertPredicate ? Hexagon::STrih_indexed_shl_cPt_V4 :
2013                              Hexagon::STrih_indexed_shl_cNotPt_V4;
2014  // Word.
2015  case Hexagon::POST_STwri:
2016    return !invertPredicate ? Hexagon::POST_STwri_cPt :
2017                              Hexagon::POST_STwri_cNotPt;
2018  case Hexagon::STriw:
2019    return !invertPredicate ? Hexagon::STriw_cPt :
2020                              Hexagon::STriw_cNotPt;
2021  case Hexagon::STriw_indexed:
2022    return !invertPredicate ? Hexagon::STriw_indexed_cPt :
2023                              Hexagon::STriw_indexed_cNotPt;
2024  case Hexagon::STriw_indexed_shl_V4:
2025    return !invertPredicate ? Hexagon::STriw_indexed_shl_cPt_V4 :
2026                              Hexagon::STriw_indexed_shl_cNotPt_V4;
2027  case Hexagon::STriw_imm_V4:
2028    return !invertPredicate ? Hexagon::STriw_imm_cPt_V4 :
2029                              Hexagon::STriw_imm_cNotPt_V4;
2030  // Double word.
2031  case Hexagon::POST_STdri:
2032    return !invertPredicate ? Hexagon::POST_STdri_cPt :
2033                              Hexagon::POST_STdri_cNotPt;
2034  case Hexagon::STrid:
2035    return !invertPredicate ? Hexagon::STrid_cPt :
2036                              Hexagon::STrid_cNotPt;
2037  case Hexagon::STrid_indexed:
2038    return !invertPredicate ? Hexagon::STrid_indexed_cPt :
2039                              Hexagon::STrid_indexed_cNotPt;
2040  case Hexagon::STrid_indexed_shl_V4:
2041    return !invertPredicate ? Hexagon::STrid_indexed_shl_cPt_V4 :
2042                              Hexagon::STrid_indexed_shl_cNotPt_V4;
2043  // Load.
2044  case Hexagon::LDrid:
2045    return !invertPredicate ? Hexagon::LDrid_cPt :
2046                              Hexagon::LDrid_cNotPt;
2047  case Hexagon::LDriw:
2048    return !invertPredicate ? Hexagon::LDriw_cPt :
2049                              Hexagon::LDriw_cNotPt;
2050  case Hexagon::LDrih:
2051    return !invertPredicate ? Hexagon::LDrih_cPt :
2052                              Hexagon::LDrih_cNotPt;
2053  case Hexagon::LDriuh:
2054    return !invertPredicate ? Hexagon::LDriuh_cPt :
2055                              Hexagon::LDriuh_cNotPt;
2056  case Hexagon::LDrib:
2057    return !invertPredicate ? Hexagon::LDrib_cPt :
2058                              Hexagon::LDrib_cNotPt;
2059  case Hexagon::LDriub:
2060    return !invertPredicate ? Hexagon::LDriub_cPt :
2061                              Hexagon::LDriub_cNotPt;
2062  case Hexagon::LDriubit:
2063    return !invertPredicate ? Hexagon::LDriub_cPt :
2064                              Hexagon::LDriub_cNotPt;
2065 // Load Indexed.
2066  case Hexagon::LDrid_indexed:
2067    return !invertPredicate ? Hexagon::LDrid_indexed_cPt :
2068                              Hexagon::LDrid_indexed_cNotPt;
2069  case Hexagon::LDriw_indexed:
2070    return !invertPredicate ? Hexagon::LDriw_indexed_cPt :
2071                              Hexagon::LDriw_indexed_cNotPt;
2072  case Hexagon::LDrih_indexed:
2073    return !invertPredicate ? Hexagon::LDrih_indexed_cPt :
2074                              Hexagon::LDrih_indexed_cNotPt;
2075  case Hexagon::LDriuh_indexed:
2076    return !invertPredicate ? Hexagon::LDriuh_indexed_cPt :
2077                              Hexagon::LDriuh_indexed_cNotPt;
2078  case Hexagon::LDrib_indexed:
2079    return !invertPredicate ? Hexagon::LDrib_indexed_cPt :
2080                              Hexagon::LDrib_indexed_cNotPt;
2081  case Hexagon::LDriub_indexed:
2082    return !invertPredicate ? Hexagon::LDriub_indexed_cPt :
2083                              Hexagon::LDriub_indexed_cNotPt;
2084  // Post Increment Load.
2085  case Hexagon::POST_LDrid:
2086    return !invertPredicate ? Hexagon::POST_LDrid_cPt :
2087                              Hexagon::POST_LDrid_cNotPt;
2088  case Hexagon::POST_LDriw:
2089    return !invertPredicate ? Hexagon::POST_LDriw_cPt :
2090                              Hexagon::POST_LDriw_cNotPt;
2091  case Hexagon::POST_LDrih:
2092    return !invertPredicate ? Hexagon::POST_LDrih_cPt :
2093                              Hexagon::POST_LDrih_cNotPt;
2094  case Hexagon::POST_LDriuh:
2095    return !invertPredicate ? Hexagon::POST_LDriuh_cPt :
2096                              Hexagon::POST_LDriuh_cNotPt;
2097  case Hexagon::POST_LDrib:
2098    return !invertPredicate ? Hexagon::POST_LDrib_cPt :
2099                              Hexagon::POST_LDrib_cNotPt;
2100  case Hexagon::POST_LDriub:
2101    return !invertPredicate ? Hexagon::POST_LDriub_cPt :
2102                              Hexagon::POST_LDriub_cNotPt;
2103  // DEALLOC_RETURN.
2104  case Hexagon::DEALLOC_RET_V4:
2105    return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
2106                              Hexagon::DEALLOC_RET_cNotPt_V4;
2107  }
2108  llvm_unreachable("Unexpected predicable instruction");
2109}
2110
2111
2112bool HexagonInstrInfo::
2113PredicateInstruction(MachineInstr *MI,
2114                     const SmallVectorImpl<MachineOperand> &Cond) const {
2115  int Opc = MI->getOpcode();
2116  assert (isPredicable(MI) && "Expected predicable instruction");
2117  bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
2118                     (Cond[0].getImm() == 0));
2119  MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
2120  //
2121  // This assumes that the predicate is always the first operand
2122  // in the set of inputs.
2123  //
2124  MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
2125  int oper;
2126  for (oper = MI->getNumOperands() - 3; oper >= 0; --oper) {
2127    MachineOperand MO = MI->getOperand(oper);
2128    if ((MO.isReg() && !MO.isUse() && !MO.isImplicit())) {
2129      break;
2130    }
2131
2132    if (MO.isReg()) {
2133      MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
2134                                              MO.isImplicit(), MO.isKill(),
2135                                              MO.isDead(), MO.isUndef(),
2136                                              MO.isDebug());
2137    } else if (MO.isImm()) {
2138      MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
2139    } else {
2140      llvm_unreachable("Unexpected operand type");
2141    }
2142  }
2143
2144  int regPos = invertJump ? 1 : 0;
2145  MachineOperand PredMO = Cond[regPos];
2146  MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
2147                                          PredMO.isImplicit(), PredMO.isKill(),
2148                                          PredMO.isDead(), PredMO.isUndef(),
2149                                          PredMO.isDebug());
2150
2151  return true;
2152}
2153
2154
2155bool
2156HexagonInstrInfo::
2157isProfitableToIfCvt(MachineBasicBlock &MBB,
2158                    unsigned NumCyles,
2159                    unsigned ExtraPredCycles,
2160                    const BranchProbability &Probability) const {
2161  return true;
2162}
2163
2164
2165bool
2166HexagonInstrInfo::
2167isProfitableToIfCvt(MachineBasicBlock &TMBB,
2168                    unsigned NumTCycles,
2169                    unsigned ExtraTCycles,
2170                    MachineBasicBlock &FMBB,
2171                    unsigned NumFCycles,
2172                    unsigned ExtraFCycles,
2173                    const BranchProbability &Probability) const {
2174  return true;
2175}
2176
2177
2178bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
2179  const uint64_t F = MI->getDesc().TSFlags;
2180
2181  return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
2182}
2183
2184
2185bool
2186HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
2187                                   std::vector<MachineOperand> &Pred) const {
2188  for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
2189    MachineOperand MO = MI->getOperand(oper);
2190    if (MO.isReg() && MO.isDef()) {
2191      const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
2192      if (RC == Hexagon::PredRegsRegisterClass) {
2193        Pred.push_back(MO);
2194        return true;
2195      }
2196    }
2197  }
2198  return false;
2199}
2200
2201
2202bool
2203HexagonInstrInfo::
2204SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
2205                  const SmallVectorImpl<MachineOperand> &Pred2) const {
2206  // TODO: Fix this
2207  return false;
2208}
2209
2210
2211//
2212// We indicate that we want to reverse the branch by
2213// inserting a 0 at the beginning of the Cond vector.
2214//
2215bool HexagonInstrInfo::
2216ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2217  if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
2218    Cond.erase(Cond.begin());
2219  } else {
2220    Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
2221  }
2222  return false;
2223}
2224
2225
2226bool HexagonInstrInfo::
2227isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
2228                          const BranchProbability &Probability) const {
2229  return (NumInstrs <= 4);
2230}
2231
2232bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
2233  switch (MI->getOpcode()) {
2234  case Hexagon::DEALLOC_RET_V4 :
2235  case Hexagon::DEALLOC_RET_cPt_V4 :
2236  case Hexagon::DEALLOC_RET_cNotPt_V4 :
2237  case Hexagon::DEALLOC_RET_cdnPnt_V4 :
2238  case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
2239  case Hexagon::DEALLOC_RET_cdnPt_V4 :
2240  case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
2241   return true;
2242  }
2243  return false;
2244}
2245
2246
2247bool HexagonInstrInfo::
2248isValidOffset(const int Opcode, const int Offset) const {
2249  // This function is to check whether the "Offset" is in the correct range of
2250  // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
2251  // inserted to calculate the final address. Due to this reason, the function
2252  // assumes that the "Offset" has correct alignment.
2253
2254  switch(Opcode) {
2255
2256  case Hexagon::LDriw:
2257  case Hexagon::STriw:
2258    assert((Offset % 4 == 0) && "Offset has incorrect alignment");
2259    return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2260      (Offset <= Hexagon_MEMW_OFFSET_MAX);
2261
2262  case Hexagon::LDrid:
2263  case Hexagon::STrid:
2264    assert((Offset % 8 == 0) && "Offset has incorrect alignment");
2265    return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2266      (Offset <= Hexagon_MEMD_OFFSET_MAX);
2267
2268  case Hexagon::LDrih:
2269  case Hexagon::LDriuh:
2270  case Hexagon::STrih:
2271  case Hexagon::LDrih_ae:
2272    assert((Offset % 2 == 0) && "Offset has incorrect alignment");
2273    return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2274      (Offset <= Hexagon_MEMH_OFFSET_MAX);
2275
2276  case Hexagon::LDrib:
2277  case Hexagon::STrib:
2278  case Hexagon::LDriub:
2279  case Hexagon::LDriubit:
2280  case Hexagon::LDrib_ae:
2281  case Hexagon::LDriub_ae:
2282    return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2283      (Offset <= Hexagon_MEMB_OFFSET_MAX);
2284
2285  case Hexagon::ADD_ri:
2286  case Hexagon::TFR_FI:
2287    return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2288      (Offset <= Hexagon_ADDI_OFFSET_MAX);
2289
2290  case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
2291  case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
2292  case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
2293  case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
2294  case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
2295  case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
2296  case Hexagon::MEMw_ORr_indexed_MEM_V4 :
2297  case Hexagon::MEMw_ADDSUBi_MEM_V4 :
2298  case Hexagon::MEMw_ADDi_MEM_V4 :
2299  case Hexagon::MEMw_SUBi_MEM_V4 :
2300  case Hexagon::MEMw_ADDr_MEM_V4 :
2301  case Hexagon::MEMw_SUBr_MEM_V4 :
2302  case Hexagon::MEMw_ANDr_MEM_V4 :
2303  case Hexagon::MEMw_ORr_MEM_V4 :
2304    assert ((Offset % 4) == 0 && "MEMOPw offset is not aligned correctly." );
2305    return (0 <= Offset && Offset <= 255);
2306
2307  case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
2308  case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
2309  case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
2310  case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
2311  case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
2312  case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
2313  case Hexagon::MEMh_ORr_indexed_MEM_V4 :
2314  case Hexagon::MEMh_ADDSUBi_MEM_V4 :
2315  case Hexagon::MEMh_ADDi_MEM_V4 :
2316  case Hexagon::MEMh_SUBi_MEM_V4 :
2317  case Hexagon::MEMh_ADDr_MEM_V4 :
2318  case Hexagon::MEMh_SUBr_MEM_V4 :
2319  case Hexagon::MEMh_ANDr_MEM_V4 :
2320  case Hexagon::MEMh_ORr_MEM_V4 :
2321    assert ((Offset % 2) == 0 && "MEMOPh offset is not aligned correctly." );
2322    return (0 <= Offset && Offset <= 127);
2323
2324  case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
2325  case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
2326  case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
2327  case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
2328  case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
2329  case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
2330  case Hexagon::MEMb_ORr_indexed_MEM_V4 :
2331  case Hexagon::MEMb_ADDSUBi_MEM_V4 :
2332  case Hexagon::MEMb_ADDi_MEM_V4 :
2333  case Hexagon::MEMb_SUBi_MEM_V4 :
2334  case Hexagon::MEMb_ADDr_MEM_V4 :
2335  case Hexagon::MEMb_SUBr_MEM_V4 :
2336  case Hexagon::MEMb_ANDr_MEM_V4 :
2337  case Hexagon::MEMb_ORr_MEM_V4 :
2338    return (0 <= Offset && Offset <= 63);
2339
2340  // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
2341  // any size. Later pass knows how to handle it.
2342  case Hexagon::STriw_pred:
2343  case Hexagon::LDriw_pred:
2344    return true;
2345
2346  // INLINEASM is very special.
2347  case Hexagon::INLINEASM:
2348    return true;
2349  }
2350
2351  llvm_unreachable("No offset range is defined for this opcode. "
2352                   "Please define it in the above switch statement!");
2353}
2354
2355
2356//
2357// Check if the Offset is a valid auto-inc imm by Load/Store Type.
2358//
2359bool HexagonInstrInfo::
2360isValidAutoIncImm(const EVT VT, const int Offset) const {
2361
2362  if (VT == MVT::i64) {
2363      return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
2364              Offset <= Hexagon_MEMD_AUTOINC_MAX &&
2365              (Offset & 0x7) == 0);
2366  }
2367  if (VT == MVT::i32) {
2368      return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
2369              Offset <= Hexagon_MEMW_AUTOINC_MAX &&
2370              (Offset & 0x3) == 0);
2371  }
2372  if (VT == MVT::i16) {
2373      return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
2374              Offset <= Hexagon_MEMH_AUTOINC_MAX &&
2375              (Offset & 0x1) == 0);
2376  }
2377  if (VT == MVT::i8) {
2378      return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
2379              Offset <= Hexagon_MEMB_AUTOINC_MAX);
2380  }
2381  llvm_unreachable("Not an auto-inc opc!");
2382}
2383
2384
2385bool HexagonInstrInfo::
2386isMemOp(const MachineInstr *MI) const {
2387  switch (MI->getOpcode())
2388  {
2389    case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
2390    case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
2391    case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
2392    case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
2393    case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
2394    case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
2395    case Hexagon::MEMw_ORr_indexed_MEM_V4 :
2396    case Hexagon::MEMw_ADDSUBi_MEM_V4 :
2397    case Hexagon::MEMw_ADDi_MEM_V4 :
2398    case Hexagon::MEMw_SUBi_MEM_V4 :
2399    case Hexagon::MEMw_ADDr_MEM_V4 :
2400    case Hexagon::MEMw_SUBr_MEM_V4 :
2401    case Hexagon::MEMw_ANDr_MEM_V4 :
2402    case Hexagon::MEMw_ORr_MEM_V4 :
2403    case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
2404    case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
2405    case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
2406    case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
2407    case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
2408    case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
2409    case Hexagon::MEMh_ORr_indexed_MEM_V4 :
2410    case Hexagon::MEMh_ADDSUBi_MEM_V4 :
2411    case Hexagon::MEMh_ADDi_MEM_V4 :
2412    case Hexagon::MEMh_SUBi_MEM_V4 :
2413    case Hexagon::MEMh_ADDr_MEM_V4 :
2414    case Hexagon::MEMh_SUBr_MEM_V4 :
2415    case Hexagon::MEMh_ANDr_MEM_V4 :
2416    case Hexagon::MEMh_ORr_MEM_V4 :
2417    case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
2418    case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
2419    case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
2420    case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
2421    case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
2422    case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
2423    case Hexagon::MEMb_ORr_indexed_MEM_V4 :
2424    case Hexagon::MEMb_ADDSUBi_MEM_V4 :
2425    case Hexagon::MEMb_ADDi_MEM_V4 :
2426    case Hexagon::MEMb_SUBi_MEM_V4 :
2427    case Hexagon::MEMb_ADDr_MEM_V4 :
2428    case Hexagon::MEMb_SUBr_MEM_V4 :
2429    case Hexagon::MEMb_ANDr_MEM_V4 :
2430    case Hexagon::MEMb_ORr_MEM_V4 :
2431    return true;
2432  }
2433  return false;
2434}
2435
2436
2437bool HexagonInstrInfo::
2438isSpillPredRegOp(const MachineInstr *MI) const {
2439  switch (MI->getOpcode())
2440  {
2441    case Hexagon::STriw_pred :
2442    case Hexagon::LDriw_pred :
2443    return true;
2444  }
2445  return false;
2446}
2447
2448bool HexagonInstrInfo::
2449isConditionalTransfer (const MachineInstr *MI) const {
2450  switch (MI->getOpcode()) {
2451    case Hexagon::TFR_cPt:
2452    case Hexagon::TFR_cNotPt:
2453    case Hexagon::TFRI_cPt:
2454    case Hexagon::TFRI_cNotPt:
2455    case Hexagon::TFR_cdnPt:
2456    case Hexagon::TFR_cdnNotPt:
2457    case Hexagon::TFRI_cdnPt:
2458    case Hexagon::TFRI_cdnNotPt:
2459      return true;
2460
2461    default:
2462      return false;
2463  }
2464  return false;
2465}
2466
2467bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
2468  const HexagonRegisterInfo& QRI = getRegisterInfo();
2469  switch (MI->getOpcode())
2470  {
2471    case Hexagon::ADD_ri_cPt:
2472    case Hexagon::ADD_ri_cNotPt:
2473    case Hexagon::ADD_rr_cPt:
2474    case Hexagon::ADD_rr_cNotPt:
2475    case Hexagon::XOR_rr_cPt:
2476    case Hexagon::XOR_rr_cNotPt:
2477    case Hexagon::AND_rr_cPt:
2478    case Hexagon::AND_rr_cNotPt:
2479    case Hexagon::OR_rr_cPt:
2480    case Hexagon::OR_rr_cNotPt:
2481    case Hexagon::SUB_rr_cPt:
2482    case Hexagon::SUB_rr_cNotPt:
2483    case Hexagon::COMBINE_rr_cPt:
2484    case Hexagon::COMBINE_rr_cNotPt:
2485      return true;
2486    case Hexagon::ASLH_cPt_V4:
2487    case Hexagon::ASLH_cNotPt_V4:
2488    case Hexagon::ASRH_cPt_V4:
2489    case Hexagon::ASRH_cNotPt_V4:
2490    case Hexagon::SXTB_cPt_V4:
2491    case Hexagon::SXTB_cNotPt_V4:
2492    case Hexagon::SXTH_cPt_V4:
2493    case Hexagon::SXTH_cNotPt_V4:
2494    case Hexagon::ZXTB_cPt_V4:
2495    case Hexagon::ZXTB_cNotPt_V4:
2496    case Hexagon::ZXTH_cPt_V4:
2497    case Hexagon::ZXTH_cNotPt_V4:
2498      return QRI.Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
2499
2500    default:
2501      return false;
2502  }
2503}
2504
2505bool HexagonInstrInfo::
2506isConditionalLoad (const MachineInstr* MI) const {
2507  const HexagonRegisterInfo& QRI = getRegisterInfo();
2508  switch (MI->getOpcode())
2509  {
2510    case Hexagon::LDrid_cPt :
2511    case Hexagon::LDrid_cNotPt :
2512    case Hexagon::LDrid_indexed_cPt :
2513    case Hexagon::LDrid_indexed_cNotPt :
2514    case Hexagon::LDriw_cPt :
2515    case Hexagon::LDriw_cNotPt :
2516    case Hexagon::LDriw_indexed_cPt :
2517    case Hexagon::LDriw_indexed_cNotPt :
2518    case Hexagon::LDrih_cPt :
2519    case Hexagon::LDrih_cNotPt :
2520    case Hexagon::LDrih_indexed_cPt :
2521    case Hexagon::LDrih_indexed_cNotPt :
2522    case Hexagon::LDrib_cPt :
2523    case Hexagon::LDrib_cNotPt :
2524    case Hexagon::LDrib_indexed_cPt :
2525    case Hexagon::LDrib_indexed_cNotPt :
2526    case Hexagon::LDriuh_cPt :
2527    case Hexagon::LDriuh_cNotPt :
2528    case Hexagon::LDriuh_indexed_cPt :
2529    case Hexagon::LDriuh_indexed_cNotPt :
2530    case Hexagon::LDriub_cPt :
2531    case Hexagon::LDriub_cNotPt :
2532    case Hexagon::LDriub_indexed_cPt :
2533    case Hexagon::LDriub_indexed_cNotPt :
2534      return true;
2535    case Hexagon::POST_LDrid_cPt :
2536    case Hexagon::POST_LDrid_cNotPt :
2537    case Hexagon::POST_LDriw_cPt :
2538    case Hexagon::POST_LDriw_cNotPt :
2539    case Hexagon::POST_LDrih_cPt :
2540    case Hexagon::POST_LDrih_cNotPt :
2541    case Hexagon::POST_LDrib_cPt :
2542    case Hexagon::POST_LDrib_cNotPt :
2543    case Hexagon::POST_LDriuh_cPt :
2544    case Hexagon::POST_LDriuh_cNotPt :
2545    case Hexagon::POST_LDriub_cPt :
2546    case Hexagon::POST_LDriub_cNotPt :
2547      return QRI.Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
2548    case Hexagon::LDrid_indexed_cPt_V4 :
2549    case Hexagon::LDrid_indexed_cNotPt_V4 :
2550    case Hexagon::LDrid_indexed_shl_cPt_V4 :
2551    case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
2552    case Hexagon::LDrib_indexed_cPt_V4 :
2553    case Hexagon::LDrib_indexed_cNotPt_V4 :
2554    case Hexagon::LDrib_indexed_shl_cPt_V4 :
2555    case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
2556    case Hexagon::LDriub_indexed_cPt_V4 :
2557    case Hexagon::LDriub_indexed_cNotPt_V4 :
2558    case Hexagon::LDriub_indexed_shl_cPt_V4 :
2559    case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
2560    case Hexagon::LDrih_indexed_cPt_V4 :
2561    case Hexagon::LDrih_indexed_cNotPt_V4 :
2562    case Hexagon::LDrih_indexed_shl_cPt_V4 :
2563    case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
2564    case Hexagon::LDriuh_indexed_cPt_V4 :
2565    case Hexagon::LDriuh_indexed_cNotPt_V4 :
2566    case Hexagon::LDriuh_indexed_shl_cPt_V4 :
2567    case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
2568    case Hexagon::LDriw_indexed_cPt_V4 :
2569    case Hexagon::LDriw_indexed_cNotPt_V4 :
2570    case Hexagon::LDriw_indexed_shl_cPt_V4 :
2571    case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
2572      return QRI.Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
2573    default:
2574      return false;
2575  }
2576}
2577
2578// Returns true if an instruction is a conditional store.
2579//
2580// Note: It doesn't include conditional new-value stores as they can't be
2581// converted to .new predicate.
2582//
2583//               p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
2584//                ^           ^
2585//               /             \ (not OK. it will cause new-value store to be
2586//              /               X conditional on p0.new while R2 producer is
2587//             /                 \ on p0)
2588//            /                   \.
2589//     p.new store                 p.old NV store
2590// [if(p0.new)memw(R0+#0)=R2]    [if(p0)memw(R0+#0)=R2.new]
2591//            ^                  ^
2592//             \                /
2593//              \              /
2594//               \            /
2595//                 p.old store
2596//             [if (p0)memw(R0+#0)=R2]
2597//
2598// The above diagram shows the steps involoved in the conversion of a predicated
2599// store instruction to its .new predicated new-value form.
2600//
2601// The following set of instructions further explains the scenario where
2602// conditional new-value store becomes invalid when promoted to .new predicate
2603// form.
2604//
2605// { 1) if (p0) r0 = add(r1, r2)
2606//   2) p0 = cmp.eq(r3, #0) }
2607//
2608//   3) if (p0) memb(r1+#0) = r0  --> this instruction can't be grouped with
2609// the first two instructions because in instr 1, r0 is conditional on old value
2610// of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
2611// is not valid for new-value stores.
2612bool HexagonInstrInfo::
2613isConditionalStore (const MachineInstr* MI) const {
2614  const HexagonRegisterInfo& QRI = getRegisterInfo();
2615  switch (MI->getOpcode())
2616  {
2617    case Hexagon::STrib_imm_cPt_V4 :
2618    case Hexagon::STrib_imm_cNotPt_V4 :
2619    case Hexagon::STrib_indexed_shl_cPt_V4 :
2620    case Hexagon::STrib_indexed_shl_cNotPt_V4 :
2621    case Hexagon::STrib_cPt :
2622    case Hexagon::STrib_cNotPt :
2623    case Hexagon::POST_STbri_cPt :
2624    case Hexagon::POST_STbri_cNotPt :
2625    case Hexagon::STrid_indexed_cPt :
2626    case Hexagon::STrid_indexed_cNotPt :
2627    case Hexagon::STrid_indexed_shl_cPt_V4 :
2628    case Hexagon::POST_STdri_cPt :
2629    case Hexagon::POST_STdri_cNotPt :
2630    case Hexagon::STrih_cPt :
2631    case Hexagon::STrih_cNotPt :
2632    case Hexagon::STrih_indexed_cPt :
2633    case Hexagon::STrih_indexed_cNotPt :
2634    case Hexagon::STrih_imm_cPt_V4 :
2635    case Hexagon::STrih_imm_cNotPt_V4 :
2636    case Hexagon::STrih_indexed_shl_cPt_V4 :
2637    case Hexagon::STrih_indexed_shl_cNotPt_V4 :
2638    case Hexagon::POST_SThri_cPt :
2639    case Hexagon::POST_SThri_cNotPt :
2640    case Hexagon::STriw_cPt :
2641    case Hexagon::STriw_cNotPt :
2642    case Hexagon::STriw_indexed_cPt :
2643    case Hexagon::STriw_indexed_cNotPt :
2644    case Hexagon::STriw_imm_cPt_V4 :
2645    case Hexagon::STriw_imm_cNotPt_V4 :
2646    case Hexagon::STriw_indexed_shl_cPt_V4 :
2647    case Hexagon::STriw_indexed_shl_cNotPt_V4 :
2648    case Hexagon::POST_STwri_cPt :
2649    case Hexagon::POST_STwri_cNotPt :
2650      return QRI.Subtarget.hasV4TOps();
2651
2652    // V4 global address store before promoting to dot new.
2653    case Hexagon::STrid_GP_cPt_V4 :
2654    case Hexagon::STrid_GP_cNotPt_V4 :
2655    case Hexagon::STrib_GP_cPt_V4 :
2656    case Hexagon::STrib_GP_cNotPt_V4 :
2657    case Hexagon::STrih_GP_cPt_V4 :
2658    case Hexagon::STrih_GP_cNotPt_V4 :
2659    case Hexagon::STriw_GP_cPt_V4 :
2660    case Hexagon::STriw_GP_cNotPt_V4 :
2661    case Hexagon::STd_GP_cPt_V4 :
2662    case Hexagon::STd_GP_cNotPt_V4 :
2663    case Hexagon::STb_GP_cPt_V4 :
2664    case Hexagon::STb_GP_cNotPt_V4 :
2665    case Hexagon::STh_GP_cPt_V4 :
2666    case Hexagon::STh_GP_cNotPt_V4 :
2667    case Hexagon::STw_GP_cPt_V4 :
2668    case Hexagon::STw_GP_cNotPt_V4 :
2669      return QRI.Subtarget.hasV4TOps();
2670
2671    // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
2672    // from the "Conditional Store" list. Because a predicated new value store
2673    // would NOT be promoted to a double dot new store. See diagram below:
2674    // This function returns yes for those stores that are predicated but not
2675    // yet promoted to predicate dot new instructions.
2676    //
2677    //                          +---------------------+
2678    //                    /-----| if (p0) memw(..)=r0 |---------\~
2679    //                   ||     +---------------------+         ||
2680    //          promote  ||       /\       /\                   ||  promote
2681    //                   ||      /||\     /||\                  ||
2682    //                  \||/    demote     ||                  \||/
2683    //                   \/       ||       ||                   \/
2684    //       +-------------------------+   ||   +-------------------------+
2685    //       | if (p0.new) memw(..)=r0 |   ||   | if (p0) memw(..)=r0.new |
2686    //       +-------------------------+   ||   +-------------------------+
2687    //                        ||           ||         ||
2688    //                        ||         demote      \||/
2689    //                      promote        ||         \/ NOT possible
2690    //                        ||           ||         /\~
2691    //                       \||/          ||        /||\~
2692    //                        \/           ||         ||
2693    //                      +-----------------------------+
2694    //                      | if (p0.new) memw(..)=r0.new |
2695    //                      +-----------------------------+
2696    //                           Double Dot New Store
2697    //
2698
2699    default:
2700      return false;
2701
2702  }
2703  return false;
2704}
2705
2706
2707
2708DFAPacketizer *HexagonInstrInfo::
2709CreateTargetScheduleState(const TargetMachine *TM,
2710                           const ScheduleDAG *DAG) const {
2711  const InstrItineraryData *II = TM->getInstrItineraryData();
2712  return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
2713}
2714
2715bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
2716                                            const MachineBasicBlock *MBB,
2717                                            const MachineFunction &MF) const {
2718  // Debug info is never a scheduling boundary. It's necessary to be explicit
2719  // due to the special treatment of IT instructions below, otherwise a
2720  // dbg_value followed by an IT will result in the IT instruction being
2721  // considered a scheduling hazard, which is wrong. It should be the actual
2722  // instruction preceding the dbg_value instruction(s), just like it is
2723  // when debug info is not present.
2724  if (MI->isDebugValue())
2725    return false;
2726
2727  // Terminators and labels can't be scheduled around.
2728  if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm())
2729    return true;
2730
2731  return false;
2732}
2733