ARMMCTargetDesc.cpp revision 288943 
1//===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file provides ARM specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMBaseInfo.h"
15#include "ARMMCAsmInfo.h"
16#include "ARMMCTargetDesc.h"
17#include "InstPrinter/ARMInstPrinter.h"
18#include "llvm/ADT/Triple.h"
19#include "llvm/MC/MCCodeGenInfo.h"
20#include "llvm/MC/MCELFStreamer.h"
21#include "llvm/MC/MCInstrAnalysis.h"
22#include "llvm/MC/MCInstrInfo.h"
23#include "llvm/MC/MCRegisterInfo.h"
24#include "llvm/MC/MCStreamer.h"
25#include "llvm/MC/MCSubtargetInfo.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/TargetRegistry.h"
28
29using namespace llvm;
30
31#define GET_REGINFO_MC_DESC
32#include "ARMGenRegisterInfo.inc"
33
34static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
35                                  std::string &Info) {
36  if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
37      (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
38      (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
39      // Checks for the deprecated CP15ISB encoding:
40      // mcr p15, #0, rX, c7, c5, #4
41      (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
42    if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
43      if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
44        Info = "deprecated since v7, use 'isb'";
45        return true;
46      }
47
48      // Checks for the deprecated CP15DSB encoding:
49      // mcr p15, #0, rX, c7, c10, #4
50      if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
51        Info = "deprecated since v7, use 'dsb'";
52        return true;
53      }
54    }
55    // Checks for the deprecated CP15DMB encoding:
56    // mcr p15, #0, rX, c7, c10, #5
57    if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
58        (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
59      Info = "deprecated since v7, use 'dmb'";
60      return true;
61    }
62  }
63  return false;
64}
65
66static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
67                                 std::string &Info) {
68  if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
69      MI.getOperand(1).getImm() != 8) {
70    Info = "applying IT instruction to more than one subsequent instruction is "
71           "deprecated";
72    return true;
73  }
74
75  return false;
76}
77
78static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
79                                       std::string &Info) {
80  assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
81         "cannot predicate thumb instructions");
82
83  assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
84  for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
85    assert(MI.getOperand(OI).isReg() && "expected register");
86    if (MI.getOperand(OI).getReg() == ARM::SP ||
87        MI.getOperand(OI).getReg() == ARM::PC) {
88      Info = "use of SP or PC in the list is deprecated";
89      return true;
90    }
91  }
92  return false;
93}
94
95static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
96                                      std::string &Info) {
97  assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
98         "cannot predicate thumb instructions");
99
100  assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
101  bool ListContainsPC = false, ListContainsLR = false;
102  for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
103    assert(MI.getOperand(OI).isReg() && "expected register");
104    switch (MI.getOperand(OI).getReg()) {
105    default:
106      break;
107    case ARM::LR:
108      ListContainsLR = true;
109      break;
110    case ARM::PC:
111      ListContainsPC = true;
112      break;
113    case ARM::SP:
114      Info = "use of SP in the list is deprecated";
115      return true;
116    }
117  }
118
119  if (ListContainsPC && ListContainsLR) {
120    Info = "use of LR and PC simultaneously in the list is deprecated";
121    return true;
122  }
123
124  return false;
125}
126
127#define GET_INSTRINFO_MC_DESC
128#include "ARMGenInstrInfo.inc"
129
130#define GET_SUBTARGETINFO_MC_DESC
131#include "ARMGenSubtargetInfo.inc"
132
133std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
134  bool isThumb =
135      TT.getArch() == Triple::thumb || TT.getArch() == Triple::thumbeb;
136
137  bool NoCPU = CPU == "generic" || CPU.empty();
138  std::string ARMArchFeature;
139  switch (TT.getSubArch()) {
140  default:
141    llvm_unreachable("invalid sub-architecture for ARM");
142  case Triple::ARMSubArch_v8:
143    if (NoCPU)
144      // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
145      //      FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
146      //      FeatureT2XtPk, FeatureCrypto, FeatureCRC
147      ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
148                       "+trustzone,+t2xtpk,+crypto,+crc";
149    else
150      // Use CPU to figure out the exact features
151      ARMArchFeature = "+v8";
152    break;
153  case Triple::ARMSubArch_v8_1a:
154    if (NoCPU)
155      // v8.1a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
156      //      FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
157      //      FeatureT2XtPk, FeatureCrypto, FeatureCRC, FeatureV8_1a
158      ARMArchFeature = "+v8.1a,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
159                       "+trustzone,+t2xtpk,+crypto,+crc";
160    else
161      // Use CPU to figure out the exact features
162      ARMArchFeature = "+v8.1a";
163    break;
164  case Triple::ARMSubArch_v7m:
165    isThumb = true;
166    if (NoCPU)
167      // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
168      ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
169    else
170      // Use CPU to figure out the exact features.
171      ARMArchFeature = "+v7";
172    break;
173  case Triple::ARMSubArch_v7em:
174    if (NoCPU)
175      // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
176      //       FeatureT2XtPk, FeatureMClass
177      ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,+t2xtpk,+mclass";
178    else
179      // Use CPU to figure out the exact features.
180      ARMArchFeature = "+v7";
181    break;
182  case Triple::ARMSubArch_v7s:
183    if (NoCPU)
184      // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
185      //      Swift
186      ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
187    else
188      // Use CPU to figure out the exact features.
189      ARMArchFeature = "+v7";
190    break;
191  case Triple::ARMSubArch_v7:
192    // v7 CPUs have lots of different feature sets. If no CPU is specified,
193    // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
194    // the "minimum" feature set and use CPU string to figure out the exact
195    // features.
196    if (NoCPU)
197      // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
198      ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
199    else
200      // Use CPU to figure out the exact features.
201      ARMArchFeature = "+v7";
202    break;
203  case Triple::ARMSubArch_v6t2:
204    ARMArchFeature = "+v6t2";
205    break;
206  case Triple::ARMSubArch_v6k:
207    ARMArchFeature = "+v6k";
208    break;
209  case Triple::ARMSubArch_v6m:
210    isThumb = true;
211    if (NoCPU)
212      // v6m: FeatureNoARM, FeatureMClass
213      ARMArchFeature = "+v6m,+noarm,+mclass";
214    else
215      ARMArchFeature = "+v6";
216    break;
217  case Triple::ARMSubArch_v6:
218    ARMArchFeature = "+v6";
219    break;
220  case Triple::ARMSubArch_v5te:
221    ARMArchFeature = "+v5te";
222    break;
223  case Triple::ARMSubArch_v5:
224    ARMArchFeature = "+v5t";
225    break;
226  case Triple::ARMSubArch_v4t:
227    ARMArchFeature = "+v4t";
228    break;
229  case Triple::NoSubArch:
230    break;
231  }
232
233  if (isThumb) {
234    if (ARMArchFeature.empty())
235      ARMArchFeature = "+thumb-mode";
236    else
237      ARMArchFeature += ",+thumb-mode";
238  }
239
240  if (TT.isOSNaCl()) {
241    if (ARMArchFeature.empty())
242      ARMArchFeature = "+nacl-trap";
243    else
244      ARMArchFeature += ",+nacl-trap";
245  }
246
247  return ARMArchFeature;
248}
249
250MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
251                                                  StringRef CPU, StringRef FS) {
252  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
253  if (!FS.empty()) {
254    if (!ArchFS.empty())
255      ArchFS = (Twine(ArchFS) + "," + FS).str();
256    else
257      ArchFS = FS;
258  }
259
260  return createARMMCSubtargetInfoImpl(TT, CPU, ArchFS);
261}
262
263static MCInstrInfo *createARMMCInstrInfo() {
264  MCInstrInfo *X = new MCInstrInfo();
265  InitARMMCInstrInfo(X);
266  return X;
267}
268
269static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
270  MCRegisterInfo *X = new MCRegisterInfo();
271  InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
272  return X;
273}
274
275static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI,
276                                     const Triple &TheTriple) {
277  MCAsmInfo *MAI;
278  if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
279    MAI = new ARMMCAsmInfoDarwin(TheTriple);
280  else if (TheTriple.isWindowsMSVCEnvironment())
281    MAI = new ARMCOFFMCAsmInfoMicrosoft();
282  else if (TheTriple.isOSWindows())
283    MAI = new ARMCOFFMCAsmInfoGNU();
284  else
285    MAI = new ARMELFMCAsmInfo(TheTriple);
286
287  unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
288  MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
289
290  return MAI;
291}
292
293static MCCodeGenInfo *createARMMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
294                                             CodeModel::Model CM,
295                                             CodeGenOpt::Level OL) {
296  MCCodeGenInfo *X = new MCCodeGenInfo();
297  if (RM == Reloc::Default) {
298    // Default relocation model on Darwin is PIC, not DynamicNoPIC.
299    RM = TT.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
300  }
301  X->initMCCodeGenInfo(RM, CM, OL);
302  return X;
303}
304
305static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
306                                     MCAsmBackend &MAB, raw_pwrite_stream &OS,
307                                     MCCodeEmitter *Emitter, bool RelaxAll) {
308  return createARMELFStreamer(Ctx, MAB, OS, Emitter, false,
309                              T.getArch() == Triple::thumb);
310}
311
312static MCStreamer *createARMMachOStreamer(MCContext &Ctx, MCAsmBackend &MAB,
313                                          raw_pwrite_stream &OS,
314                                          MCCodeEmitter *Emitter, bool RelaxAll,
315                                          bool DWARFMustBeAtTheEnd) {
316  return createMachOStreamer(Ctx, MAB, OS, Emitter, false, DWARFMustBeAtTheEnd);
317}
318
319static MCInstPrinter *createARMMCInstPrinter(const Triple &T,
320                                             unsigned SyntaxVariant,
321                                             const MCAsmInfo &MAI,
322                                             const MCInstrInfo &MII,
323                                             const MCRegisterInfo &MRI) {
324  if (SyntaxVariant == 0)
325    return new ARMInstPrinter(MAI, MII, MRI);
326  return nullptr;
327}
328
329static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT,
330                                                   MCContext &Ctx) {
331  if (TT.isOSBinFormatMachO())
332    return createARMMachORelocationInfo(Ctx);
333  // Default to the stock relocation info.
334  return llvm::createMCRelocationInfo(TT, Ctx);
335}
336
337namespace {
338
339class ARMMCInstrAnalysis : public MCInstrAnalysis {
340public:
341  ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
342
343  bool isUnconditionalBranch(const MCInst &Inst) const override {
344    // BCCs with the "always" predicate are unconditional branches.
345    if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
346      return true;
347    return MCInstrAnalysis::isUnconditionalBranch(Inst);
348  }
349
350  bool isConditionalBranch(const MCInst &Inst) const override {
351    // BCCs with the "always" predicate are unconditional branches.
352    if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
353      return false;
354    return MCInstrAnalysis::isConditionalBranch(Inst);
355  }
356
357  bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
358                      uint64_t Size, uint64_t &Target) const override {
359    // We only handle PCRel branches for now.
360    if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
361      return false;
362
363    int64_t Imm = Inst.getOperand(0).getImm();
364    // FIXME: This is not right for thumb.
365    Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
366    return true;
367  }
368};
369
370}
371
372static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
373  return new ARMMCInstrAnalysis(Info);
374}
375
376// Force static initialization.
377extern "C" void LLVMInitializeARMTargetMC() {
378  for (Target *T : {&TheARMLETarget, &TheARMBETarget, &TheThumbLETarget,
379                    &TheThumbBETarget}) {
380    // Register the MC asm info.
381    RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo);
382
383    // Register the MC codegen info.
384    TargetRegistry::RegisterMCCodeGenInfo(*T, createARMMCCodeGenInfo);
385
386    // Register the MC instruction info.
387    TargetRegistry::RegisterMCInstrInfo(*T, createARMMCInstrInfo);
388
389    // Register the MC register info.
390    TargetRegistry::RegisterMCRegInfo(*T, createARMMCRegisterInfo);
391
392    // Register the MC subtarget info.
393    TargetRegistry::RegisterMCSubtargetInfo(*T,
394                                            ARM_MC::createARMMCSubtargetInfo);
395
396    // Register the MC instruction analyzer.
397    TargetRegistry::RegisterMCInstrAnalysis(*T, createARMMCInstrAnalysis);
398
399    TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
400    TargetRegistry::RegisterCOFFStreamer(*T, createARMWinCOFFStreamer);
401    TargetRegistry::RegisterMachOStreamer(*T, createARMMachOStreamer);
402
403    // Register the obj target streamer.
404    TargetRegistry::RegisterObjectTargetStreamer(*T,
405                                                 createARMObjectTargetStreamer);
406
407    // Register the asm streamer.
408    TargetRegistry::RegisterAsmTargetStreamer(*T, createARMTargetAsmStreamer);
409
410    // Register the null TargetStreamer.
411    TargetRegistry::RegisterNullTargetStreamer(*T, createARMNullTargetStreamer);
412
413    // Register the MCInstPrinter.
414    TargetRegistry::RegisterMCInstPrinter(*T, createARMMCInstPrinter);
415
416    // Register the MC relocation info.
417    TargetRegistry::RegisterMCRelocationInfo(*T, createARMMCRelocationInfo);
418  }
419
420  // Register the MC Code Emitter
421  for (Target *T : {&TheARMLETarget, &TheThumbLETarget})
422    TargetRegistry::RegisterMCCodeEmitter(*T, createARMLEMCCodeEmitter);
423  for (Target *T : {&TheARMBETarget, &TheThumbBETarget})
424    TargetRegistry::RegisterMCCodeEmitter(*T, createARMBEMCCodeEmitter);
425
426  // Register the asm backend.
427  TargetRegistry::RegisterMCAsmBackend(TheARMLETarget, createARMLEAsmBackend);
428  TargetRegistry::RegisterMCAsmBackend(TheARMBETarget, createARMBEAsmBackend);
429  TargetRegistry::RegisterMCAsmBackend(TheThumbLETarget,
430                                       createThumbLEAsmBackend);
431  TargetRegistry::RegisterMCAsmBackend(TheThumbBETarget,
432                                       createThumbBEAsmBackend);
433}
434