ARMAddressingModes.h revision 226584
1205407Srdivacky//===- ARMAddressingModes.h - ARM Addressing Modes --------------*- C++ -*-===// 2205407Srdivacky// 3205407Srdivacky// The LLVM Compiler Infrastructure 4205407Srdivacky// 5205407Srdivacky// This file is distributed under the University of Illinois Open Source 6205407Srdivacky// License. See LICENSE.TXT for details. 7205407Srdivacky// 8205407Srdivacky//===----------------------------------------------------------------------===// 9205407Srdivacky// 10218893Sdim// This file contains the ARM addressing mode implementation stuff. 11205407Srdivacky// 12205407Srdivacky//===----------------------------------------------------------------------===// 13205407Srdivacky 14226633Sdim#ifndef LLVM_TARGET_ARM_ARMADDRESSINGMODES_H 15206083Srdivacky#define LLVM_TARGET_ARM_ARMADDRESSINGMODES_H 16205407Srdivacky 17234353Sdim#include "llvm/ADT/APFloat.h" 18205407Srdivacky#include "llvm/ADT/APInt.h" 19205407Srdivacky#include "llvm/Support/MathExtras.h" 20205407Srdivacky#include <cassert> 21208599Srdivacky 22205407Srdivackynamespace llvm { 23218893Sdim 24239462Sdim/// ARM_AM - ARM Addressing Mode Stuff 25205407Srdivackynamespace ARM_AM { 26205407Srdivacky enum ShiftOpc { 27205407Srdivacky no_shift = 0, 28205407Srdivacky asr, 29218893Sdim lsl, 30205407Srdivacky lsr, 31224145Sdim ror, 32224145Sdim rrx 33208599Srdivacky }; 34208599Srdivacky 35208599Srdivacky enum AddrOpc { 36208599Srdivacky sub = 0, 37208599Srdivacky add 38208599Srdivacky }; 39208599Srdivacky 40208599Srdivacky static inline const char *getAddrOpcStr(AddrOpc Op) { 41208599Srdivacky return Op == sub ? "-" : ""; 42208599Srdivacky } 43208599Srdivacky 44208599Srdivacky static inline const char *getShiftOpcStr(ShiftOpc Op) { 45208599Srdivacky switch (Op) { 46224145Sdim default: assert(0 && "Unknown shift opc!"); 47224145Sdim case ARM_AM::asr: return "asr"; 48224145Sdim case ARM_AM::lsl: return "lsl"; 49224145Sdim case ARM_AM::lsr: return "lsr"; 50224145Sdim case ARM_AM::ror: return "ror"; 51205407Srdivacky case ARM_AM::rrx: return "rrx"; 52224145Sdim } 53224145Sdim } 54224145Sdim 55205407Srdivacky static inline unsigned getShiftOpcEncoding(ShiftOpc Op) { 56224145Sdim switch (Op) { 57224145Sdim default: assert(0 && "Unknown shift opc!"); 58205407Srdivacky case ARM_AM::asr: return 2; 59224145Sdim case ARM_AM::lsl: return 0; 60224145Sdim case ARM_AM::lsr: return 1; 61224145Sdim case ARM_AM::ror: return 3; 62224145Sdim } 63224145Sdim } 64218893Sdim 65224145Sdim enum AMSubMode { 66224145Sdim bad_am_submode = 0, 67224145Sdim ia, 68205407Srdivacky ib, 69224145Sdim da, 70224145Sdim db 71243830Sdim }; 72243830Sdim 73243830Sdim static inline const char *getAMSubModeStr(AMSubMode Mode) { 74243830Sdim switch (Mode) { 75243830Sdim default: assert(0 && "Unknown addressing sub-mode!"); 76224145Sdim case ARM_AM::ia: return "ia"; 77224145Sdim case ARM_AM::ib: return "ib"; 78224145Sdim case ARM_AM::da: return "da"; 79224145Sdim case ARM_AM::db: return "db"; 80205407Srdivacky } 81224145Sdim } 82224145Sdim 83224145Sdim /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits. 84224145Sdim /// 85224145Sdim static inline unsigned rotr32(unsigned Val, unsigned Amt) { 86224145Sdim assert(Amt < 32 && "Invalid rotate amount"); 87224145Sdim return (Val >> Amt) | (Val << ((32-Amt)&31)); 88205407Srdivacky } 89224145Sdim 90224145Sdim /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits. 91224145Sdim /// 92224145Sdim static inline unsigned rotl32(unsigned Val, unsigned Amt) { 93224145Sdim assert(Amt < 32 && "Invalid rotate amount"); 94224145Sdim return (Val << Amt) | (Val >> ((32-Amt)&31)); 95224145Sdim } 96224145Sdim 97218893Sdim //===--------------------------------------------------------------------===// 98205407Srdivacky // Addressing Mode #1: shift_operand with registers 99224145Sdim //===--------------------------------------------------------------------===// 100224145Sdim // 101224145Sdim // This 'addressing mode' is used for arithmetic instructions. It can 102218893Sdim // represent things like: 103224145Sdim // reg 104224145Sdim // reg [asr|lsl|lsr|ror|rrx] reg 105224145Sdim // reg [asr|lsl|lsr|ror|rrx] imm 106224145Sdim // 107224145Sdim // This is stored three operands [rega, regb, opc]. The first is the base 108224145Sdim // reg, the second is the shift amount (or reg0 if not present or imm). The 109221345Sdim // third operand encodes the shift opcode and the imm if a reg isn't present. 110224145Sdim // 111224145Sdim static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { 112224145Sdim return ShOp | (Imm << 3); 113224145Sdim } 114224145Sdim static inline unsigned getSORegOffset(unsigned Op) { 115221345Sdim return Op >> 3; 116224145Sdim } 117224145Sdim static inline ShiftOpc getSORegShOp(unsigned Op) { 118224145Sdim return (ShiftOpc)(Op & 7); 119224145Sdim } 120221345Sdim 121224145Sdim /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return 122224145Sdim /// the 8-bit imm value. 123221345Sdim static inline unsigned getSOImmValImm(unsigned Imm) { 124224145Sdim return Imm & 0xFF; 125224145Sdim } 126218893Sdim /// getSOImmValRot - Given an encoded imm field for the reg/imm form, return 127224145Sdim /// the rotate amount. 128224145Sdim static inline unsigned getSOImmValRot(unsigned Imm) { 129218893Sdim return (Imm >> 8) * 2; 130224145Sdim } 131218893Sdim 132224145Sdim /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand, 133224145Sdim /// computing the rotate amount to use. If this immediate value cannot be 134205407Srdivacky /// handled with a single shifter-op, determine a good rotate amount that will 135224145Sdim /// take a maximal chunk of bits out of the immediate. 136224145Sdim static inline unsigned getSOImmValRotate(unsigned Imm) { 137224145Sdim // 8-bit (or less) immediates are trivially shifter_operands with a rotate 138224145Sdim // of zero. 139224145Sdim if ((Imm & ~255U) == 0) return 0; 140224145Sdim 141218893Sdim // Use CTZ to compute the rotate amount. 142224145Sdim unsigned TZ = CountTrailingZeros_32(Imm); 143224145Sdim 144224145Sdim // Rotate amount must be even. Something like 0x200 must be rotated 8 bits, 145205407Srdivacky // not 9. 146224145Sdim unsigned RotAmt = TZ & ~1; 147224145Sdim 148243830Sdim // If we can handle this spread, return it. 149243830Sdim if ((rotr32(Imm, RotAmt) & ~255U) == 0) 150224145Sdim return (32-RotAmt)&31; // HW rotates right, not left. 151224145Sdim 152224145Sdim // For values like 0xF000000F, we should ignore the low 6 bits, then 153224145Sdim // retry the hunt. 154224145Sdim if (Imm & 63U) { 155224145Sdim unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U); 156218893Sdim unsigned RotAmt2 = TZ2 & ~1; 157224145Sdim if ((rotr32(Imm, RotAmt2) & ~255U) == 0) 158224145Sdim return (32-RotAmt2)&31; // HW rotates right, not left. 159205407Srdivacky } 160224145Sdim 161224145Sdim // Otherwise, we have no way to cover this span of bits with a single 162224145Sdim // shifter_op immediate. Return a chunk of bits that will be useful to 163224145Sdim // handle. 164224145Sdim return (32-RotAmt)&31; // HW rotates right, not left. 165224145Sdim } 166224145Sdim 167205407Srdivacky /// getSOImmVal - Given a 32-bit immediate, if it is something that can fit 168224145Sdim /// into an shifter_operand immediate operand, return the 12-bit encoding for 169224145Sdim /// it. If not, return -1. 170224145Sdim static inline int getSOImmVal(unsigned Arg) { 171224145Sdim // 8-bit (or less) immediates are trivially shifter_operands with a rotate 172224145Sdim // of zero. 173224145Sdim if ((Arg & ~255U) == 0) return Arg; 174224145Sdim 175224145Sdim unsigned RotAmt = getSOImmValRotate(Arg); 176224145Sdim 177224145Sdim // If this cannot be handled with a single shifter_op, bail out. 178224145Sdim if (rotr32(~255U, RotAmt) & Arg) 179205407Srdivacky return -1; 180224145Sdim 181224145Sdim // Encode this correctly. 182224145Sdim return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8); 183224145Sdim } 184205407Srdivacky 185224145Sdim /// isSOImmTwoPartVal - Return true if the specified value can be obtained by 186224145Sdim /// or'ing together two SOImmVal's. 187205407Srdivacky static inline bool isSOImmTwoPartVal(unsigned V) { 188224145Sdim // If this can be handled with a single shifter_op, bail out. 189224145Sdim V = rotr32(~255U, getSOImmValRotate(V)) & V; 190224145Sdim if (V == 0) 191224145Sdim return false; 192224145Sdim 193224145Sdim // If this can be handled with two shifter_op's, accept. 194224145Sdim V = rotr32(~255U, getSOImmValRotate(V)) & V; 195205407Srdivacky return V == 0; 196224145Sdim } 197224145Sdim 198224145Sdim /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, 199224145Sdim /// return the first chunk of it. 200205407Srdivacky static inline unsigned getSOImmTwoPartFirst(unsigned V) { 201205407Srdivacky return rotr32(255U, getSOImmValRotate(V)) & V; 202224145Sdim } 203224145Sdim 204206083Srdivacky /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, 205224145Sdim /// return the second chunk of it. 206224145Sdim static inline unsigned getSOImmTwoPartSecond(unsigned V) { 207205407Srdivacky // Mask out the first hunk. 208224145Sdim V = rotr32(~255U, getSOImmValRotate(V)) & V; 209224145Sdim 210224145Sdim // Take what's left. 211224145Sdim assert(V == (rotr32(255U, getSOImmValRotate(V)) & V)); 212224145Sdim return V; 213224145Sdim } 214224145Sdim 215224145Sdim /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed 216224145Sdim /// by a left shift. Returns the shift amount to use. 217205407Srdivacky static inline unsigned getThumbImmValShift(unsigned Imm) { 218224145Sdim // 8-bit (or less) immediates are trivially immediate operand with a shift 219205407Srdivacky // of zero. 220224145Sdim if ((Imm & ~255U) == 0) return 0; 221224145Sdim 222224145Sdim // Use CTZ to compute the shift amount. 223205407Srdivacky return CountTrailingZeros_32(Imm); 224224145Sdim } 225224145Sdim 226224145Sdim /// isThumbImmShiftedVal - Return true if the specified value can be obtained 227224145Sdim /// by left shifting a 8-bit immediate. 228224145Sdim static inline bool isThumbImmShiftedVal(unsigned V) { 229224145Sdim // If this can be handled with 230224145Sdim V = (~255U << getThumbImmValShift(V)) & V; 231224145Sdim return V == 0; 232224145Sdim } 233205407Srdivacky 234224145Sdim /// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed 235224145Sdim /// by a left shift. Returns the shift amount to use. 236224145Sdim static inline unsigned getThumbImm16ValShift(unsigned Imm) { 237205407Srdivacky // 16-bit (or less) immediates are trivially immediate operand with a shift 238224145Sdim // of zero. 239224145Sdim if ((Imm & ~65535U) == 0) return 0; 240224145Sdim 241224145Sdim // Use CTZ to compute the shift amount. 242224145Sdim return CountTrailingZeros_32(Imm); 243205407Srdivacky } 244224145Sdim 245224145Sdim /// isThumbImm16ShiftedVal - Return true if the specified value can be 246205407Srdivacky /// obtained by left shifting a 16-bit immediate. 247224145Sdim static inline bool isThumbImm16ShiftedVal(unsigned V) { 248224145Sdim // If this can be handled with 249224145Sdim V = (~65535U << getThumbImm16ValShift(V)) & V; 250224145Sdim return V == 0; 251224145Sdim } 252224145Sdim 253205407Srdivacky /// getThumbImmNonShiftedVal - If V is a value that satisfies 254224145Sdim /// isThumbImmShiftedVal, return the non-shiftd value. 255224145Sdim static inline unsigned getThumbImmNonShiftedVal(unsigned V) { 256205407Srdivacky return V >> getThumbImmValShift(V); 257224145Sdim } 258224145Sdim 259224145Sdim 260224145Sdim /// getT2SOImmValSplat - Return the 12-bit encoded representation 261224145Sdim /// if the specified value can be obtained by splatting the low 8 bits 262224145Sdim /// into every other byte or every byte of a 32-bit value. i.e., 263224145Sdim /// 00000000 00000000 00000000 abcdefgh control = 0 264224145Sdim /// 00000000 abcdefgh 00000000 abcdefgh control = 1 265224145Sdim /// abcdefgh 00000000 abcdefgh 00000000 control = 2 266205407Srdivacky /// abcdefgh abcdefgh abcdefgh abcdefgh control = 3 267224145Sdim /// Return -1 if none of the above apply. 268224145Sdim /// See ARM Reference Manual A6.3.2. 269205407Srdivacky static inline int getT2SOImmValSplatVal(unsigned V) { 270224145Sdim unsigned u, Vs, Imm; 271224145Sdim // control = 0 272224145Sdim if ((V & 0xffffff00) == 0) 273224145Sdim return V; 274224145Sdim 275224145Sdim // If the value is zeroes in the first byte, just shift those off 276224145Sdim Vs = ((V & 0xff) == 0) ? V >> 8 : V; 277224145Sdim // Any passing value only has 8 bits of payload, splatted across the word 278224145Sdim Imm = Vs & 0xff; 279224145Sdim // Likewise, any passing values have the payload splatted into the 3rd byte 280224145Sdim u = Imm | (Imm << 16); 281224145Sdim 282224145Sdim // control = 1 or 2 283224145Sdim if (Vs == u) 284224145Sdim return (((Vs == V) ? 1 : 2) << 8) | Imm; 285224145Sdim 286224145Sdim // control = 3 287224145Sdim if (Vs == (u | (u << 8))) 288224145Sdim return (3 << 8) | Imm; 289224145Sdim 290205407Srdivacky return -1; 291224145Sdim } 292224145Sdim 293205407Srdivacky /// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the 294224145Sdim /// specified value is a rotated 8-bit value. Return -1 if no rotation 295224145Sdim /// encoding is possible. 296224145Sdim /// See ARM Reference Manual A6.3.2. 297224145Sdim static inline int getT2SOImmValRotateVal(unsigned V) { 298224145Sdim unsigned RotAmt = CountLeadingZeros_32(V); 299224145Sdim if (RotAmt >= 24) 300226633Sdim return -1; 301205407Srdivacky 302224145Sdim // If 'Arg' can be handled with a single shifter_op return the value. 303206083Srdivacky if ((rotr32(0xff000000U, RotAmt) & V) == V) 304224145Sdim return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7); 305224145Sdim 306224145Sdim return -1; 307224145Sdim } 308224145Sdim 309224145Sdim /// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit 310224145Sdim /// into a Thumb-2 shifter_operand immediate operand, return the 12-bit 311206083Srdivacky /// encoding for it. If not, return -1. 312224145Sdim /// See ARM Reference Manual A6.3.2. 313205407Srdivacky static inline int getT2SOImmVal(unsigned Arg) { 314224145Sdim // If 'Arg' is an 8-bit splat, then get the encoded value. 315224145Sdim int Splat = getT2SOImmValSplatVal(Arg); 316205407Srdivacky if (Splat != -1) 317224145Sdim return Splat; 318224145Sdim 319224145Sdim // If 'Arg' can be handled with a single shifter_op return the value. 320205407Srdivacky int Rot = getT2SOImmValRotateVal(Arg); 321224145Sdim if (Rot != -1) 322224145Sdim return Rot; 323243830Sdim 324224145Sdim return -1; 325224145Sdim } 326224145Sdim 327224145Sdim static inline unsigned getT2SOImmValRotate(unsigned V) { 328205407Srdivacky if ((V & ~255U) == 0) return 0; 329224145Sdim // Use CTZ to compute the rotate amount. 330224145Sdim unsigned RotAmt = CountTrailingZeros_32(V); 331224145Sdim return (32 - RotAmt) & 31; 332224145Sdim } 333224145Sdim 334224145Sdim static inline bool isT2SOImmTwoPartVal (unsigned Imm) { 335224145Sdim unsigned V = Imm; 336224145Sdim // Passing values can be any combination of splat values and shifter 337224145Sdim // values. If this can be handled with a single shifter or splat, bail 338205407Srdivacky // out. Those should be handled directly, not with a two-part val. 339205407Srdivacky if (getT2SOImmValSplatVal(V) != -1) 340205407Srdivacky return false; 341224145Sdim V = rotr32 (~255U, getT2SOImmValRotate(V)) & V; 342205407Srdivacky if (V == 0) 343224145Sdim return false; 344224145Sdim 345224145Sdim // If this can be handled as an immediate, accept. 346205407Srdivacky if (getT2SOImmVal(V) != -1) return true; 347224145Sdim 348224145Sdim // Likewise, try masking out a splat value first. 349224145Sdim V = Imm; 350224145Sdim if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1) 351224145Sdim V &= ~0xff00ff00U; 352224145Sdim else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1) 353224145Sdim V &= ~0x00ff00ffU; 354224145Sdim // If what's left can be handled as an immediate, accept. 355205407Srdivacky if (getT2SOImmVal(V) != -1) return true; 356239462Sdim 357239462Sdim // Otherwise, do not accept. 358239462Sdim return false; 359239462Sdim } 360239462Sdim 361239462Sdim static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) { 362239462Sdim assert (isT2SOImmTwoPartVal(Imm) && 363239462Sdim "Immedate cannot be encoded as two part immediate!"); 364239462Sdim // Try a shifter operand as one part 365239462Sdim unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm; 366239462Sdim // If the rest is encodable as an immediate, then return it. 367239462Sdim if (getT2SOImmVal(V) != -1) return V; 368239462Sdim 369239462Sdim // Try masking out a splat value first. 370239462Sdim if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1) 371224145Sdim return Imm & 0xff00ff00U; 372224145Sdim 373224145Sdim // The other splat is all that's left as an option. 374224145Sdim assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1); 375224145Sdim return Imm & 0x00ff00ffU; 376224145Sdim } 377224145Sdim 378224145Sdim static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) { 379224145Sdim // Mask out the first hunk 380205407Srdivacky Imm ^= getT2SOImmTwoPartFirst(Imm); 381224145Sdim // Return what's left 382224145Sdim assert (getT2SOImmVal(Imm) != -1 && 383224145Sdim "Unable to encode second part of T2 two part SO immediate"); 384224145Sdim return Imm; 385224145Sdim } 386224145Sdim 387224145Sdim 388205407Srdivacky //===--------------------------------------------------------------------===// 389224145Sdim // Addressing Mode #2 390224145Sdim //===--------------------------------------------------------------------===// 391224145Sdim // 392224145Sdim // This is used for most simple load/store instructions. 393224145Sdim // 394224145Sdim // addrmode2 := reg +/- reg shop imm 395205407Srdivacky // addrmode2 := reg +/- imm12 396224145Sdim // 397224145Sdim // The first operand is always a Reg. The second operand is a reg if in 398205407Srdivacky // reg/reg form, otherwise it's reg#0. The third field encodes the operation 399224145Sdim // in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The 400243830Sdim // fourth operand 16-17 encodes the index mode. 401205407Srdivacky // 402224145Sdim // If this addressing mode is a frame index (before prolog/epilog insertion 403205407Srdivacky // and code rewriting), this operand will have the form: FI#, reg0, <offs> 404205407Srdivacky // with no shift amount for the frame offset. 405224145Sdim // 406224145Sdim static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, 407224145Sdim unsigned IdxMode = 0) { 408224145Sdim assert(Imm12 < (1 << 12) && "Imm too large!"); 409224145Sdim bool isSub = Opc == sub; 410224145Sdim return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ; 411218893Sdim } 412224145Sdim static inline unsigned getAM2Offset(unsigned AM2Opc) { 413224145Sdim return AM2Opc & ((1 << 12)-1); 414224145Sdim } 415218893Sdim static inline AddrOpc getAM2Op(unsigned AM2Opc) { 416224145Sdim return ((AM2Opc >> 12) & 1) ? sub : add; 417243830Sdim } 418218893Sdim static inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) { 419224145Sdim return (ShiftOpc)((AM2Opc >> 13) & 7); 420224145Sdim } 421224145Sdim static inline unsigned getAM2IdxMode(unsigned AM2Opc) { 422224145Sdim return (AM2Opc >> 16); 423224145Sdim } 424224145Sdim 425224145Sdim 426218893Sdim //===--------------------------------------------------------------------===// 427224145Sdim // Addressing Mode #3 428218893Sdim //===--------------------------------------------------------------------===// 429224145Sdim // 430224145Sdim // This is used for sign-extending loads, and load/store-pair instructions. 431224145Sdim // 432224145Sdim // addrmode3 := reg +/- reg 433224145Sdim // addrmode3 := reg +/- imm8 434224145Sdim // 435224145Sdim // The first operand is always a Reg. The second operand is a reg if in 436224145Sdim // reg/reg form, otherwise it's reg#0. The third field encodes the operation 437224145Sdim // in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the 438224145Sdim // index mode. 439224145Sdim 440224145Sdim /// getAM3Opc - This function encodes the addrmode3 opc field. 441224145Sdim static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset, 442224145Sdim unsigned IdxMode = 0) { 443224145Sdim bool isSub = Opc == sub; 444224145Sdim return ((int)isSub << 8) | Offset | (IdxMode << 9); 445224145Sdim } 446218893Sdim static inline unsigned char getAM3Offset(unsigned AM3Opc) { 447224145Sdim return AM3Opc & 0xFF; 448224145Sdim } 449224145Sdim static inline AddrOpc getAM3Op(unsigned AM3Opc) { 450218893Sdim return ((AM3Opc >> 8) & 1) ? sub : add; 451224145Sdim } 452224145Sdim static inline unsigned getAM3IdxMode(unsigned AM3Opc) { 453224145Sdim return (AM3Opc >> 9); 454224145Sdim } 455224145Sdim 456224145Sdim //===--------------------------------------------------------------------===// 457224145Sdim // Addressing Mode #4 458224145Sdim //===--------------------------------------------------------------------===// 459224145Sdim // 460224145Sdim // This is used for load / store multiple instructions. 461218893Sdim // 462224145Sdim // addrmode4 := reg, <mode> 463224145Sdim // 464224145Sdim // The four modes are: 465218893Sdim // IA - Increment after 466224145Sdim // IB - Increment before 467224145Sdim // DA - Decrement after 468218893Sdim // DB - Decrement before 469224145Sdim // For VFP instructions, only the IA and DB modes are valid. 470224145Sdim 471224145Sdim static inline AMSubMode getAM4SubMode(unsigned Mode) { 472224145Sdim return (AMSubMode)(Mode & 0x7); 473224145Sdim } 474218893Sdim 475218893Sdim static inline unsigned getAM4ModeImm(AMSubMode SubMode) { 476224145Sdim return (int)SubMode; 477224145Sdim } 478224145Sdim 479218893Sdim //===--------------------------------------------------------------------===// 480224145Sdim // Addressing Mode #5 481224145Sdim //===--------------------------------------------------------------------===// 482224145Sdim // 483224145Sdim // This is used for coprocessor instructions, such as FP load/stores. 484224145Sdim // 485224145Sdim // addrmode5 := reg +/- imm8*4 486210299Sed // 487224145Sdim // The first operand is always a Reg. The second operand encodes the 488224145Sdim // operation in bit 8 and the immediate in bits 0-7. 489224145Sdim 490210299Sed /// getAM5Opc - This function encodes the addrmode5 opc field. 491218893Sdim static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) { 492218893Sdim bool isSub = Opc == sub; 493224145Sdim return ((int)isSub << 8) | Offset; 494224145Sdim } 495224145Sdim static inline unsigned char getAM5Offset(unsigned AM5Opc) { 496224145Sdim return AM5Opc & 0xFF; 497218893Sdim } 498224145Sdim static inline AddrOpc getAM5Op(unsigned AM5Opc) { 499224145Sdim return ((AM5Opc >> 8) & 1) ? sub : add; 500224145Sdim } 501218893Sdim 502224145Sdim //===--------------------------------------------------------------------===// 503224145Sdim // Addressing Mode #6 504218893Sdim //===--------------------------------------------------------------------===// 505224145Sdim // 506224145Sdim // This is used for NEON load / store instructions. 507224145Sdim // 508224145Sdim // addrmode6 := reg with optional alignment 509224145Sdim // 510218893Sdim // This is stored in two operands [regaddr, align]. The first is the 511218893Sdim // address register. The second operand is the value of the alignment 512224145Sdim // specifier in bytes or zero if no explicit alignment. 513224145Sdim // Valid alignments depend on the specific instruction. 514224145Sdim 515218893Sdim //===--------------------------------------------------------------------===// 516224145Sdim // NEON Modified Immediates 517224145Sdim //===--------------------------------------------------------------------===// 518224145Sdim // 519221345Sdim // Several NEON instructions (e.g., VMOV) take a "modified immediate" 520224145Sdim // vector operand, where a small immediate encoded in the instruction 521224145Sdim // specifies a full NEON vector value. These modified immediates are 522224145Sdim // represented here as encoded integers. The low 8 bits hold the immediate 523218893Sdim // value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold 524210299Sed // the "Cmode" field of the instruction. The interfaces below treat the 525218893Sdim // Op and Cmode values as a single 5-bit value. 526224145Sdim 527224145Sdim static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) { 528224145Sdim return (OpCmode << 8) | Val; 529205407Srdivacky } 530224145Sdim static inline unsigned getNEONModImmOpCmode(unsigned ModImm) { 531224145Sdim return (ModImm >> 8) & 0x1f; 532224145Sdim } 533224145Sdim static inline unsigned getNEONModImmVal(unsigned ModImm) { 534224145Sdim return ModImm & 0xff; 535224145Sdim } 536224145Sdim 537224145Sdim /// decodeNEONModImm - Decode a NEON modified immediate value into the 538205407Srdivacky /// element value and the element size in bits. (If the element size is 539224145Sdim /// smaller than the vector, it is splatted into all the elements.) 540224145Sdim static inline uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits) { 541224145Sdim unsigned OpCmode = getNEONModImmOpCmode(ModImm); 542224145Sdim unsigned Imm8 = getNEONModImmVal(ModImm); 543218893Sdim uint64_t Val = 0; 544224145Sdim 545224145Sdim if (OpCmode == 0xe) { 546224145Sdim // 8-bit vector elements 547224145Sdim Val = Imm8; 548224145Sdim EltBits = 8; 549224145Sdim } else if ((OpCmode & 0xc) == 0x8) { 550224145Sdim // 16-bit vector elements 551224145Sdim unsigned ByteNum = (OpCmode & 0x6) >> 1; 552224145Sdim Val = Imm8 << (8 * ByteNum); 553208599Srdivacky EltBits = 16; 554224145Sdim } else if ((OpCmode & 0x8) == 0) { 555224145Sdim // 32-bit vector elements, zero with one byte set 556224145Sdim unsigned ByteNum = (OpCmode & 0x6) >> 1; 557224145Sdim Val = Imm8 << (8 * ByteNum); 558205407Srdivacky EltBits = 32; 559224145Sdim } else if ((OpCmode & 0xe) == 0xc) { 560205407Srdivacky // 32-bit vector elements, one byte with low bits set 561243830Sdim unsigned ByteNum = 1 + (OpCmode & 0x1); 562243830Sdim Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum))); 563243830Sdim EltBits = 32; 564243830Sdim } else if (OpCmode == 0x1e) { 565243830Sdim // 64-bit vector elements 566243830Sdim for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) { 567243830Sdim if ((ModImm >> ByteNum) & 1) 568243830Sdim Val |= (uint64_t)0xff << (8 * ByteNum); 569243830Sdim } 570243830Sdim EltBits = 64; 571243830Sdim } else { 572243830Sdim assert(false && "Unsupported NEON immediate"); 573243830Sdim } 574243830Sdim return Val; 575243830Sdim } 576243830Sdim 577243830Sdim AMSubMode getLoadStoreMultipleSubMode(int Opcode); 578243830Sdim 579243830Sdim //===--------------------------------------------------------------------===// 580243830Sdim // Floating-point Immediates 581224145Sdim // 582224145Sdim static inline float getFPImmFloat(unsigned Imm) { 583224145Sdim // We expect an 8-bit binary encoding of a floating-point number here. 584205407Srdivacky union { 585224145Sdim uint32_t I; 586224145Sdim float F; 587205407Srdivacky } FPUnion; 588243830Sdim 589243830Sdim uint8_t Sign = (Imm >> 7) & 0x1; 590243830Sdim uint8_t Exp = (Imm >> 4) & 0x7; 591243830Sdim uint8_t Mantissa = Imm & 0xf; 592224145Sdim 593224145Sdim // 8-bit FP iEEEE Float Encoding 594224145Sdim // abcd efgh aBbbbbbc defgh000 00000000 00000000 595224145Sdim // 596205407Srdivacky // where B = NOT(b); 597224145Sdim 598224145Sdim FPUnion.I = 0; 599224145Sdim FPUnion.I |= Sign << 31; 600224145Sdim FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; 601224145Sdim FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; 602224145Sdim FPUnion.I |= (Exp & 0x3) << 23; 603224145Sdim FPUnion.I |= Mantissa << 19; 604224145Sdim return FPUnion.F; 605218893Sdim } 606224145Sdim 607224145Sdim /// getFP32Imm - Return an 8-bit floating-point version of the 32-bit 608224145Sdim /// floating-point value. If the value cannot be represented as an 8-bit 609224145Sdim /// floating-point value, then return -1. 610224145Sdim static inline int getFP32Imm(const APInt &Imm) { 611224145Sdim uint32_t Sign = Imm.lshr(31).getZExtValue() & 1; 612205407Srdivacky int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127 613224145Sdim int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits 614224145Sdim 615224145Sdim // We can handle 4 bits of mantissa. 616205407Srdivacky // mantissa = (16+UInt(e:f:g:h))/16. 617224145Sdim if (Mantissa & 0x7ffff) 618224145Sdim return -1; 619224145Sdim Mantissa >>= 19; 620224145Sdim if ((Mantissa & 0xf) != Mantissa) 621224145Sdim return -1; 622224145Sdim 623224145Sdim // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3 624224145Sdim if (Exp < -3 || Exp > 4) 625224145Sdim return -1; 626234353Sdim Exp = ((Exp+3) & 0x7) ^ 4; 627234353Sdim 628234353Sdim return ((int)Sign << 7) | (Exp << 4) | Mantissa; 629234353Sdim } 630205407Srdivacky 631224145Sdim static inline int getFP32Imm(const APFloat &FPImm) { 632234353Sdim return getFP32Imm(FPImm.bitcastToAPInt()); 633234353Sdim } 634234353Sdim 635234353Sdim /// getFP64Imm - Return an 8-bit floating-point version of the 64-bit 636224145Sdim /// floating-point value. If the value cannot be represented as an 8-bit 637224145Sdim /// floating-point value, then return -1. 638205407Srdivacky static inline int getFP64Imm(const APInt &Imm) { 639226633Sdim uint64_t Sign = Imm.lshr(63).getZExtValue() & 1; 640226633Sdim int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023 641226633Sdim uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffULL; 642226633Sdim 643226633Sdim // We can handle 4 bits of mantissa. 644226633Sdim // mantissa = (16+UInt(e:f:g:h))/16. 645226633Sdim if (Mantissa & 0xffffffffffffULL) 646226633Sdim return -1; 647226633Sdim Mantissa >>= 48; 648226633Sdim if ((Mantissa & 0xf) != Mantissa) 649224145Sdim return -1; 650224145Sdim 651224145Sdim // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3 652205407Srdivacky if (Exp < -3 || Exp > 4) 653205407Srdivacky return -1; 654226633Sdim Exp = ((Exp+3) & 0x7) ^ 4; 655205407Srdivacky 656226633Sdim return ((int)Sign << 7) | (Exp << 4) | Mantissa; 657226633Sdim } 658226633Sdim 659226633Sdim static inline int getFP64Imm(const APFloat &FPImm) { 660226633Sdim return getFP64Imm(FPImm.bitcastToAPInt()); 661224145Sdim } 662224145Sdim 663205407Srdivacky} // end namespace ARM_AM 664224145Sdim} // end namespace llvm 665224145Sdim 666224145Sdim#endif 667205407Srdivacky 668224145Sdim