ARMAsmParser.cpp revision 280031 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "ARMFPUName.h"
11#include "ARMFeatures.h"
12#include "MCTargetDesc/ARMAddressingModes.h"
13#include "MCTargetDesc/ARMArchName.h"
14#include "MCTargetDesc/ARMBaseInfo.h"
15#include "MCTargetDesc/ARMMCExpr.h"
16#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/ADT/StringExtras.h"
19#include "llvm/ADT/StringSwitch.h"
20#include "llvm/ADT/Twine.h"
21#include "llvm/MC/MCAsmInfo.h"
22#include "llvm/MC/MCAssembler.h"
23#include "llvm/MC/MCContext.h"
24#include "llvm/MC/MCDisassembler.h"
25#include "llvm/MC/MCELFStreamer.h"
26#include "llvm/MC/MCExpr.h"
27#include "llvm/MC/MCInst.h"
28#include "llvm/MC/MCInstrDesc.h"
29#include "llvm/MC/MCInstrInfo.h"
30#include "llvm/MC/MCObjectFileInfo.h"
31#include "llvm/MC/MCParser/MCAsmLexer.h"
32#include "llvm/MC/MCParser/MCAsmParser.h"
33#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
34#include "llvm/MC/MCRegisterInfo.h"
35#include "llvm/MC/MCSection.h"
36#include "llvm/MC/MCStreamer.h"
37#include "llvm/MC/MCSubtargetInfo.h"
38#include "llvm/MC/MCSymbol.h"
39#include "llvm/MC/MCTargetAsmParser.h"
40#include "llvm/Support/ARMBuildAttributes.h"
41#include "llvm/Support/ARMEHABI.h"
42#include "llvm/Support/COFF.h"
43#include "llvm/Support/Debug.h"
44#include "llvm/Support/ELF.h"
45#include "llvm/Support/MathExtras.h"
46#include "llvm/Support/SourceMgr.h"
47#include "llvm/Support/TargetRegistry.h"
48#include "llvm/Support/raw_ostream.h"
49
50using namespace llvm;
51
52namespace {
53
54class ARMOperand;
55
56enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
57
58class UnwindContext {
59  MCAsmParser &Parser;
60
61  typedef SmallVector<SMLoc, 4> Locs;
62
63  Locs FnStartLocs;
64  Locs CantUnwindLocs;
65  Locs PersonalityLocs;
66  Locs PersonalityIndexLocs;
67  Locs HandlerDataLocs;
68  int FPReg;
69
70public:
71  UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
72
73  bool hasFnStart() const { return !FnStartLocs.empty(); }
74  bool cantUnwind() const { return !CantUnwindLocs.empty(); }
75  bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
76  bool hasPersonality() const {
77    return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
78  }
79
80  void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
81  void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
82  void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
83  void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
84  void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
85
86  void saveFPReg(int Reg) { FPReg = Reg; }
87  int getFPReg() const { return FPReg; }
88
89  void emitFnStartLocNotes() const {
90    for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
91         FI != FE; ++FI)
92      Parser.Note(*FI, ".fnstart was specified here");
93  }
94  void emitCantUnwindLocNotes() const {
95    for (Locs::const_iterator UI = CantUnwindLocs.begin(),
96                              UE = CantUnwindLocs.end(); UI != UE; ++UI)
97      Parser.Note(*UI, ".cantunwind was specified here");
98  }
99  void emitHandlerDataLocNotes() const {
100    for (Locs::const_iterator HI = HandlerDataLocs.begin(),
101                              HE = HandlerDataLocs.end(); HI != HE; ++HI)
102      Parser.Note(*HI, ".handlerdata was specified here");
103  }
104  void emitPersonalityLocNotes() const {
105    for (Locs::const_iterator PI = PersonalityLocs.begin(),
106                              PE = PersonalityLocs.end(),
107                              PII = PersonalityIndexLocs.begin(),
108                              PIE = PersonalityIndexLocs.end();
109         PI != PE || PII != PIE;) {
110      if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
111        Parser.Note(*PI++, ".personality was specified here");
112      else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
113        Parser.Note(*PII++, ".personalityindex was specified here");
114      else
115        llvm_unreachable(".personality and .personalityindex cannot be "
116                         "at the same location");
117    }
118  }
119
120  void reset() {
121    FnStartLocs = Locs();
122    CantUnwindLocs = Locs();
123    PersonalityLocs = Locs();
124    HandlerDataLocs = Locs();
125    PersonalityIndexLocs = Locs();
126    FPReg = ARM::SP;
127  }
128};
129
130class ARMAsmParser : public MCTargetAsmParser {
131  MCSubtargetInfo &STI;
132  const MCInstrInfo &MII;
133  const MCRegisterInfo *MRI;
134  UnwindContext UC;
135
136  ARMTargetStreamer &getTargetStreamer() {
137    assert(getParser().getStreamer().getTargetStreamer() &&
138           "do not have a target streamer");
139    MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
140    return static_cast<ARMTargetStreamer &>(TS);
141  }
142
143  // Map of register aliases registers via the .req directive.
144  StringMap<unsigned> RegisterReqs;
145
146  bool NextSymbolIsThumb;
147
148  struct {
149    ARMCC::CondCodes Cond;    // Condition for IT block.
150    unsigned Mask:4;          // Condition mask for instructions.
151                              // Starting at first 1 (from lsb).
152                              //   '1'  condition as indicated in IT.
153                              //   '0'  inverse of condition (else).
154                              // Count of instructions in IT block is
155                              // 4 - trailingzeroes(mask)
156
157    bool FirstCond;           // Explicit flag for when we're parsing the
158                              // First instruction in the IT block. It's
159                              // implied in the mask, so needs special
160                              // handling.
161
162    unsigned CurPosition;     // Current position in parsing of IT
163                              // block. In range [0,3]. Initialized
164                              // according to count of instructions in block.
165                              // ~0U if no active IT block.
166  } ITState;
167  bool inITBlock() { return ITState.CurPosition != ~0U; }
168  bool lastInITBlock() {
169    return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
170  }
171  void forwardITPosition() {
172    if (!inITBlock()) return;
173    // Move to the next instruction in the IT block, if there is one. If not,
174    // mark the block as done.
175    unsigned TZ = countTrailingZeros(ITState.Mask);
176    if (++ITState.CurPosition == 5 - TZ)
177      ITState.CurPosition = ~0U; // Done with the IT block after this.
178  }
179
180  void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
181    return getParser().Note(L, Msg, Ranges);
182  }
183  bool Warning(SMLoc L, const Twine &Msg,
184               ArrayRef<SMRange> Ranges = None) {
185    return getParser().Warning(L, Msg, Ranges);
186  }
187  bool Error(SMLoc L, const Twine &Msg,
188             ArrayRef<SMRange> Ranges = None) {
189    return getParser().Error(L, Msg, Ranges);
190  }
191
192  bool validatetLDMRegList(MCInst Inst, const OperandVector &Operands,
193                           unsigned ListNo, bool IsARPop = false);
194  bool validatetSTMRegList(MCInst Inst, const OperandVector &Operands,
195                           unsigned ListNo);
196
197  int tryParseRegister();
198  bool tryParseRegisterWithWriteBack(OperandVector &);
199  int tryParseShiftRegister(OperandVector &);
200  bool parseRegisterList(OperandVector &);
201  bool parseMemory(OperandVector &);
202  bool parseOperand(OperandVector &, StringRef Mnemonic);
203  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
204  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
205                              unsigned &ShiftAmount);
206  bool parseLiteralValues(unsigned Size, SMLoc L);
207  bool parseDirectiveThumb(SMLoc L);
208  bool parseDirectiveARM(SMLoc L);
209  bool parseDirectiveThumbFunc(SMLoc L);
210  bool parseDirectiveCode(SMLoc L);
211  bool parseDirectiveSyntax(SMLoc L);
212  bool parseDirectiveReq(StringRef Name, SMLoc L);
213  bool parseDirectiveUnreq(SMLoc L);
214  bool parseDirectiveArch(SMLoc L);
215  bool parseDirectiveEabiAttr(SMLoc L);
216  bool parseDirectiveCPU(SMLoc L);
217  bool parseDirectiveFPU(SMLoc L);
218  bool parseDirectiveFnStart(SMLoc L);
219  bool parseDirectiveFnEnd(SMLoc L);
220  bool parseDirectiveCantUnwind(SMLoc L);
221  bool parseDirectivePersonality(SMLoc L);
222  bool parseDirectiveHandlerData(SMLoc L);
223  bool parseDirectiveSetFP(SMLoc L);
224  bool parseDirectivePad(SMLoc L);
225  bool parseDirectiveRegSave(SMLoc L, bool IsVector);
226  bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
227  bool parseDirectiveLtorg(SMLoc L);
228  bool parseDirectiveEven(SMLoc L);
229  bool parseDirectivePersonalityIndex(SMLoc L);
230  bool parseDirectiveUnwindRaw(SMLoc L);
231  bool parseDirectiveTLSDescSeq(SMLoc L);
232  bool parseDirectiveMovSP(SMLoc L);
233  bool parseDirectiveObjectArch(SMLoc L);
234  bool parseDirectiveArchExtension(SMLoc L);
235  bool parseDirectiveAlign(SMLoc L);
236  bool parseDirectiveThumbSet(SMLoc L);
237
238  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
239                          bool &CarrySetting, unsigned &ProcessorIMod,
240                          StringRef &ITMask);
241  void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
242                             bool &CanAcceptCarrySet,
243                             bool &CanAcceptPredicationCode);
244
245  bool isThumb() const {
246    // FIXME: Can tablegen auto-generate this?
247    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
248  }
249  bool isThumbOne() const {
250    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
251  }
252  bool isThumbTwo() const {
253    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
254  }
255  bool hasThumb() const {
256    return STI.getFeatureBits() & ARM::HasV4TOps;
257  }
258  bool hasV6Ops() const {
259    return STI.getFeatureBits() & ARM::HasV6Ops;
260  }
261  bool hasV6MOps() const {
262    return STI.getFeatureBits() & ARM::HasV6MOps;
263  }
264  bool hasV7Ops() const {
265    return STI.getFeatureBits() & ARM::HasV7Ops;
266  }
267  bool hasV8Ops() const {
268    return STI.getFeatureBits() & ARM::HasV8Ops;
269  }
270  bool hasARM() const {
271    return !(STI.getFeatureBits() & ARM::FeatureNoARM);
272  }
273  bool hasThumb2DSP() const {
274    return STI.getFeatureBits() & ARM::FeatureDSPThumb2;
275  }
276  bool hasD16() const {
277    return STI.getFeatureBits() & ARM::FeatureD16;
278  }
279
280  void SwitchMode() {
281    uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
282    setAvailableFeatures(FB);
283  }
284  bool isMClass() const {
285    return STI.getFeatureBits() & ARM::FeatureMClass;
286  }
287
288  /// @name Auto-generated Match Functions
289  /// {
290
291#define GET_ASSEMBLER_HEADER
292#include "ARMGenAsmMatcher.inc"
293
294  /// }
295
296  OperandMatchResultTy parseITCondCode(OperandVector &);
297  OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
298  OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
299  OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
300  OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
301  OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
302  OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
303  OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
304  OperandMatchResultTy parseBankedRegOperand(OperandVector &);
305  OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
306                                   int High);
307  OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
308    return parsePKHImm(O, "lsl", 0, 31);
309  }
310  OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
311    return parsePKHImm(O, "asr", 1, 32);
312  }
313  OperandMatchResultTy parseSetEndImm(OperandVector &);
314  OperandMatchResultTy parseShifterImm(OperandVector &);
315  OperandMatchResultTy parseRotImm(OperandVector &);
316  OperandMatchResultTy parseModImm(OperandVector &);
317  OperandMatchResultTy parseBitfield(OperandVector &);
318  OperandMatchResultTy parsePostIdxReg(OperandVector &);
319  OperandMatchResultTy parseAM3Offset(OperandVector &);
320  OperandMatchResultTy parseFPImm(OperandVector &);
321  OperandMatchResultTy parseVectorList(OperandVector &);
322  OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
323                                       SMLoc &EndLoc);
324
325  // Asm Match Converter Methods
326  void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
327  void cvtThumbBranches(MCInst &Inst, const OperandVector &);
328
329  bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
330  bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
331  bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
332  bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
333
334public:
335  enum ARMMatchResultTy {
336    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
337    Match_RequiresNotITBlock,
338    Match_RequiresV6,
339    Match_RequiresThumb2,
340#define GET_OPERAND_DIAGNOSTIC_TYPES
341#include "ARMGenAsmMatcher.inc"
342
343  };
344
345  ARMAsmParser(MCSubtargetInfo & _STI, MCAsmParser & _Parser,
346               const MCInstrInfo &MII, const MCTargetOptions &Options)
347      : MCTargetAsmParser(), STI(_STI), MII(MII), UC(_Parser) {
348    MCAsmParserExtension::Initialize(_Parser);
349
350    // Cache the MCRegisterInfo.
351    MRI = getContext().getRegisterInfo();
352
353    // Initialize the set of available features.
354    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
355
356    // Not in an ITBlock to start with.
357    ITState.CurPosition = ~0U;
358
359    NextSymbolIsThumb = false;
360  }
361
362  // Implementation of the MCTargetAsmParser interface:
363  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
364  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
365                        SMLoc NameLoc, OperandVector &Operands) override;
366  bool ParseDirective(AsmToken DirectiveID) override;
367
368  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
369                                      unsigned Kind) override;
370  unsigned checkTargetMatchPredicate(MCInst &Inst) override;
371
372  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
373                               OperandVector &Operands, MCStreamer &Out,
374                               uint64_t &ErrorInfo,
375                               bool MatchingInlineAsm) override;
376  void onLabelParsed(MCSymbol *Symbol) override;
377};
378} // end anonymous namespace
379
380namespace {
381
382/// ARMOperand - Instances of this class represent a parsed ARM machine
383/// operand.
384class ARMOperand : public MCParsedAsmOperand {
385  enum KindTy {
386    k_CondCode,
387    k_CCOut,
388    k_ITCondMask,
389    k_CoprocNum,
390    k_CoprocReg,
391    k_CoprocOption,
392    k_Immediate,
393    k_MemBarrierOpt,
394    k_InstSyncBarrierOpt,
395    k_Memory,
396    k_PostIndexRegister,
397    k_MSRMask,
398    k_BankedReg,
399    k_ProcIFlags,
400    k_VectorIndex,
401    k_Register,
402    k_RegisterList,
403    k_DPRRegisterList,
404    k_SPRRegisterList,
405    k_VectorList,
406    k_VectorListAllLanes,
407    k_VectorListIndexed,
408    k_ShiftedRegister,
409    k_ShiftedImmediate,
410    k_ShifterImmediate,
411    k_RotateImmediate,
412    k_ModifiedImmediate,
413    k_BitfieldDescriptor,
414    k_Token
415  } Kind;
416
417  SMLoc StartLoc, EndLoc, AlignmentLoc;
418  SmallVector<unsigned, 8> Registers;
419
420  struct CCOp {
421    ARMCC::CondCodes Val;
422  };
423
424  struct CopOp {
425    unsigned Val;
426  };
427
428  struct CoprocOptionOp {
429    unsigned Val;
430  };
431
432  struct ITMaskOp {
433    unsigned Mask:4;
434  };
435
436  struct MBOptOp {
437    ARM_MB::MemBOpt Val;
438  };
439
440  struct ISBOptOp {
441    ARM_ISB::InstSyncBOpt Val;
442  };
443
444  struct IFlagsOp {
445    ARM_PROC::IFlags Val;
446  };
447
448  struct MMaskOp {
449    unsigned Val;
450  };
451
452  struct BankedRegOp {
453    unsigned Val;
454  };
455
456  struct TokOp {
457    const char *Data;
458    unsigned Length;
459  };
460
461  struct RegOp {
462    unsigned RegNum;
463  };
464
465  // A vector register list is a sequential list of 1 to 4 registers.
466  struct VectorListOp {
467    unsigned RegNum;
468    unsigned Count;
469    unsigned LaneIndex;
470    bool isDoubleSpaced;
471  };
472
473  struct VectorIndexOp {
474    unsigned Val;
475  };
476
477  struct ImmOp {
478    const MCExpr *Val;
479  };
480
481  /// Combined record for all forms of ARM address expressions.
482  struct MemoryOp {
483    unsigned BaseRegNum;
484    // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
485    // was specified.
486    const MCConstantExpr *OffsetImm;  // Offset immediate value
487    unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
488    ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
489    unsigned ShiftImm;        // shift for OffsetReg.
490    unsigned Alignment;       // 0 = no alignment specified
491    // n = alignment in bytes (2, 4, 8, 16, or 32)
492    unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
493  };
494
495  struct PostIdxRegOp {
496    unsigned RegNum;
497    bool isAdd;
498    ARM_AM::ShiftOpc ShiftTy;
499    unsigned ShiftImm;
500  };
501
502  struct ShifterImmOp {
503    bool isASR;
504    unsigned Imm;
505  };
506
507  struct RegShiftedRegOp {
508    ARM_AM::ShiftOpc ShiftTy;
509    unsigned SrcReg;
510    unsigned ShiftReg;
511    unsigned ShiftImm;
512  };
513
514  struct RegShiftedImmOp {
515    ARM_AM::ShiftOpc ShiftTy;
516    unsigned SrcReg;
517    unsigned ShiftImm;
518  };
519
520  struct RotImmOp {
521    unsigned Imm;
522  };
523
524  struct ModImmOp {
525    unsigned Bits;
526    unsigned Rot;
527  };
528
529  struct BitfieldOp {
530    unsigned LSB;
531    unsigned Width;
532  };
533
534  union {
535    struct CCOp CC;
536    struct CopOp Cop;
537    struct CoprocOptionOp CoprocOption;
538    struct MBOptOp MBOpt;
539    struct ISBOptOp ISBOpt;
540    struct ITMaskOp ITMask;
541    struct IFlagsOp IFlags;
542    struct MMaskOp MMask;
543    struct BankedRegOp BankedReg;
544    struct TokOp Tok;
545    struct RegOp Reg;
546    struct VectorListOp VectorList;
547    struct VectorIndexOp VectorIndex;
548    struct ImmOp Imm;
549    struct MemoryOp Memory;
550    struct PostIdxRegOp PostIdxReg;
551    struct ShifterImmOp ShifterImm;
552    struct RegShiftedRegOp RegShiftedReg;
553    struct RegShiftedImmOp RegShiftedImm;
554    struct RotImmOp RotImm;
555    struct ModImmOp ModImm;
556    struct BitfieldOp Bitfield;
557  };
558
559public:
560  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
561  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
562    Kind = o.Kind;
563    StartLoc = o.StartLoc;
564    EndLoc = o.EndLoc;
565    switch (Kind) {
566    case k_CondCode:
567      CC = o.CC;
568      break;
569    case k_ITCondMask:
570      ITMask = o.ITMask;
571      break;
572    case k_Token:
573      Tok = o.Tok;
574      break;
575    case k_CCOut:
576    case k_Register:
577      Reg = o.Reg;
578      break;
579    case k_RegisterList:
580    case k_DPRRegisterList:
581    case k_SPRRegisterList:
582      Registers = o.Registers;
583      break;
584    case k_VectorList:
585    case k_VectorListAllLanes:
586    case k_VectorListIndexed:
587      VectorList = o.VectorList;
588      break;
589    case k_CoprocNum:
590    case k_CoprocReg:
591      Cop = o.Cop;
592      break;
593    case k_CoprocOption:
594      CoprocOption = o.CoprocOption;
595      break;
596    case k_Immediate:
597      Imm = o.Imm;
598      break;
599    case k_MemBarrierOpt:
600      MBOpt = o.MBOpt;
601      break;
602    case k_InstSyncBarrierOpt:
603      ISBOpt = o.ISBOpt;
604    case k_Memory:
605      Memory = o.Memory;
606      break;
607    case k_PostIndexRegister:
608      PostIdxReg = o.PostIdxReg;
609      break;
610    case k_MSRMask:
611      MMask = o.MMask;
612      break;
613    case k_BankedReg:
614      BankedReg = o.BankedReg;
615      break;
616    case k_ProcIFlags:
617      IFlags = o.IFlags;
618      break;
619    case k_ShifterImmediate:
620      ShifterImm = o.ShifterImm;
621      break;
622    case k_ShiftedRegister:
623      RegShiftedReg = o.RegShiftedReg;
624      break;
625    case k_ShiftedImmediate:
626      RegShiftedImm = o.RegShiftedImm;
627      break;
628    case k_RotateImmediate:
629      RotImm = o.RotImm;
630      break;
631    case k_ModifiedImmediate:
632      ModImm = o.ModImm;
633      break;
634    case k_BitfieldDescriptor:
635      Bitfield = o.Bitfield;
636      break;
637    case k_VectorIndex:
638      VectorIndex = o.VectorIndex;
639      break;
640    }
641  }
642
643  /// getStartLoc - Get the location of the first token of this operand.
644  SMLoc getStartLoc() const override { return StartLoc; }
645  /// getEndLoc - Get the location of the last token of this operand.
646  SMLoc getEndLoc() const override { return EndLoc; }
647  /// getLocRange - Get the range between the first and last token of this
648  /// operand.
649  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
650
651  /// getAlignmentLoc - Get the location of the Alignment token of this operand.
652  SMLoc getAlignmentLoc() const {
653    assert(Kind == k_Memory && "Invalid access!");
654    return AlignmentLoc;
655  }
656
657  ARMCC::CondCodes getCondCode() const {
658    assert(Kind == k_CondCode && "Invalid access!");
659    return CC.Val;
660  }
661
662  unsigned getCoproc() const {
663    assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
664    return Cop.Val;
665  }
666
667  StringRef getToken() const {
668    assert(Kind == k_Token && "Invalid access!");
669    return StringRef(Tok.Data, Tok.Length);
670  }
671
672  unsigned getReg() const override {
673    assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
674    return Reg.RegNum;
675  }
676
677  const SmallVectorImpl<unsigned> &getRegList() const {
678    assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
679            Kind == k_SPRRegisterList) && "Invalid access!");
680    return Registers;
681  }
682
683  const MCExpr *getImm() const {
684    assert(isImm() && "Invalid access!");
685    return Imm.Val;
686  }
687
688  unsigned getVectorIndex() const {
689    assert(Kind == k_VectorIndex && "Invalid access!");
690    return VectorIndex.Val;
691  }
692
693  ARM_MB::MemBOpt getMemBarrierOpt() const {
694    assert(Kind == k_MemBarrierOpt && "Invalid access!");
695    return MBOpt.Val;
696  }
697
698  ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
699    assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
700    return ISBOpt.Val;
701  }
702
703  ARM_PROC::IFlags getProcIFlags() const {
704    assert(Kind == k_ProcIFlags && "Invalid access!");
705    return IFlags.Val;
706  }
707
708  unsigned getMSRMask() const {
709    assert(Kind == k_MSRMask && "Invalid access!");
710    return MMask.Val;
711  }
712
713  unsigned getBankedReg() const {
714    assert(Kind == k_BankedReg && "Invalid access!");
715    return BankedReg.Val;
716  }
717
718  bool isCoprocNum() const { return Kind == k_CoprocNum; }
719  bool isCoprocReg() const { return Kind == k_CoprocReg; }
720  bool isCoprocOption() const { return Kind == k_CoprocOption; }
721  bool isCondCode() const { return Kind == k_CondCode; }
722  bool isCCOut() const { return Kind == k_CCOut; }
723  bool isITMask() const { return Kind == k_ITCondMask; }
724  bool isITCondCode() const { return Kind == k_CondCode; }
725  bool isImm() const override { return Kind == k_Immediate; }
726  // checks whether this operand is an unsigned offset which fits is a field
727  // of specified width and scaled by a specific number of bits
728  template<unsigned width, unsigned scale>
729  bool isUnsignedOffset() const {
730    if (!isImm()) return false;
731    if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
732    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
733      int64_t Val = CE->getValue();
734      int64_t Align = 1LL << scale;
735      int64_t Max = Align * ((1LL << width) - 1);
736      return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
737    }
738    return false;
739  }
740  // checks whether this operand is an signed offset which fits is a field
741  // of specified width and scaled by a specific number of bits
742  template<unsigned width, unsigned scale>
743  bool isSignedOffset() const {
744    if (!isImm()) return false;
745    if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
746    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
747      int64_t Val = CE->getValue();
748      int64_t Align = 1LL << scale;
749      int64_t Max = Align * ((1LL << (width-1)) - 1);
750      int64_t Min = -Align * (1LL << (width-1));
751      return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
752    }
753    return false;
754  }
755
756  // checks whether this operand is a memory operand computed as an offset
757  // applied to PC. the offset may have 8 bits of magnitude and is represented
758  // with two bits of shift. textually it may be either [pc, #imm], #imm or
759  // relocable expression...
760  bool isThumbMemPC() const {
761    int64_t Val = 0;
762    if (isImm()) {
763      if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
764      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
765      if (!CE) return false;
766      Val = CE->getValue();
767    }
768    else if (isMem()) {
769      if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
770      if(Memory.BaseRegNum != ARM::PC) return false;
771      Val = Memory.OffsetImm->getValue();
772    }
773    else return false;
774    return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
775  }
776  bool isFPImm() const {
777    if (!isImm()) return false;
778    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
779    if (!CE) return false;
780    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
781    return Val != -1;
782  }
783  bool isFBits16() const {
784    if (!isImm()) return false;
785    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
786    if (!CE) return false;
787    int64_t Value = CE->getValue();
788    return Value >= 0 && Value <= 16;
789  }
790  bool isFBits32() const {
791    if (!isImm()) return false;
792    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
793    if (!CE) return false;
794    int64_t Value = CE->getValue();
795    return Value >= 1 && Value <= 32;
796  }
797  bool isImm8s4() const {
798    if (!isImm()) return false;
799    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
800    if (!CE) return false;
801    int64_t Value = CE->getValue();
802    return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
803  }
804  bool isImm0_1020s4() const {
805    if (!isImm()) return false;
806    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
807    if (!CE) return false;
808    int64_t Value = CE->getValue();
809    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
810  }
811  bool isImm0_508s4() const {
812    if (!isImm()) return false;
813    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
814    if (!CE) return false;
815    int64_t Value = CE->getValue();
816    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
817  }
818  bool isImm0_508s4Neg() const {
819    if (!isImm()) return false;
820    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
821    if (!CE) return false;
822    int64_t Value = -CE->getValue();
823    // explicitly exclude zero. we want that to use the normal 0_508 version.
824    return ((Value & 3) == 0) && Value > 0 && Value <= 508;
825  }
826  bool isImm0_239() const {
827    if (!isImm()) return false;
828    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
829    if (!CE) return false;
830    int64_t Value = CE->getValue();
831    return Value >= 0 && Value < 240;
832  }
833  bool isImm0_255() const {
834    if (!isImm()) return false;
835    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
836    if (!CE) return false;
837    int64_t Value = CE->getValue();
838    return Value >= 0 && Value < 256;
839  }
840  bool isImm0_4095() const {
841    if (!isImm()) return false;
842    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
843    if (!CE) return false;
844    int64_t Value = CE->getValue();
845    return Value >= 0 && Value < 4096;
846  }
847  bool isImm0_4095Neg() const {
848    if (!isImm()) return false;
849    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
850    if (!CE) return false;
851    int64_t Value = -CE->getValue();
852    return Value > 0 && Value < 4096;
853  }
854  bool isImm0_1() const {
855    if (!isImm()) return false;
856    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
857    if (!CE) return false;
858    int64_t Value = CE->getValue();
859    return Value >= 0 && Value < 2;
860  }
861  bool isImm0_3() const {
862    if (!isImm()) return false;
863    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
864    if (!CE) return false;
865    int64_t Value = CE->getValue();
866    return Value >= 0 && Value < 4;
867  }
868  bool isImm0_7() const {
869    if (!isImm()) return false;
870    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
871    if (!CE) return false;
872    int64_t Value = CE->getValue();
873    return Value >= 0 && Value < 8;
874  }
875  bool isImm0_15() const {
876    if (!isImm()) return false;
877    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
878    if (!CE) return false;
879    int64_t Value = CE->getValue();
880    return Value >= 0 && Value < 16;
881  }
882  bool isImm0_31() const {
883    if (!isImm()) return false;
884    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
885    if (!CE) return false;
886    int64_t Value = CE->getValue();
887    return Value >= 0 && Value < 32;
888  }
889  bool isImm0_63() const {
890    if (!isImm()) return false;
891    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
892    if (!CE) return false;
893    int64_t Value = CE->getValue();
894    return Value >= 0 && Value < 64;
895  }
896  bool isImm8() const {
897    if (!isImm()) return false;
898    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
899    if (!CE) return false;
900    int64_t Value = CE->getValue();
901    return Value == 8;
902  }
903  bool isImm16() const {
904    if (!isImm()) return false;
905    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
906    if (!CE) return false;
907    int64_t Value = CE->getValue();
908    return Value == 16;
909  }
910  bool isImm32() const {
911    if (!isImm()) return false;
912    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
913    if (!CE) return false;
914    int64_t Value = CE->getValue();
915    return Value == 32;
916  }
917  bool isShrImm8() const {
918    if (!isImm()) return false;
919    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
920    if (!CE) return false;
921    int64_t Value = CE->getValue();
922    return Value > 0 && Value <= 8;
923  }
924  bool isShrImm16() const {
925    if (!isImm()) return false;
926    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
927    if (!CE) return false;
928    int64_t Value = CE->getValue();
929    return Value > 0 && Value <= 16;
930  }
931  bool isShrImm32() const {
932    if (!isImm()) return false;
933    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
934    if (!CE) return false;
935    int64_t Value = CE->getValue();
936    return Value > 0 && Value <= 32;
937  }
938  bool isShrImm64() const {
939    if (!isImm()) return false;
940    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
941    if (!CE) return false;
942    int64_t Value = CE->getValue();
943    return Value > 0 && Value <= 64;
944  }
945  bool isImm1_7() const {
946    if (!isImm()) return false;
947    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
948    if (!CE) return false;
949    int64_t Value = CE->getValue();
950    return Value > 0 && Value < 8;
951  }
952  bool isImm1_15() const {
953    if (!isImm()) return false;
954    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
955    if (!CE) return false;
956    int64_t Value = CE->getValue();
957    return Value > 0 && Value < 16;
958  }
959  bool isImm1_31() const {
960    if (!isImm()) return false;
961    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
962    if (!CE) return false;
963    int64_t Value = CE->getValue();
964    return Value > 0 && Value < 32;
965  }
966  bool isImm1_16() const {
967    if (!isImm()) return false;
968    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
969    if (!CE) return false;
970    int64_t Value = CE->getValue();
971    return Value > 0 && Value < 17;
972  }
973  bool isImm1_32() const {
974    if (!isImm()) return false;
975    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
976    if (!CE) return false;
977    int64_t Value = CE->getValue();
978    return Value > 0 && Value < 33;
979  }
980  bool isImm0_32() const {
981    if (!isImm()) return false;
982    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
983    if (!CE) return false;
984    int64_t Value = CE->getValue();
985    return Value >= 0 && Value < 33;
986  }
987  bool isImm0_65535() const {
988    if (!isImm()) return false;
989    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
990    if (!CE) return false;
991    int64_t Value = CE->getValue();
992    return Value >= 0 && Value < 65536;
993  }
994  bool isImm256_65535Expr() const {
995    if (!isImm()) return false;
996    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
997    // If it's not a constant expression, it'll generate a fixup and be
998    // handled later.
999    if (!CE) return true;
1000    int64_t Value = CE->getValue();
1001    return Value >= 256 && Value < 65536;
1002  }
1003  bool isImm0_65535Expr() const {
1004    if (!isImm()) return false;
1005    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1006    // If it's not a constant expression, it'll generate a fixup and be
1007    // handled later.
1008    if (!CE) return true;
1009    int64_t Value = CE->getValue();
1010    return Value >= 0 && Value < 65536;
1011  }
1012  bool isImm24bit() const {
1013    if (!isImm()) return false;
1014    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1015    if (!CE) return false;
1016    int64_t Value = CE->getValue();
1017    return Value >= 0 && Value <= 0xffffff;
1018  }
1019  bool isImmThumbSR() const {
1020    if (!isImm()) return false;
1021    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1022    if (!CE) return false;
1023    int64_t Value = CE->getValue();
1024    return Value > 0 && Value < 33;
1025  }
1026  bool isPKHLSLImm() const {
1027    if (!isImm()) return false;
1028    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1029    if (!CE) return false;
1030    int64_t Value = CE->getValue();
1031    return Value >= 0 && Value < 32;
1032  }
1033  bool isPKHASRImm() const {
1034    if (!isImm()) return false;
1035    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1036    if (!CE) return false;
1037    int64_t Value = CE->getValue();
1038    return Value > 0 && Value <= 32;
1039  }
1040  bool isAdrLabel() const {
1041    // If we have an immediate that's not a constant, treat it as a label
1042    // reference needing a fixup.
1043    if (isImm() && !isa<MCConstantExpr>(getImm()))
1044      return true;
1045
1046    // If it is a constant, it must fit into a modified immediate encoding.
1047    if (!isImm()) return false;
1048    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1049    if (!CE) return false;
1050    int64_t Value = CE->getValue();
1051    return (ARM_AM::getSOImmVal(Value) != -1 ||
1052            ARM_AM::getSOImmVal(-Value) != -1);;
1053  }
1054  bool isT2SOImm() const {
1055    if (!isImm()) return false;
1056    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1057    if (!CE) return false;
1058    int64_t Value = CE->getValue();
1059    return ARM_AM::getT2SOImmVal(Value) != -1;
1060  }
1061  bool isT2SOImmNot() const {
1062    if (!isImm()) return false;
1063    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1064    if (!CE) return false;
1065    int64_t Value = CE->getValue();
1066    return ARM_AM::getT2SOImmVal(Value) == -1 &&
1067      ARM_AM::getT2SOImmVal(~Value) != -1;
1068  }
1069  bool isT2SOImmNeg() const {
1070    if (!isImm()) return false;
1071    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1072    if (!CE) return false;
1073    int64_t Value = CE->getValue();
1074    // Only use this when not representable as a plain so_imm.
1075    return ARM_AM::getT2SOImmVal(Value) == -1 &&
1076      ARM_AM::getT2SOImmVal(-Value) != -1;
1077  }
1078  bool isSetEndImm() const {
1079    if (!isImm()) return false;
1080    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1081    if (!CE) return false;
1082    int64_t Value = CE->getValue();
1083    return Value == 1 || Value == 0;
1084  }
1085  bool isReg() const override { return Kind == k_Register; }
1086  bool isRegList() const { return Kind == k_RegisterList; }
1087  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1088  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1089  bool isToken() const override { return Kind == k_Token; }
1090  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1091  bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1092  bool isMem() const override { return Kind == k_Memory; }
1093  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1094  bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1095  bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1096  bool isRotImm() const { return Kind == k_RotateImmediate; }
1097  bool isModImm() const { return Kind == k_ModifiedImmediate; }
1098  bool isModImmNot() const {
1099    if (!isImm()) return false;
1100    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1101    if (!CE) return false;
1102    int64_t Value = CE->getValue();
1103    return ARM_AM::getSOImmVal(~Value) != -1;
1104  }
1105  bool isModImmNeg() const {
1106    if (!isImm()) return false;
1107    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1108    if (!CE) return false;
1109    int64_t Value = CE->getValue();
1110    return ARM_AM::getSOImmVal(Value) == -1 &&
1111      ARM_AM::getSOImmVal(-Value) != -1;
1112  }
1113  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1114  bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1115  bool isPostIdxReg() const {
1116    return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1117  }
1118  bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1119    if (!isMem())
1120      return false;
1121    // No offset of any kind.
1122    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1123     (alignOK || Memory.Alignment == Alignment);
1124  }
1125  bool isMemPCRelImm12() const {
1126    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1127      return false;
1128    // Base register must be PC.
1129    if (Memory.BaseRegNum != ARM::PC)
1130      return false;
1131    // Immediate offset in range [-4095, 4095].
1132    if (!Memory.OffsetImm) return true;
1133    int64_t Val = Memory.OffsetImm->getValue();
1134    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1135  }
1136  bool isAlignedMemory() const {
1137    return isMemNoOffset(true);
1138  }
1139  bool isAlignedMemoryNone() const {
1140    return isMemNoOffset(false, 0);
1141  }
1142  bool isDupAlignedMemoryNone() const {
1143    return isMemNoOffset(false, 0);
1144  }
1145  bool isAlignedMemory16() const {
1146    if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1147      return true;
1148    return isMemNoOffset(false, 0);
1149  }
1150  bool isDupAlignedMemory16() const {
1151    if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1152      return true;
1153    return isMemNoOffset(false, 0);
1154  }
1155  bool isAlignedMemory32() const {
1156    if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1157      return true;
1158    return isMemNoOffset(false, 0);
1159  }
1160  bool isDupAlignedMemory32() const {
1161    if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1162      return true;
1163    return isMemNoOffset(false, 0);
1164  }
1165  bool isAlignedMemory64() const {
1166    if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1167      return true;
1168    return isMemNoOffset(false, 0);
1169  }
1170  bool isDupAlignedMemory64() const {
1171    if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1172      return true;
1173    return isMemNoOffset(false, 0);
1174  }
1175  bool isAlignedMemory64or128() const {
1176    if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1177      return true;
1178    if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1179      return true;
1180    return isMemNoOffset(false, 0);
1181  }
1182  bool isDupAlignedMemory64or128() const {
1183    if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1184      return true;
1185    if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1186      return true;
1187    return isMemNoOffset(false, 0);
1188  }
1189  bool isAlignedMemory64or128or256() const {
1190    if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1191      return true;
1192    if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1193      return true;
1194    if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1195      return true;
1196    return isMemNoOffset(false, 0);
1197  }
1198  bool isAddrMode2() const {
1199    if (!isMem() || Memory.Alignment != 0) return false;
1200    // Check for register offset.
1201    if (Memory.OffsetRegNum) return true;
1202    // Immediate offset in range [-4095, 4095].
1203    if (!Memory.OffsetImm) return true;
1204    int64_t Val = Memory.OffsetImm->getValue();
1205    return Val > -4096 && Val < 4096;
1206  }
1207  bool isAM2OffsetImm() const {
1208    if (!isImm()) return false;
1209    // Immediate offset in range [-4095, 4095].
1210    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1211    if (!CE) return false;
1212    int64_t Val = CE->getValue();
1213    return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1214  }
1215  bool isAddrMode3() const {
1216    // If we have an immediate that's not a constant, treat it as a label
1217    // reference needing a fixup. If it is a constant, it's something else
1218    // and we reject it.
1219    if (isImm() && !isa<MCConstantExpr>(getImm()))
1220      return true;
1221    if (!isMem() || Memory.Alignment != 0) return false;
1222    // No shifts are legal for AM3.
1223    if (Memory.ShiftType != ARM_AM::no_shift) return false;
1224    // Check for register offset.
1225    if (Memory.OffsetRegNum) return true;
1226    // Immediate offset in range [-255, 255].
1227    if (!Memory.OffsetImm) return true;
1228    int64_t Val = Memory.OffsetImm->getValue();
1229    // The #-0 offset is encoded as INT32_MIN, and we have to check
1230    // for this too.
1231    return (Val > -256 && Val < 256) || Val == INT32_MIN;
1232  }
1233  bool isAM3Offset() const {
1234    if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1235      return false;
1236    if (Kind == k_PostIndexRegister)
1237      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1238    // Immediate offset in range [-255, 255].
1239    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1240    if (!CE) return false;
1241    int64_t Val = CE->getValue();
1242    // Special case, #-0 is INT32_MIN.
1243    return (Val > -256 && Val < 256) || Val == INT32_MIN;
1244  }
1245  bool isAddrMode5() const {
1246    // If we have an immediate that's not a constant, treat it as a label
1247    // reference needing a fixup. If it is a constant, it's something else
1248    // and we reject it.
1249    if (isImm() && !isa<MCConstantExpr>(getImm()))
1250      return true;
1251    if (!isMem() || Memory.Alignment != 0) return false;
1252    // Check for register offset.
1253    if (Memory.OffsetRegNum) return false;
1254    // Immediate offset in range [-1020, 1020] and a multiple of 4.
1255    if (!Memory.OffsetImm) return true;
1256    int64_t Val = Memory.OffsetImm->getValue();
1257    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1258      Val == INT32_MIN;
1259  }
1260  bool isMemTBB() const {
1261    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1262        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1263      return false;
1264    return true;
1265  }
1266  bool isMemTBH() const {
1267    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1268        Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1269        Memory.Alignment != 0 )
1270      return false;
1271    return true;
1272  }
1273  bool isMemRegOffset() const {
1274    if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1275      return false;
1276    return true;
1277  }
1278  bool isT2MemRegOffset() const {
1279    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1280        Memory.Alignment != 0)
1281      return false;
1282    // Only lsl #{0, 1, 2, 3} allowed.
1283    if (Memory.ShiftType == ARM_AM::no_shift)
1284      return true;
1285    if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1286      return false;
1287    return true;
1288  }
1289  bool isMemThumbRR() const {
1290    // Thumb reg+reg addressing is simple. Just two registers, a base and
1291    // an offset. No shifts, negations or any other complicating factors.
1292    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1293        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1294      return false;
1295    return isARMLowRegister(Memory.BaseRegNum) &&
1296      (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1297  }
1298  bool isMemThumbRIs4() const {
1299    if (!isMem() || Memory.OffsetRegNum != 0 ||
1300        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1301      return false;
1302    // Immediate offset, multiple of 4 in range [0, 124].
1303    if (!Memory.OffsetImm) return true;
1304    int64_t Val = Memory.OffsetImm->getValue();
1305    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1306  }
1307  bool isMemThumbRIs2() const {
1308    if (!isMem() || Memory.OffsetRegNum != 0 ||
1309        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1310      return false;
1311    // Immediate offset, multiple of 4 in range [0, 62].
1312    if (!Memory.OffsetImm) return true;
1313    int64_t Val = Memory.OffsetImm->getValue();
1314    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1315  }
1316  bool isMemThumbRIs1() const {
1317    if (!isMem() || Memory.OffsetRegNum != 0 ||
1318        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1319      return false;
1320    // Immediate offset in range [0, 31].
1321    if (!Memory.OffsetImm) return true;
1322    int64_t Val = Memory.OffsetImm->getValue();
1323    return Val >= 0 && Val <= 31;
1324  }
1325  bool isMemThumbSPI() const {
1326    if (!isMem() || Memory.OffsetRegNum != 0 ||
1327        Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1328      return false;
1329    // Immediate offset, multiple of 4 in range [0, 1020].
1330    if (!Memory.OffsetImm) return true;
1331    int64_t Val = Memory.OffsetImm->getValue();
1332    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1333  }
1334  bool isMemImm8s4Offset() const {
1335    // If we have an immediate that's not a constant, treat it as a label
1336    // reference needing a fixup. If it is a constant, it's something else
1337    // and we reject it.
1338    if (isImm() && !isa<MCConstantExpr>(getImm()))
1339      return true;
1340    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1341      return false;
1342    // Immediate offset a multiple of 4 in range [-1020, 1020].
1343    if (!Memory.OffsetImm) return true;
1344    int64_t Val = Memory.OffsetImm->getValue();
1345    // Special case, #-0 is INT32_MIN.
1346    return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1347  }
1348  bool isMemImm0_1020s4Offset() const {
1349    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1350      return false;
1351    // Immediate offset a multiple of 4 in range [0, 1020].
1352    if (!Memory.OffsetImm) return true;
1353    int64_t Val = Memory.OffsetImm->getValue();
1354    return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1355  }
1356  bool isMemImm8Offset() const {
1357    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1358      return false;
1359    // Base reg of PC isn't allowed for these encodings.
1360    if (Memory.BaseRegNum == ARM::PC) return false;
1361    // Immediate offset in range [-255, 255].
1362    if (!Memory.OffsetImm) return true;
1363    int64_t Val = Memory.OffsetImm->getValue();
1364    return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1365  }
1366  bool isMemPosImm8Offset() const {
1367    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1368      return false;
1369    // Immediate offset in range [0, 255].
1370    if (!Memory.OffsetImm) return true;
1371    int64_t Val = Memory.OffsetImm->getValue();
1372    return Val >= 0 && Val < 256;
1373  }
1374  bool isMemNegImm8Offset() const {
1375    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1376      return false;
1377    // Base reg of PC isn't allowed for these encodings.
1378    if (Memory.BaseRegNum == ARM::PC) return false;
1379    // Immediate offset in range [-255, -1].
1380    if (!Memory.OffsetImm) return false;
1381    int64_t Val = Memory.OffsetImm->getValue();
1382    return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1383  }
1384  bool isMemUImm12Offset() const {
1385    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1386      return false;
1387    // Immediate offset in range [0, 4095].
1388    if (!Memory.OffsetImm) return true;
1389    int64_t Val = Memory.OffsetImm->getValue();
1390    return (Val >= 0 && Val < 4096);
1391  }
1392  bool isMemImm12Offset() const {
1393    // If we have an immediate that's not a constant, treat it as a label
1394    // reference needing a fixup. If it is a constant, it's something else
1395    // and we reject it.
1396    if (isImm() && !isa<MCConstantExpr>(getImm()))
1397      return true;
1398
1399    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1400      return false;
1401    // Immediate offset in range [-4095, 4095].
1402    if (!Memory.OffsetImm) return true;
1403    int64_t Val = Memory.OffsetImm->getValue();
1404    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1405  }
1406  bool isPostIdxImm8() const {
1407    if (!isImm()) return false;
1408    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1409    if (!CE) return false;
1410    int64_t Val = CE->getValue();
1411    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1412  }
1413  bool isPostIdxImm8s4() const {
1414    if (!isImm()) return false;
1415    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1416    if (!CE) return false;
1417    int64_t Val = CE->getValue();
1418    return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1419      (Val == INT32_MIN);
1420  }
1421
1422  bool isMSRMask() const { return Kind == k_MSRMask; }
1423  bool isBankedReg() const { return Kind == k_BankedReg; }
1424  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1425
1426  // NEON operands.
1427  bool isSingleSpacedVectorList() const {
1428    return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1429  }
1430  bool isDoubleSpacedVectorList() const {
1431    return Kind == k_VectorList && VectorList.isDoubleSpaced;
1432  }
1433  bool isVecListOneD() const {
1434    if (!isSingleSpacedVectorList()) return false;
1435    return VectorList.Count == 1;
1436  }
1437
1438  bool isVecListDPair() const {
1439    if (!isSingleSpacedVectorList()) return false;
1440    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1441              .contains(VectorList.RegNum));
1442  }
1443
1444  bool isVecListThreeD() const {
1445    if (!isSingleSpacedVectorList()) return false;
1446    return VectorList.Count == 3;
1447  }
1448
1449  bool isVecListFourD() const {
1450    if (!isSingleSpacedVectorList()) return false;
1451    return VectorList.Count == 4;
1452  }
1453
1454  bool isVecListDPairSpaced() const {
1455    if (Kind != k_VectorList) return false;
1456    if (isSingleSpacedVectorList()) return false;
1457    return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1458              .contains(VectorList.RegNum));
1459  }
1460
1461  bool isVecListThreeQ() const {
1462    if (!isDoubleSpacedVectorList()) return false;
1463    return VectorList.Count == 3;
1464  }
1465
1466  bool isVecListFourQ() const {
1467    if (!isDoubleSpacedVectorList()) return false;
1468    return VectorList.Count == 4;
1469  }
1470
1471  bool isSingleSpacedVectorAllLanes() const {
1472    return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1473  }
1474  bool isDoubleSpacedVectorAllLanes() const {
1475    return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1476  }
1477  bool isVecListOneDAllLanes() const {
1478    if (!isSingleSpacedVectorAllLanes()) return false;
1479    return VectorList.Count == 1;
1480  }
1481
1482  bool isVecListDPairAllLanes() const {
1483    if (!isSingleSpacedVectorAllLanes()) return false;
1484    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1485              .contains(VectorList.RegNum));
1486  }
1487
1488  bool isVecListDPairSpacedAllLanes() const {
1489    if (!isDoubleSpacedVectorAllLanes()) return false;
1490    return VectorList.Count == 2;
1491  }
1492
1493  bool isVecListThreeDAllLanes() const {
1494    if (!isSingleSpacedVectorAllLanes()) return false;
1495    return VectorList.Count == 3;
1496  }
1497
1498  bool isVecListThreeQAllLanes() const {
1499    if (!isDoubleSpacedVectorAllLanes()) return false;
1500    return VectorList.Count == 3;
1501  }
1502
1503  bool isVecListFourDAllLanes() const {
1504    if (!isSingleSpacedVectorAllLanes()) return false;
1505    return VectorList.Count == 4;
1506  }
1507
1508  bool isVecListFourQAllLanes() const {
1509    if (!isDoubleSpacedVectorAllLanes()) return false;
1510    return VectorList.Count == 4;
1511  }
1512
1513  bool isSingleSpacedVectorIndexed() const {
1514    return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1515  }
1516  bool isDoubleSpacedVectorIndexed() const {
1517    return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1518  }
1519  bool isVecListOneDByteIndexed() const {
1520    if (!isSingleSpacedVectorIndexed()) return false;
1521    return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1522  }
1523
1524  bool isVecListOneDHWordIndexed() const {
1525    if (!isSingleSpacedVectorIndexed()) return false;
1526    return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1527  }
1528
1529  bool isVecListOneDWordIndexed() const {
1530    if (!isSingleSpacedVectorIndexed()) return false;
1531    return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1532  }
1533
1534  bool isVecListTwoDByteIndexed() const {
1535    if (!isSingleSpacedVectorIndexed()) return false;
1536    return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1537  }
1538
1539  bool isVecListTwoDHWordIndexed() const {
1540    if (!isSingleSpacedVectorIndexed()) return false;
1541    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1542  }
1543
1544  bool isVecListTwoQWordIndexed() const {
1545    if (!isDoubleSpacedVectorIndexed()) return false;
1546    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1547  }
1548
1549  bool isVecListTwoQHWordIndexed() const {
1550    if (!isDoubleSpacedVectorIndexed()) return false;
1551    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1552  }
1553
1554  bool isVecListTwoDWordIndexed() const {
1555    if (!isSingleSpacedVectorIndexed()) return false;
1556    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1557  }
1558
1559  bool isVecListThreeDByteIndexed() const {
1560    if (!isSingleSpacedVectorIndexed()) return false;
1561    return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1562  }
1563
1564  bool isVecListThreeDHWordIndexed() const {
1565    if (!isSingleSpacedVectorIndexed()) return false;
1566    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1567  }
1568
1569  bool isVecListThreeQWordIndexed() const {
1570    if (!isDoubleSpacedVectorIndexed()) return false;
1571    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1572  }
1573
1574  bool isVecListThreeQHWordIndexed() const {
1575    if (!isDoubleSpacedVectorIndexed()) return false;
1576    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1577  }
1578
1579  bool isVecListThreeDWordIndexed() const {
1580    if (!isSingleSpacedVectorIndexed()) return false;
1581    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1582  }
1583
1584  bool isVecListFourDByteIndexed() const {
1585    if (!isSingleSpacedVectorIndexed()) return false;
1586    return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1587  }
1588
1589  bool isVecListFourDHWordIndexed() const {
1590    if (!isSingleSpacedVectorIndexed()) return false;
1591    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1592  }
1593
1594  bool isVecListFourQWordIndexed() const {
1595    if (!isDoubleSpacedVectorIndexed()) return false;
1596    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1597  }
1598
1599  bool isVecListFourQHWordIndexed() const {
1600    if (!isDoubleSpacedVectorIndexed()) return false;
1601    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1602  }
1603
1604  bool isVecListFourDWordIndexed() const {
1605    if (!isSingleSpacedVectorIndexed()) return false;
1606    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1607  }
1608
1609  bool isVectorIndex8() const {
1610    if (Kind != k_VectorIndex) return false;
1611    return VectorIndex.Val < 8;
1612  }
1613  bool isVectorIndex16() const {
1614    if (Kind != k_VectorIndex) return false;
1615    return VectorIndex.Val < 4;
1616  }
1617  bool isVectorIndex32() const {
1618    if (Kind != k_VectorIndex) return false;
1619    return VectorIndex.Val < 2;
1620  }
1621
1622  bool isNEONi8splat() const {
1623    if (!isImm()) return false;
1624    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1625    // Must be a constant.
1626    if (!CE) return false;
1627    int64_t Value = CE->getValue();
1628    // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1629    // value.
1630    return Value >= 0 && Value < 256;
1631  }
1632
1633  bool isNEONi16splat() const {
1634    if (isNEONByteReplicate(2))
1635      return false; // Leave that for bytes replication and forbid by default.
1636    if (!isImm())
1637      return false;
1638    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1639    // Must be a constant.
1640    if (!CE) return false;
1641    unsigned Value = CE->getValue();
1642    return ARM_AM::isNEONi16splat(Value);
1643  }
1644
1645  bool isNEONi16splatNot() const {
1646    if (!isImm())
1647      return false;
1648    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1649    // Must be a constant.
1650    if (!CE) return false;
1651    unsigned Value = CE->getValue();
1652    return ARM_AM::isNEONi16splat(~Value & 0xffff);
1653  }
1654
1655  bool isNEONi32splat() const {
1656    if (isNEONByteReplicate(4))
1657      return false; // Leave that for bytes replication and forbid by default.
1658    if (!isImm())
1659      return false;
1660    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1661    // Must be a constant.
1662    if (!CE) return false;
1663    unsigned Value = CE->getValue();
1664    return ARM_AM::isNEONi32splat(Value);
1665  }
1666
1667  bool isNEONi32splatNot() const {
1668    if (!isImm())
1669      return false;
1670    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1671    // Must be a constant.
1672    if (!CE) return false;
1673    unsigned Value = CE->getValue();
1674    return ARM_AM::isNEONi32splat(~Value);
1675  }
1676
1677  bool isNEONByteReplicate(unsigned NumBytes) const {
1678    if (!isImm())
1679      return false;
1680    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1681    // Must be a constant.
1682    if (!CE)
1683      return false;
1684    int64_t Value = CE->getValue();
1685    if (!Value)
1686      return false; // Don't bother with zero.
1687
1688    unsigned char B = Value & 0xff;
1689    for (unsigned i = 1; i < NumBytes; ++i) {
1690      Value >>= 8;
1691      if ((Value & 0xff) != B)
1692        return false;
1693    }
1694    return true;
1695  }
1696  bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
1697  bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1698  bool isNEONi32vmov() const {
1699    if (isNEONByteReplicate(4))
1700      return false; // Let it to be classified as byte-replicate case.
1701    if (!isImm())
1702      return false;
1703    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1704    // Must be a constant.
1705    if (!CE)
1706      return false;
1707    int64_t Value = CE->getValue();
1708    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1709    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1710    // FIXME: This is probably wrong and a copy and paste from previous example
1711    return (Value >= 0 && Value < 256) ||
1712      (Value >= 0x0100 && Value <= 0xff00) ||
1713      (Value >= 0x010000 && Value <= 0xff0000) ||
1714      (Value >= 0x01000000 && Value <= 0xff000000) ||
1715      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1716      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1717  }
1718  bool isNEONi32vmovNeg() const {
1719    if (!isImm()) return false;
1720    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1721    // Must be a constant.
1722    if (!CE) return false;
1723    int64_t Value = ~CE->getValue();
1724    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1725    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1726    // FIXME: This is probably wrong and a copy and paste from previous example
1727    return (Value >= 0 && Value < 256) ||
1728      (Value >= 0x0100 && Value <= 0xff00) ||
1729      (Value >= 0x010000 && Value <= 0xff0000) ||
1730      (Value >= 0x01000000 && Value <= 0xff000000) ||
1731      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1732      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1733  }
1734
1735  bool isNEONi64splat() const {
1736    if (!isImm()) return false;
1737    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1738    // Must be a constant.
1739    if (!CE) return false;
1740    uint64_t Value = CE->getValue();
1741    // i64 value with each byte being either 0 or 0xff.
1742    for (unsigned i = 0; i < 8; ++i)
1743      if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1744    return true;
1745  }
1746
1747  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1748    // Add as immediates when possible.  Null MCExpr = 0.
1749    if (!Expr)
1750      Inst.addOperand(MCOperand::CreateImm(0));
1751    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1752      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1753    else
1754      Inst.addOperand(MCOperand::CreateExpr(Expr));
1755  }
1756
1757  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1758    assert(N == 2 && "Invalid number of operands!");
1759    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1760    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1761    Inst.addOperand(MCOperand::CreateReg(RegNum));
1762  }
1763
1764  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1765    assert(N == 1 && "Invalid number of operands!");
1766    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1767  }
1768
1769  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1770    assert(N == 1 && "Invalid number of operands!");
1771    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1772  }
1773
1774  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1775    assert(N == 1 && "Invalid number of operands!");
1776    Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1777  }
1778
1779  void addITMaskOperands(MCInst &Inst, unsigned N) const {
1780    assert(N == 1 && "Invalid number of operands!");
1781    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1782  }
1783
1784  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1785    assert(N == 1 && "Invalid number of operands!");
1786    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1787  }
1788
1789  void addCCOutOperands(MCInst &Inst, unsigned N) const {
1790    assert(N == 1 && "Invalid number of operands!");
1791    Inst.addOperand(MCOperand::CreateReg(getReg()));
1792  }
1793
1794  void addRegOperands(MCInst &Inst, unsigned N) const {
1795    assert(N == 1 && "Invalid number of operands!");
1796    Inst.addOperand(MCOperand::CreateReg(getReg()));
1797  }
1798
1799  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1800    assert(N == 3 && "Invalid number of operands!");
1801    assert(isRegShiftedReg() &&
1802           "addRegShiftedRegOperands() on non-RegShiftedReg!");
1803    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1804    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1805    Inst.addOperand(MCOperand::CreateImm(
1806      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1807  }
1808
1809  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1810    assert(N == 2 && "Invalid number of operands!");
1811    assert(isRegShiftedImm() &&
1812           "addRegShiftedImmOperands() on non-RegShiftedImm!");
1813    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1814    // Shift of #32 is encoded as 0 where permitted
1815    unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1816    Inst.addOperand(MCOperand::CreateImm(
1817      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1818  }
1819
1820  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1821    assert(N == 1 && "Invalid number of operands!");
1822    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1823                                         ShifterImm.Imm));
1824  }
1825
1826  void addRegListOperands(MCInst &Inst, unsigned N) const {
1827    assert(N == 1 && "Invalid number of operands!");
1828    const SmallVectorImpl<unsigned> &RegList = getRegList();
1829    for (SmallVectorImpl<unsigned>::const_iterator
1830           I = RegList.begin(), E = RegList.end(); I != E; ++I)
1831      Inst.addOperand(MCOperand::CreateReg(*I));
1832  }
1833
1834  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1835    addRegListOperands(Inst, N);
1836  }
1837
1838  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1839    addRegListOperands(Inst, N);
1840  }
1841
1842  void addRotImmOperands(MCInst &Inst, unsigned N) const {
1843    assert(N == 1 && "Invalid number of operands!");
1844    // Encoded as val>>3. The printer handles display as 8, 16, 24.
1845    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1846  }
1847
1848  void addModImmOperands(MCInst &Inst, unsigned N) const {
1849    assert(N == 1 && "Invalid number of operands!");
1850
1851    // Support for fixups (MCFixup)
1852    if (isImm())
1853      return addImmOperands(Inst, N);
1854
1855    Inst.addOperand(MCOperand::CreateImm(ModImm.Bits | (ModImm.Rot << 7)));
1856  }
1857
1858  void addModImmNotOperands(MCInst &Inst, unsigned N) const {
1859    assert(N == 1 && "Invalid number of operands!");
1860    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1861    uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
1862    Inst.addOperand(MCOperand::CreateImm(Enc));
1863  }
1864
1865  void addModImmNegOperands(MCInst &Inst, unsigned N) const {
1866    assert(N == 1 && "Invalid number of operands!");
1867    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1868    uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
1869    Inst.addOperand(MCOperand::CreateImm(Enc));
1870  }
1871
1872  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1873    assert(N == 1 && "Invalid number of operands!");
1874    // Munge the lsb/width into a bitfield mask.
1875    unsigned lsb = Bitfield.LSB;
1876    unsigned width = Bitfield.Width;
1877    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1878    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1879                      (32 - (lsb + width)));
1880    Inst.addOperand(MCOperand::CreateImm(Mask));
1881  }
1882
1883  void addImmOperands(MCInst &Inst, unsigned N) const {
1884    assert(N == 1 && "Invalid number of operands!");
1885    addExpr(Inst, getImm());
1886  }
1887
1888  void addFBits16Operands(MCInst &Inst, unsigned N) const {
1889    assert(N == 1 && "Invalid number of operands!");
1890    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1891    Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1892  }
1893
1894  void addFBits32Operands(MCInst &Inst, unsigned N) const {
1895    assert(N == 1 && "Invalid number of operands!");
1896    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1897    Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1898  }
1899
1900  void addFPImmOperands(MCInst &Inst, unsigned N) const {
1901    assert(N == 1 && "Invalid number of operands!");
1902    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1903    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1904    Inst.addOperand(MCOperand::CreateImm(Val));
1905  }
1906
1907  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1908    assert(N == 1 && "Invalid number of operands!");
1909    // FIXME: We really want to scale the value here, but the LDRD/STRD
1910    // instruction don't encode operands that way yet.
1911    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1912    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1913  }
1914
1915  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1916    assert(N == 1 && "Invalid number of operands!");
1917    // The immediate is scaled by four in the encoding and is stored
1918    // in the MCInst as such. Lop off the low two bits here.
1919    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1920    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1921  }
1922
1923  void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1924    assert(N == 1 && "Invalid number of operands!");
1925    // The immediate is scaled by four in the encoding and is stored
1926    // in the MCInst as such. Lop off the low two bits here.
1927    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1928    Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1929  }
1930
1931  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1932    assert(N == 1 && "Invalid number of operands!");
1933    // The immediate is scaled by four in the encoding and is stored
1934    // in the MCInst as such. Lop off the low two bits here.
1935    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1936    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1937  }
1938
1939  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1940    assert(N == 1 && "Invalid number of operands!");
1941    // The constant encodes as the immediate-1, and we store in the instruction
1942    // the bits as encoded, so subtract off one here.
1943    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1944    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1945  }
1946
1947  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1948    assert(N == 1 && "Invalid number of operands!");
1949    // The constant encodes as the immediate-1, and we store in the instruction
1950    // the bits as encoded, so subtract off one here.
1951    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1952    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1953  }
1954
1955  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1956    assert(N == 1 && "Invalid number of operands!");
1957    // The constant encodes as the immediate, except for 32, which encodes as
1958    // zero.
1959    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1960    unsigned Imm = CE->getValue();
1961    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1962  }
1963
1964  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1965    assert(N == 1 && "Invalid number of operands!");
1966    // An ASR value of 32 encodes as 0, so that's how we want to add it to
1967    // the instruction as well.
1968    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1969    int Val = CE->getValue();
1970    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1971  }
1972
1973  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1974    assert(N == 1 && "Invalid number of operands!");
1975    // The operand is actually a t2_so_imm, but we have its bitwise
1976    // negation in the assembly source, so twiddle it here.
1977    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1978    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1979  }
1980
1981  void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1982    assert(N == 1 && "Invalid number of operands!");
1983    // The operand is actually a t2_so_imm, but we have its
1984    // negation in the assembly source, so twiddle it here.
1985    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1986    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1987  }
1988
1989  void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1990    assert(N == 1 && "Invalid number of operands!");
1991    // The operand is actually an imm0_4095, but we have its
1992    // negation in the assembly source, so twiddle it here.
1993    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1994    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1995  }
1996
1997  void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1998    if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1999      Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
2000      return;
2001    }
2002
2003    const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2004    assert(SR && "Unknown value type!");
2005    Inst.addOperand(MCOperand::CreateExpr(SR));
2006  }
2007
2008  void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2009    assert(N == 1 && "Invalid number of operands!");
2010    if (isImm()) {
2011      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2012      if (CE) {
2013        Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
2014        return;
2015      }
2016
2017      const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2018      assert(SR && "Unknown value type!");
2019      Inst.addOperand(MCOperand::CreateExpr(SR));
2020      return;
2021    }
2022
2023    assert(isMem()  && "Unknown value type!");
2024    assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
2025    Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
2026  }
2027
2028  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2029    assert(N == 1 && "Invalid number of operands!");
2030    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
2031  }
2032
2033  void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2034    assert(N == 1 && "Invalid number of operands!");
2035    Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
2036  }
2037
2038  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2039    assert(N == 1 && "Invalid number of operands!");
2040    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2041  }
2042
2043  void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2044    assert(N == 1 && "Invalid number of operands!");
2045    int32_t Imm = Memory.OffsetImm->getValue();
2046    Inst.addOperand(MCOperand::CreateImm(Imm));
2047  }
2048
2049  void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2050    assert(N == 1 && "Invalid number of operands!");
2051    assert(isImm() && "Not an immediate!");
2052
2053    // If we have an immediate that's not a constant, treat it as a label
2054    // reference needing a fixup.
2055    if (!isa<MCConstantExpr>(getImm())) {
2056      Inst.addOperand(MCOperand::CreateExpr(getImm()));
2057      return;
2058    }
2059
2060    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2061    int Val = CE->getValue();
2062    Inst.addOperand(MCOperand::CreateImm(Val));
2063  }
2064
2065  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2066    assert(N == 2 && "Invalid number of operands!");
2067    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2068    Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
2069  }
2070
2071  void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2072    addAlignedMemoryOperands(Inst, N);
2073  }
2074
2075  void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2076    addAlignedMemoryOperands(Inst, N);
2077  }
2078
2079  void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2080    addAlignedMemoryOperands(Inst, N);
2081  }
2082
2083  void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2084    addAlignedMemoryOperands(Inst, N);
2085  }
2086
2087  void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2088    addAlignedMemoryOperands(Inst, N);
2089  }
2090
2091  void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2092    addAlignedMemoryOperands(Inst, N);
2093  }
2094
2095  void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2096    addAlignedMemoryOperands(Inst, N);
2097  }
2098
2099  void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2100    addAlignedMemoryOperands(Inst, N);
2101  }
2102
2103  void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2104    addAlignedMemoryOperands(Inst, N);
2105  }
2106
2107  void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2108    addAlignedMemoryOperands(Inst, N);
2109  }
2110
2111  void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2112    addAlignedMemoryOperands(Inst, N);
2113  }
2114
2115  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2116    assert(N == 3 && "Invalid number of operands!");
2117    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2118    if (!Memory.OffsetRegNum) {
2119      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2120      // Special case for #-0
2121      if (Val == INT32_MIN) Val = 0;
2122      if (Val < 0) Val = -Val;
2123      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2124    } else {
2125      // For register offset, we encode the shift type and negation flag
2126      // here.
2127      Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2128                              Memory.ShiftImm, Memory.ShiftType);
2129    }
2130    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2131    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2132    Inst.addOperand(MCOperand::CreateImm(Val));
2133  }
2134
2135  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2136    assert(N == 2 && "Invalid number of operands!");
2137    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2138    assert(CE && "non-constant AM2OffsetImm operand!");
2139    int32_t Val = CE->getValue();
2140    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2141    // Special case for #-0
2142    if (Val == INT32_MIN) Val = 0;
2143    if (Val < 0) Val = -Val;
2144    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2145    Inst.addOperand(MCOperand::CreateReg(0));
2146    Inst.addOperand(MCOperand::CreateImm(Val));
2147  }
2148
2149  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2150    assert(N == 3 && "Invalid number of operands!");
2151    // If we have an immediate that's not a constant, treat it as a label
2152    // reference needing a fixup. If it is a constant, it's something else
2153    // and we reject it.
2154    if (isImm()) {
2155      Inst.addOperand(MCOperand::CreateExpr(getImm()));
2156      Inst.addOperand(MCOperand::CreateReg(0));
2157      Inst.addOperand(MCOperand::CreateImm(0));
2158      return;
2159    }
2160
2161    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2162    if (!Memory.OffsetRegNum) {
2163      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2164      // Special case for #-0
2165      if (Val == INT32_MIN) Val = 0;
2166      if (Val < 0) Val = -Val;
2167      Val = ARM_AM::getAM3Opc(AddSub, Val);
2168    } else {
2169      // For register offset, we encode the shift type and negation flag
2170      // here.
2171      Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2172    }
2173    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2174    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2175    Inst.addOperand(MCOperand::CreateImm(Val));
2176  }
2177
2178  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2179    assert(N == 2 && "Invalid number of operands!");
2180    if (Kind == k_PostIndexRegister) {
2181      int32_t Val =
2182        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2183      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2184      Inst.addOperand(MCOperand::CreateImm(Val));
2185      return;
2186    }
2187
2188    // Constant offset.
2189    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2190    int32_t Val = CE->getValue();
2191    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2192    // Special case for #-0
2193    if (Val == INT32_MIN) Val = 0;
2194    if (Val < 0) Val = -Val;
2195    Val = ARM_AM::getAM3Opc(AddSub, Val);
2196    Inst.addOperand(MCOperand::CreateReg(0));
2197    Inst.addOperand(MCOperand::CreateImm(Val));
2198  }
2199
2200  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2201    assert(N == 2 && "Invalid number of operands!");
2202    // If we have an immediate that's not a constant, treat it as a label
2203    // reference needing a fixup. If it is a constant, it's something else
2204    // and we reject it.
2205    if (isImm()) {
2206      Inst.addOperand(MCOperand::CreateExpr(getImm()));
2207      Inst.addOperand(MCOperand::CreateImm(0));
2208      return;
2209    }
2210
2211    // The lower two bits are always zero and as such are not encoded.
2212    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2213    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2214    // Special case for #-0
2215    if (Val == INT32_MIN) Val = 0;
2216    if (Val < 0) Val = -Val;
2217    Val = ARM_AM::getAM5Opc(AddSub, Val);
2218    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2219    Inst.addOperand(MCOperand::CreateImm(Val));
2220  }
2221
2222  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2223    assert(N == 2 && "Invalid number of operands!");
2224    // If we have an immediate that's not a constant, treat it as a label
2225    // reference needing a fixup. If it is a constant, it's something else
2226    // and we reject it.
2227    if (isImm()) {
2228      Inst.addOperand(MCOperand::CreateExpr(getImm()));
2229      Inst.addOperand(MCOperand::CreateImm(0));
2230      return;
2231    }
2232
2233    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2234    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2235    Inst.addOperand(MCOperand::CreateImm(Val));
2236  }
2237
2238  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2239    assert(N == 2 && "Invalid number of operands!");
2240    // The lower two bits are always zero and as such are not encoded.
2241    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2242    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2243    Inst.addOperand(MCOperand::CreateImm(Val));
2244  }
2245
2246  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2247    assert(N == 2 && "Invalid number of operands!");
2248    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2249    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2250    Inst.addOperand(MCOperand::CreateImm(Val));
2251  }
2252
2253  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2254    addMemImm8OffsetOperands(Inst, N);
2255  }
2256
2257  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2258    addMemImm8OffsetOperands(Inst, N);
2259  }
2260
2261  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2262    assert(N == 2 && "Invalid number of operands!");
2263    // If this is an immediate, it's a label reference.
2264    if (isImm()) {
2265      addExpr(Inst, getImm());
2266      Inst.addOperand(MCOperand::CreateImm(0));
2267      return;
2268    }
2269
2270    // Otherwise, it's a normal memory reg+offset.
2271    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2272    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2273    Inst.addOperand(MCOperand::CreateImm(Val));
2274  }
2275
2276  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2277    assert(N == 2 && "Invalid number of operands!");
2278    // If this is an immediate, it's a label reference.
2279    if (isImm()) {
2280      addExpr(Inst, getImm());
2281      Inst.addOperand(MCOperand::CreateImm(0));
2282      return;
2283    }
2284
2285    // Otherwise, it's a normal memory reg+offset.
2286    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2287    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2288    Inst.addOperand(MCOperand::CreateImm(Val));
2289  }
2290
2291  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2292    assert(N == 2 && "Invalid number of operands!");
2293    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2294    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2295  }
2296
2297  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2298    assert(N == 2 && "Invalid number of operands!");
2299    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2300    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2301  }
2302
2303  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2304    assert(N == 3 && "Invalid number of operands!");
2305    unsigned Val =
2306      ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2307                        Memory.ShiftImm, Memory.ShiftType);
2308    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2309    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2310    Inst.addOperand(MCOperand::CreateImm(Val));
2311  }
2312
2313  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2314    assert(N == 3 && "Invalid number of operands!");
2315    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2316    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2317    Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2318  }
2319
2320  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2321    assert(N == 2 && "Invalid number of operands!");
2322    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2323    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2324  }
2325
2326  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2327    assert(N == 2 && "Invalid number of operands!");
2328    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2329    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2330    Inst.addOperand(MCOperand::CreateImm(Val));
2331  }
2332
2333  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2334    assert(N == 2 && "Invalid number of operands!");
2335    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2336    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2337    Inst.addOperand(MCOperand::CreateImm(Val));
2338  }
2339
2340  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2341    assert(N == 2 && "Invalid number of operands!");
2342    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2343    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2344    Inst.addOperand(MCOperand::CreateImm(Val));
2345  }
2346
2347  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2348    assert(N == 2 && "Invalid number of operands!");
2349    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2350    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2351    Inst.addOperand(MCOperand::CreateImm(Val));
2352  }
2353
2354  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2355    assert(N == 1 && "Invalid number of operands!");
2356    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2357    assert(CE && "non-constant post-idx-imm8 operand!");
2358    int Imm = CE->getValue();
2359    bool isAdd = Imm >= 0;
2360    if (Imm == INT32_MIN) Imm = 0;
2361    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2362    Inst.addOperand(MCOperand::CreateImm(Imm));
2363  }
2364
2365  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2366    assert(N == 1 && "Invalid number of operands!");
2367    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2368    assert(CE && "non-constant post-idx-imm8s4 operand!");
2369    int Imm = CE->getValue();
2370    bool isAdd = Imm >= 0;
2371    if (Imm == INT32_MIN) Imm = 0;
2372    // Immediate is scaled by 4.
2373    Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2374    Inst.addOperand(MCOperand::CreateImm(Imm));
2375  }
2376
2377  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2378    assert(N == 2 && "Invalid number of operands!");
2379    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2380    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2381  }
2382
2383  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2384    assert(N == 2 && "Invalid number of operands!");
2385    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2386    // The sign, shift type, and shift amount are encoded in a single operand
2387    // using the AM2 encoding helpers.
2388    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2389    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2390                                     PostIdxReg.ShiftTy);
2391    Inst.addOperand(MCOperand::CreateImm(Imm));
2392  }
2393
2394  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2395    assert(N == 1 && "Invalid number of operands!");
2396    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2397  }
2398
2399  void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2400    assert(N == 1 && "Invalid number of operands!");
2401    Inst.addOperand(MCOperand::CreateImm(unsigned(getBankedReg())));
2402  }
2403
2404  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2405    assert(N == 1 && "Invalid number of operands!");
2406    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2407  }
2408
2409  void addVecListOperands(MCInst &Inst, unsigned N) const {
2410    assert(N == 1 && "Invalid number of operands!");
2411    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2412  }
2413
2414  void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2415    assert(N == 2 && "Invalid number of operands!");
2416    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2417    Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2418  }
2419
2420  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2421    assert(N == 1 && "Invalid number of operands!");
2422    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2423  }
2424
2425  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2426    assert(N == 1 && "Invalid number of operands!");
2427    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2428  }
2429
2430  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2431    assert(N == 1 && "Invalid number of operands!");
2432    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2433  }
2434
2435  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2436    assert(N == 1 && "Invalid number of operands!");
2437    // The immediate encodes the type of constant as well as the value.
2438    // Mask in that this is an i8 splat.
2439    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2440    Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2441  }
2442
2443  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2444    assert(N == 1 && "Invalid number of operands!");
2445    // The immediate encodes the type of constant as well as the value.
2446    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2447    unsigned Value = CE->getValue();
2448    Value = ARM_AM::encodeNEONi16splat(Value);
2449    Inst.addOperand(MCOperand::CreateImm(Value));
2450  }
2451
2452  void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
2453    assert(N == 1 && "Invalid number of operands!");
2454    // The immediate encodes the type of constant as well as the value.
2455    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2456    unsigned Value = CE->getValue();
2457    Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
2458    Inst.addOperand(MCOperand::CreateImm(Value));
2459  }
2460
2461  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2462    assert(N == 1 && "Invalid number of operands!");
2463    // The immediate encodes the type of constant as well as the value.
2464    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2465    unsigned Value = CE->getValue();
2466    Value = ARM_AM::encodeNEONi32splat(Value);
2467    Inst.addOperand(MCOperand::CreateImm(Value));
2468  }
2469
2470  void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
2471    assert(N == 1 && "Invalid number of operands!");
2472    // The immediate encodes the type of constant as well as the value.
2473    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2474    unsigned Value = CE->getValue();
2475    Value = ARM_AM::encodeNEONi32splat(~Value);
2476    Inst.addOperand(MCOperand::CreateImm(Value));
2477  }
2478
2479  void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2480    assert(N == 1 && "Invalid number of operands!");
2481    // The immediate encodes the type of constant as well as the value.
2482    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2483    unsigned Value = CE->getValue();
2484    assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2485            Inst.getOpcode() == ARM::VMOVv16i8) &&
2486           "All vmvn instructions that wants to replicate non-zero byte "
2487           "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2488    unsigned B = ((~Value) & 0xff);
2489    B |= 0xe00; // cmode = 0b1110
2490    Inst.addOperand(MCOperand::CreateImm(B));
2491  }
2492  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2493    assert(N == 1 && "Invalid number of operands!");
2494    // The immediate encodes the type of constant as well as the value.
2495    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2496    unsigned Value = CE->getValue();
2497    if (Value >= 256 && Value <= 0xffff)
2498      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2499    else if (Value > 0xffff && Value <= 0xffffff)
2500      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2501    else if (Value > 0xffffff)
2502      Value = (Value >> 24) | 0x600;
2503    Inst.addOperand(MCOperand::CreateImm(Value));
2504  }
2505
2506  void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2507    assert(N == 1 && "Invalid number of operands!");
2508    // The immediate encodes the type of constant as well as the value.
2509    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2510    unsigned Value = CE->getValue();
2511    assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2512            Inst.getOpcode() == ARM::VMOVv16i8) &&
2513           "All instructions that wants to replicate non-zero byte "
2514           "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2515    unsigned B = Value & 0xff;
2516    B |= 0xe00; // cmode = 0b1110
2517    Inst.addOperand(MCOperand::CreateImm(B));
2518  }
2519  void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2520    assert(N == 1 && "Invalid number of operands!");
2521    // The immediate encodes the type of constant as well as the value.
2522    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2523    unsigned Value = ~CE->getValue();
2524    if (Value >= 256 && Value <= 0xffff)
2525      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2526    else if (Value > 0xffff && Value <= 0xffffff)
2527      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2528    else if (Value > 0xffffff)
2529      Value = (Value >> 24) | 0x600;
2530    Inst.addOperand(MCOperand::CreateImm(Value));
2531  }
2532
2533  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2534    assert(N == 1 && "Invalid number of operands!");
2535    // The immediate encodes the type of constant as well as the value.
2536    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2537    uint64_t Value = CE->getValue();
2538    unsigned Imm = 0;
2539    for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2540      Imm |= (Value & 1) << i;
2541    }
2542    Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2543  }
2544
2545  void print(raw_ostream &OS) const override;
2546
2547  static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2548    auto Op = make_unique<ARMOperand>(k_ITCondMask);
2549    Op->ITMask.Mask = Mask;
2550    Op->StartLoc = S;
2551    Op->EndLoc = S;
2552    return Op;
2553  }
2554
2555  static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2556                                                    SMLoc S) {
2557    auto Op = make_unique<ARMOperand>(k_CondCode);
2558    Op->CC.Val = CC;
2559    Op->StartLoc = S;
2560    Op->EndLoc = S;
2561    return Op;
2562  }
2563
2564  static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2565    auto Op = make_unique<ARMOperand>(k_CoprocNum);
2566    Op->Cop.Val = CopVal;
2567    Op->StartLoc = S;
2568    Op->EndLoc = S;
2569    return Op;
2570  }
2571
2572  static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2573    auto Op = make_unique<ARMOperand>(k_CoprocReg);
2574    Op->Cop.Val = CopVal;
2575    Op->StartLoc = S;
2576    Op->EndLoc = S;
2577    return Op;
2578  }
2579
2580  static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2581                                                        SMLoc E) {
2582    auto Op = make_unique<ARMOperand>(k_CoprocOption);
2583    Op->Cop.Val = Val;
2584    Op->StartLoc = S;
2585    Op->EndLoc = E;
2586    return Op;
2587  }
2588
2589  static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2590    auto Op = make_unique<ARMOperand>(k_CCOut);
2591    Op->Reg.RegNum = RegNum;
2592    Op->StartLoc = S;
2593    Op->EndLoc = S;
2594    return Op;
2595  }
2596
2597  static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2598    auto Op = make_unique<ARMOperand>(k_Token);
2599    Op->Tok.Data = Str.data();
2600    Op->Tok.Length = Str.size();
2601    Op->StartLoc = S;
2602    Op->EndLoc = S;
2603    return Op;
2604  }
2605
2606  static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2607                                               SMLoc E) {
2608    auto Op = make_unique<ARMOperand>(k_Register);
2609    Op->Reg.RegNum = RegNum;
2610    Op->StartLoc = S;
2611    Op->EndLoc = E;
2612    return Op;
2613  }
2614
2615  static std::unique_ptr<ARMOperand>
2616  CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2617                        unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2618                        SMLoc E) {
2619    auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2620    Op->RegShiftedReg.ShiftTy = ShTy;
2621    Op->RegShiftedReg.SrcReg = SrcReg;
2622    Op->RegShiftedReg.ShiftReg = ShiftReg;
2623    Op->RegShiftedReg.ShiftImm = ShiftImm;
2624    Op->StartLoc = S;
2625    Op->EndLoc = E;
2626    return Op;
2627  }
2628
2629  static std::unique_ptr<ARMOperand>
2630  CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2631                         unsigned ShiftImm, SMLoc S, SMLoc E) {
2632    auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2633    Op->RegShiftedImm.ShiftTy = ShTy;
2634    Op->RegShiftedImm.SrcReg = SrcReg;
2635    Op->RegShiftedImm.ShiftImm = ShiftImm;
2636    Op->StartLoc = S;
2637    Op->EndLoc = E;
2638    return Op;
2639  }
2640
2641  static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2642                                                      SMLoc S, SMLoc E) {
2643    auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2644    Op->ShifterImm.isASR = isASR;
2645    Op->ShifterImm.Imm = Imm;
2646    Op->StartLoc = S;
2647    Op->EndLoc = E;
2648    return Op;
2649  }
2650
2651  static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
2652                                                  SMLoc E) {
2653    auto Op = make_unique<ARMOperand>(k_RotateImmediate);
2654    Op->RotImm.Imm = Imm;
2655    Op->StartLoc = S;
2656    Op->EndLoc = E;
2657    return Op;
2658  }
2659
2660  static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
2661                                                  SMLoc S, SMLoc E) {
2662    auto Op = make_unique<ARMOperand>(k_ModifiedImmediate);
2663    Op->ModImm.Bits = Bits;
2664    Op->ModImm.Rot = Rot;
2665    Op->StartLoc = S;
2666    Op->EndLoc = E;
2667    return Op;
2668  }
2669
2670  static std::unique_ptr<ARMOperand>
2671  CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
2672    auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
2673    Op->Bitfield.LSB = LSB;
2674    Op->Bitfield.Width = Width;
2675    Op->StartLoc = S;
2676    Op->EndLoc = E;
2677    return Op;
2678  }
2679
2680  static std::unique_ptr<ARMOperand>
2681  CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
2682                SMLoc StartLoc, SMLoc EndLoc) {
2683    assert (Regs.size() > 0 && "RegList contains no registers?");
2684    KindTy Kind = k_RegisterList;
2685
2686    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2687      Kind = k_DPRRegisterList;
2688    else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2689             contains(Regs.front().second))
2690      Kind = k_SPRRegisterList;
2691
2692    // Sort based on the register encoding values.
2693    array_pod_sort(Regs.begin(), Regs.end());
2694
2695    auto Op = make_unique<ARMOperand>(Kind);
2696    for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2697           I = Regs.begin(), E = Regs.end(); I != E; ++I)
2698      Op->Registers.push_back(I->second);
2699    Op->StartLoc = StartLoc;
2700    Op->EndLoc = EndLoc;
2701    return Op;
2702  }
2703
2704  static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
2705                                                      unsigned Count,
2706                                                      bool isDoubleSpaced,
2707                                                      SMLoc S, SMLoc E) {
2708    auto Op = make_unique<ARMOperand>(k_VectorList);
2709    Op->VectorList.RegNum = RegNum;
2710    Op->VectorList.Count = Count;
2711    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2712    Op->StartLoc = S;
2713    Op->EndLoc = E;
2714    return Op;
2715  }
2716
2717  static std::unique_ptr<ARMOperand>
2718  CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
2719                           SMLoc S, SMLoc E) {
2720    auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
2721    Op->VectorList.RegNum = RegNum;
2722    Op->VectorList.Count = Count;
2723    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2724    Op->StartLoc = S;
2725    Op->EndLoc = E;
2726    return Op;
2727  }
2728
2729  static std::unique_ptr<ARMOperand>
2730  CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
2731                          bool isDoubleSpaced, SMLoc S, SMLoc E) {
2732    auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
2733    Op->VectorList.RegNum = RegNum;
2734    Op->VectorList.Count = Count;
2735    Op->VectorList.LaneIndex = Index;
2736    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2737    Op->StartLoc = S;
2738    Op->EndLoc = E;
2739    return Op;
2740  }
2741
2742  static std::unique_ptr<ARMOperand>
2743  CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
2744    auto Op = make_unique<ARMOperand>(k_VectorIndex);
2745    Op->VectorIndex.Val = Idx;
2746    Op->StartLoc = S;
2747    Op->EndLoc = E;
2748    return Op;
2749  }
2750
2751  static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
2752                                               SMLoc E) {
2753    auto Op = make_unique<ARMOperand>(k_Immediate);
2754    Op->Imm.Val = Val;
2755    Op->StartLoc = S;
2756    Op->EndLoc = E;
2757    return Op;
2758  }
2759
2760  static std::unique_ptr<ARMOperand>
2761  CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
2762            unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
2763            unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
2764            SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
2765    auto Op = make_unique<ARMOperand>(k_Memory);
2766    Op->Memory.BaseRegNum = BaseRegNum;
2767    Op->Memory.OffsetImm = OffsetImm;
2768    Op->Memory.OffsetRegNum = OffsetRegNum;
2769    Op->Memory.ShiftType = ShiftType;
2770    Op->Memory.ShiftImm = ShiftImm;
2771    Op->Memory.Alignment = Alignment;
2772    Op->Memory.isNegative = isNegative;
2773    Op->StartLoc = S;
2774    Op->EndLoc = E;
2775    Op->AlignmentLoc = AlignmentLoc;
2776    return Op;
2777  }
2778
2779  static std::unique_ptr<ARMOperand>
2780  CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
2781                   unsigned ShiftImm, SMLoc S, SMLoc E) {
2782    auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
2783    Op->PostIdxReg.RegNum = RegNum;
2784    Op->PostIdxReg.isAdd = isAdd;
2785    Op->PostIdxReg.ShiftTy = ShiftTy;
2786    Op->PostIdxReg.ShiftImm = ShiftImm;
2787    Op->StartLoc = S;
2788    Op->EndLoc = E;
2789    return Op;
2790  }
2791
2792  static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
2793                                                         SMLoc S) {
2794    auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
2795    Op->MBOpt.Val = Opt;
2796    Op->StartLoc = S;
2797    Op->EndLoc = S;
2798    return Op;
2799  }
2800
2801  static std::unique_ptr<ARMOperand>
2802  CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
2803    auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
2804    Op->ISBOpt.Val = Opt;
2805    Op->StartLoc = S;
2806    Op->EndLoc = S;
2807    return Op;
2808  }
2809
2810  static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
2811                                                      SMLoc S) {
2812    auto Op = make_unique<ARMOperand>(k_ProcIFlags);
2813    Op->IFlags.Val = IFlags;
2814    Op->StartLoc = S;
2815    Op->EndLoc = S;
2816    return Op;
2817  }
2818
2819  static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
2820    auto Op = make_unique<ARMOperand>(k_MSRMask);
2821    Op->MMask.Val = MMask;
2822    Op->StartLoc = S;
2823    Op->EndLoc = S;
2824    return Op;
2825  }
2826
2827  static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
2828    auto Op = make_unique<ARMOperand>(k_BankedReg);
2829    Op->BankedReg.Val = Reg;
2830    Op->StartLoc = S;
2831    Op->EndLoc = S;
2832    return Op;
2833  }
2834};
2835
2836} // end anonymous namespace.
2837
2838void ARMOperand::print(raw_ostream &OS) const {
2839  switch (Kind) {
2840  case k_CondCode:
2841    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2842    break;
2843  case k_CCOut:
2844    OS << "<ccout " << getReg() << ">";
2845    break;
2846  case k_ITCondMask: {
2847    static const char *const MaskStr[] = {
2848      "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2849      "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2850    };
2851    assert((ITMask.Mask & 0xf) == ITMask.Mask);
2852    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2853    break;
2854  }
2855  case k_CoprocNum:
2856    OS << "<coprocessor number: " << getCoproc() << ">";
2857    break;
2858  case k_CoprocReg:
2859    OS << "<coprocessor register: " << getCoproc() << ">";
2860    break;
2861  case k_CoprocOption:
2862    OS << "<coprocessor option: " << CoprocOption.Val << ">";
2863    break;
2864  case k_MSRMask:
2865    OS << "<mask: " << getMSRMask() << ">";
2866    break;
2867  case k_BankedReg:
2868    OS << "<banked reg: " << getBankedReg() << ">";
2869    break;
2870  case k_Immediate:
2871    getImm()->print(OS);
2872    break;
2873  case k_MemBarrierOpt:
2874    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2875    break;
2876  case k_InstSyncBarrierOpt:
2877    OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2878    break;
2879  case k_Memory:
2880    OS << "<memory "
2881       << " base:" << Memory.BaseRegNum;
2882    OS << ">";
2883    break;
2884  case k_PostIndexRegister:
2885    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2886       << PostIdxReg.RegNum;
2887    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2888      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2889         << PostIdxReg.ShiftImm;
2890    OS << ">";
2891    break;
2892  case k_ProcIFlags: {
2893    OS << "<ARM_PROC::";
2894    unsigned IFlags = getProcIFlags();
2895    for (int i=2; i >= 0; --i)
2896      if (IFlags & (1 << i))
2897        OS << ARM_PROC::IFlagsToString(1 << i);
2898    OS << ">";
2899    break;
2900  }
2901  case k_Register:
2902    OS << "<register " << getReg() << ">";
2903    break;
2904  case k_ShifterImmediate:
2905    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2906       << " #" << ShifterImm.Imm << ">";
2907    break;
2908  case k_ShiftedRegister:
2909    OS << "<so_reg_reg "
2910       << RegShiftedReg.SrcReg << " "
2911       << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2912       << " " << RegShiftedReg.ShiftReg << ">";
2913    break;
2914  case k_ShiftedImmediate:
2915    OS << "<so_reg_imm "
2916       << RegShiftedImm.SrcReg << " "
2917       << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2918       << " #" << RegShiftedImm.ShiftImm << ">";
2919    break;
2920  case k_RotateImmediate:
2921    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2922    break;
2923  case k_ModifiedImmediate:
2924    OS << "<mod_imm #" << ModImm.Bits << ", #"
2925       <<  ModImm.Rot << ")>";
2926    break;
2927  case k_BitfieldDescriptor:
2928    OS << "<bitfield " << "lsb: " << Bitfield.LSB
2929       << ", width: " << Bitfield.Width << ">";
2930    break;
2931  case k_RegisterList:
2932  case k_DPRRegisterList:
2933  case k_SPRRegisterList: {
2934    OS << "<register_list ";
2935
2936    const SmallVectorImpl<unsigned> &RegList = getRegList();
2937    for (SmallVectorImpl<unsigned>::const_iterator
2938           I = RegList.begin(), E = RegList.end(); I != E; ) {
2939      OS << *I;
2940      if (++I < E) OS << ", ";
2941    }
2942
2943    OS << ">";
2944    break;
2945  }
2946  case k_VectorList:
2947    OS << "<vector_list " << VectorList.Count << " * "
2948       << VectorList.RegNum << ">";
2949    break;
2950  case k_VectorListAllLanes:
2951    OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2952       << VectorList.RegNum << ">";
2953    break;
2954  case k_VectorListIndexed:
2955    OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2956       << VectorList.Count << " * " << VectorList.RegNum << ">";
2957    break;
2958  case k_Token:
2959    OS << "'" << getToken() << "'";
2960    break;
2961  case k_VectorIndex:
2962    OS << "<vectorindex " << getVectorIndex() << ">";
2963    break;
2964  }
2965}
2966
2967/// @name Auto-generated Match Functions
2968/// {
2969
2970static unsigned MatchRegisterName(StringRef Name);
2971
2972/// }
2973
2974bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2975                                 SMLoc &StartLoc, SMLoc &EndLoc) {
2976  const AsmToken &Tok = getParser().getTok();
2977  StartLoc = Tok.getLoc();
2978  EndLoc = Tok.getEndLoc();
2979  RegNo = tryParseRegister();
2980
2981  return (RegNo == (unsigned)-1);
2982}
2983
2984/// Try to parse a register name.  The token must be an Identifier when called,
2985/// and if it is a register name the token is eaten and the register number is
2986/// returned.  Otherwise return -1.
2987///
2988int ARMAsmParser::tryParseRegister() {
2989  MCAsmParser &Parser = getParser();
2990  const AsmToken &Tok = Parser.getTok();
2991  if (Tok.isNot(AsmToken::Identifier)) return -1;
2992
2993  std::string lowerCase = Tok.getString().lower();
2994  unsigned RegNum = MatchRegisterName(lowerCase);
2995  if (!RegNum) {
2996    RegNum = StringSwitch<unsigned>(lowerCase)
2997      .Case("r13", ARM::SP)
2998      .Case("r14", ARM::LR)
2999      .Case("r15", ARM::PC)
3000      .Case("ip", ARM::R12)
3001      // Additional register name aliases for 'gas' compatibility.
3002      .Case("a1", ARM::R0)
3003      .Case("a2", ARM::R1)
3004      .Case("a3", ARM::R2)
3005      .Case("a4", ARM::R3)
3006      .Case("v1", ARM::R4)
3007      .Case("v2", ARM::R5)
3008      .Case("v3", ARM::R6)
3009      .Case("v4", ARM::R7)
3010      .Case("v5", ARM::R8)
3011      .Case("v6", ARM::R9)
3012      .Case("v7", ARM::R10)
3013      .Case("v8", ARM::R11)
3014      .Case("sb", ARM::R9)
3015      .Case("sl", ARM::R10)
3016      .Case("fp", ARM::R11)
3017      .Default(0);
3018  }
3019  if (!RegNum) {
3020    // Check for aliases registered via .req. Canonicalize to lower case.
3021    // That's more consistent since register names are case insensitive, and
3022    // it's how the original entry was passed in from MC/MCParser/AsmParser.
3023    StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
3024    // If no match, return failure.
3025    if (Entry == RegisterReqs.end())
3026      return -1;
3027    Parser.Lex(); // Eat identifier token.
3028    return Entry->getValue();
3029  }
3030
3031  // Some FPUs only have 16 D registers, so D16-D31 are invalid
3032  if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
3033    return -1;
3034
3035  Parser.Lex(); // Eat identifier token.
3036
3037  return RegNum;
3038}
3039
3040// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
3041// If a recoverable error occurs, return 1. If an irrecoverable error
3042// occurs, return -1. An irrecoverable error is one where tokens have been
3043// consumed in the process of trying to parse the shifter (i.e., when it is
3044// indeed a shifter operand, but malformed).
3045int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
3046  MCAsmParser &Parser = getParser();
3047  SMLoc S = Parser.getTok().getLoc();
3048  const AsmToken &Tok = Parser.getTok();
3049  if (Tok.isNot(AsmToken::Identifier))
3050    return -1;
3051
3052  std::string lowerCase = Tok.getString().lower();
3053  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
3054      .Case("asl", ARM_AM::lsl)
3055      .Case("lsl", ARM_AM::lsl)
3056      .Case("lsr", ARM_AM::lsr)
3057      .Case("asr", ARM_AM::asr)
3058      .Case("ror", ARM_AM::ror)
3059      .Case("rrx", ARM_AM::rrx)
3060      .Default(ARM_AM::no_shift);
3061
3062  if (ShiftTy == ARM_AM::no_shift)
3063    return 1;
3064
3065  Parser.Lex(); // Eat the operator.
3066
3067  // The source register for the shift has already been added to the
3068  // operand list, so we need to pop it off and combine it into the shifted
3069  // register operand instead.
3070  std::unique_ptr<ARMOperand> PrevOp(
3071      (ARMOperand *)Operands.pop_back_val().release());
3072  if (!PrevOp->isReg())
3073    return Error(PrevOp->getStartLoc(), "shift must be of a register");
3074  int SrcReg = PrevOp->getReg();
3075
3076  SMLoc EndLoc;
3077  int64_t Imm = 0;
3078  int ShiftReg = 0;
3079  if (ShiftTy == ARM_AM::rrx) {
3080    // RRX Doesn't have an explicit shift amount. The encoder expects
3081    // the shift register to be the same as the source register. Seems odd,
3082    // but OK.
3083    ShiftReg = SrcReg;
3084  } else {
3085    // Figure out if this is shifted by a constant or a register (for non-RRX).
3086    if (Parser.getTok().is(AsmToken::Hash) ||
3087        Parser.getTok().is(AsmToken::Dollar)) {
3088      Parser.Lex(); // Eat hash.
3089      SMLoc ImmLoc = Parser.getTok().getLoc();
3090      const MCExpr *ShiftExpr = nullptr;
3091      if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3092        Error(ImmLoc, "invalid immediate shift value");
3093        return -1;
3094      }
3095      // The expression must be evaluatable as an immediate.
3096      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3097      if (!CE) {
3098        Error(ImmLoc, "invalid immediate shift value");
3099        return -1;
3100      }
3101      // Range check the immediate.
3102      // lsl, ror: 0 <= imm <= 31
3103      // lsr, asr: 0 <= imm <= 32
3104      Imm = CE->getValue();
3105      if (Imm < 0 ||
3106          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3107          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3108        Error(ImmLoc, "immediate shift value out of range");
3109        return -1;
3110      }
3111      // shift by zero is a nop. Always send it through as lsl.
3112      // ('as' compatibility)
3113      if (Imm == 0)
3114        ShiftTy = ARM_AM::lsl;
3115    } else if (Parser.getTok().is(AsmToken::Identifier)) {
3116      SMLoc L = Parser.getTok().getLoc();
3117      EndLoc = Parser.getTok().getEndLoc();
3118      ShiftReg = tryParseRegister();
3119      if (ShiftReg == -1) {
3120        Error(L, "expected immediate or register in shift operand");
3121        return -1;
3122      }
3123    } else {
3124      Error(Parser.getTok().getLoc(),
3125            "expected immediate or register in shift operand");
3126      return -1;
3127    }
3128  }
3129
3130  if (ShiftReg && ShiftTy != ARM_AM::rrx)
3131    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3132                                                         ShiftReg, Imm,
3133                                                         S, EndLoc));
3134  else
3135    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3136                                                          S, EndLoc));
3137
3138  return 0;
3139}
3140
3141
3142/// Try to parse a register name.  The token must be an Identifier when called.
3143/// If it's a register, an AsmOperand is created. Another AsmOperand is created
3144/// if there is a "writeback". 'true' if it's not a register.
3145///
3146/// TODO this is likely to change to allow different register types and or to
3147/// parse for a specific register type.
3148bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3149  MCAsmParser &Parser = getParser();
3150  const AsmToken &RegTok = Parser.getTok();
3151  int RegNo = tryParseRegister();
3152  if (RegNo == -1)
3153    return true;
3154
3155  Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3156                                           RegTok.getEndLoc()));
3157
3158  const AsmToken &ExclaimTok = Parser.getTok();
3159  if (ExclaimTok.is(AsmToken::Exclaim)) {
3160    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3161                                               ExclaimTok.getLoc()));
3162    Parser.Lex(); // Eat exclaim token
3163    return false;
3164  }
3165
3166  // Also check for an index operand. This is only legal for vector registers,
3167  // but that'll get caught OK in operand matching, so we don't need to
3168  // explicitly filter everything else out here.
3169  if (Parser.getTok().is(AsmToken::LBrac)) {
3170    SMLoc SIdx = Parser.getTok().getLoc();
3171    Parser.Lex(); // Eat left bracket token.
3172
3173    const MCExpr *ImmVal;
3174    if (getParser().parseExpression(ImmVal))
3175      return true;
3176    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3177    if (!MCE)
3178      return TokError("immediate value expected for vector index");
3179
3180    if (Parser.getTok().isNot(AsmToken::RBrac))
3181      return Error(Parser.getTok().getLoc(), "']' expected");
3182
3183    SMLoc E = Parser.getTok().getEndLoc();
3184    Parser.Lex(); // Eat right bracket token.
3185
3186    Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3187                                                     SIdx, E,
3188                                                     getContext()));
3189  }
3190
3191  return false;
3192}
3193
3194/// MatchCoprocessorOperandName - Try to parse an coprocessor related
3195/// instruction with a symbolic operand name.
3196/// We accept "crN" syntax for GAS compatibility.
3197/// <operand-name> ::= <prefix><number>
3198/// If CoprocOp is 'c', then:
3199///   <prefix> ::= c | cr
3200/// If CoprocOp is 'p', then :
3201///   <prefix> ::= p
3202/// <number> ::= integer in range [0, 15]
3203static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3204  // Use the same layout as the tablegen'erated register name matcher. Ugly,
3205  // but efficient.
3206  if (Name.size() < 2 || Name[0] != CoprocOp)
3207    return -1;
3208  Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
3209
3210  switch (Name.size()) {
3211  default: return -1;
3212  case 1:
3213    switch (Name[0]) {
3214    default:  return -1;
3215    case '0': return 0;
3216    case '1': return 1;
3217    case '2': return 2;
3218    case '3': return 3;
3219    case '4': return 4;
3220    case '5': return 5;
3221    case '6': return 6;
3222    case '7': return 7;
3223    case '8': return 8;
3224    case '9': return 9;
3225    }
3226  case 2:
3227    if (Name[0] != '1')
3228      return -1;
3229    switch (Name[1]) {
3230    default:  return -1;
3231    // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
3232    // However, old cores (v5/v6) did use them in that way.
3233    case '0': return 10;
3234    case '1': return 11;
3235    case '2': return 12;
3236    case '3': return 13;
3237    case '4': return 14;
3238    case '5': return 15;
3239    }
3240  }
3241}
3242
3243/// parseITCondCode - Try to parse a condition code for an IT instruction.
3244ARMAsmParser::OperandMatchResultTy
3245ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3246  MCAsmParser &Parser = getParser();
3247  SMLoc S = Parser.getTok().getLoc();
3248  const AsmToken &Tok = Parser.getTok();
3249  if (!Tok.is(AsmToken::Identifier))
3250    return MatchOperand_NoMatch;
3251  unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3252    .Case("eq", ARMCC::EQ)
3253    .Case("ne", ARMCC::NE)
3254    .Case("hs", ARMCC::HS)
3255    .Case("cs", ARMCC::HS)
3256    .Case("lo", ARMCC::LO)
3257    .Case("cc", ARMCC::LO)
3258    .Case("mi", ARMCC::MI)
3259    .Case("pl", ARMCC::PL)
3260    .Case("vs", ARMCC::VS)
3261    .Case("vc", ARMCC::VC)
3262    .Case("hi", ARMCC::HI)
3263    .Case("ls", ARMCC::LS)
3264    .Case("ge", ARMCC::GE)
3265    .Case("lt", ARMCC::LT)
3266    .Case("gt", ARMCC::GT)
3267    .Case("le", ARMCC::LE)
3268    .Case("al", ARMCC::AL)
3269    .Default(~0U);
3270  if (CC == ~0U)
3271    return MatchOperand_NoMatch;
3272  Parser.Lex(); // Eat the token.
3273
3274  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3275
3276  return MatchOperand_Success;
3277}
3278
3279/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3280/// token must be an Identifier when called, and if it is a coprocessor
3281/// number, the token is eaten and the operand is added to the operand list.
3282ARMAsmParser::OperandMatchResultTy
3283ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3284  MCAsmParser &Parser = getParser();
3285  SMLoc S = Parser.getTok().getLoc();
3286  const AsmToken &Tok = Parser.getTok();
3287  if (Tok.isNot(AsmToken::Identifier))
3288    return MatchOperand_NoMatch;
3289
3290  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3291  if (Num == -1)
3292    return MatchOperand_NoMatch;
3293  // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
3294  if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
3295    return MatchOperand_NoMatch;
3296
3297  Parser.Lex(); // Eat identifier token.
3298  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3299  return MatchOperand_Success;
3300}
3301
3302/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3303/// token must be an Identifier when called, and if it is a coprocessor
3304/// number, the token is eaten and the operand is added to the operand list.
3305ARMAsmParser::OperandMatchResultTy
3306ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3307  MCAsmParser &Parser = getParser();
3308  SMLoc S = Parser.getTok().getLoc();
3309  const AsmToken &Tok = Parser.getTok();
3310  if (Tok.isNot(AsmToken::Identifier))
3311    return MatchOperand_NoMatch;
3312
3313  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3314  if (Reg == -1)
3315    return MatchOperand_NoMatch;
3316
3317  Parser.Lex(); // Eat identifier token.
3318  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3319  return MatchOperand_Success;
3320}
3321
3322/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3323/// coproc_option : '{' imm0_255 '}'
3324ARMAsmParser::OperandMatchResultTy
3325ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3326  MCAsmParser &Parser = getParser();
3327  SMLoc S = Parser.getTok().getLoc();
3328
3329  // If this isn't a '{', this isn't a coprocessor immediate operand.
3330  if (Parser.getTok().isNot(AsmToken::LCurly))
3331    return MatchOperand_NoMatch;
3332  Parser.Lex(); // Eat the '{'
3333
3334  const MCExpr *Expr;
3335  SMLoc Loc = Parser.getTok().getLoc();
3336  if (getParser().parseExpression(Expr)) {
3337    Error(Loc, "illegal expression");
3338    return MatchOperand_ParseFail;
3339  }
3340  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3341  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3342    Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3343    return MatchOperand_ParseFail;
3344  }
3345  int Val = CE->getValue();
3346
3347  // Check for and consume the closing '}'
3348  if (Parser.getTok().isNot(AsmToken::RCurly))
3349    return MatchOperand_ParseFail;
3350  SMLoc E = Parser.getTok().getEndLoc();
3351  Parser.Lex(); // Eat the '}'
3352
3353  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3354  return MatchOperand_Success;
3355}
3356
3357// For register list parsing, we need to map from raw GPR register numbering
3358// to the enumeration values. The enumeration values aren't sorted by
3359// register number due to our using "sp", "lr" and "pc" as canonical names.
3360static unsigned getNextRegister(unsigned Reg) {
3361  // If this is a GPR, we need to do it manually, otherwise we can rely
3362  // on the sort ordering of the enumeration since the other reg-classes
3363  // are sane.
3364  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3365    return Reg + 1;
3366  switch(Reg) {
3367  default: llvm_unreachable("Invalid GPR number!");
3368  case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
3369  case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
3370  case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
3371  case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
3372  case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
3373  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3374  case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
3375  case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
3376  }
3377}
3378
3379// Return the low-subreg of a given Q register.
3380static unsigned getDRegFromQReg(unsigned QReg) {
3381  switch (QReg) {
3382  default: llvm_unreachable("expected a Q register!");
3383  case ARM::Q0:  return ARM::D0;
3384  case ARM::Q1:  return ARM::D2;
3385  case ARM::Q2:  return ARM::D4;
3386  case ARM::Q3:  return ARM::D6;
3387  case ARM::Q4:  return ARM::D8;
3388  case ARM::Q5:  return ARM::D10;
3389  case ARM::Q6:  return ARM::D12;
3390  case ARM::Q7:  return ARM::D14;
3391  case ARM::Q8:  return ARM::D16;
3392  case ARM::Q9:  return ARM::D18;
3393  case ARM::Q10: return ARM::D20;
3394  case ARM::Q11: return ARM::D22;
3395  case ARM::Q12: return ARM::D24;
3396  case ARM::Q13: return ARM::D26;
3397  case ARM::Q14: return ARM::D28;
3398  case ARM::Q15: return ARM::D30;
3399  }
3400}
3401
3402/// Parse a register list.
3403bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3404  MCAsmParser &Parser = getParser();
3405  assert(Parser.getTok().is(AsmToken::LCurly) &&
3406         "Token is not a Left Curly Brace");
3407  SMLoc S = Parser.getTok().getLoc();
3408  Parser.Lex(); // Eat '{' token.
3409  SMLoc RegLoc = Parser.getTok().getLoc();
3410
3411  // Check the first register in the list to see what register class
3412  // this is a list of.
3413  int Reg = tryParseRegister();
3414  if (Reg == -1)
3415    return Error(RegLoc, "register expected");
3416
3417  // The reglist instructions have at most 16 registers, so reserve
3418  // space for that many.
3419  int EReg = 0;
3420  SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3421
3422  // Allow Q regs and just interpret them as the two D sub-registers.
3423  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3424    Reg = getDRegFromQReg(Reg);
3425    EReg = MRI->getEncodingValue(Reg);
3426    Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3427    ++Reg;
3428  }
3429  const MCRegisterClass *RC;
3430  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3431    RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3432  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3433    RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3434  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3435    RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3436  else
3437    return Error(RegLoc, "invalid register in register list");
3438
3439  // Store the register.
3440  EReg = MRI->getEncodingValue(Reg);
3441  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3442
3443  // This starts immediately after the first register token in the list,
3444  // so we can see either a comma or a minus (range separator) as a legal
3445  // next token.
3446  while (Parser.getTok().is(AsmToken::Comma) ||
3447         Parser.getTok().is(AsmToken::Minus)) {
3448    if (Parser.getTok().is(AsmToken::Minus)) {
3449      Parser.Lex(); // Eat the minus.
3450      SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3451      int EndReg = tryParseRegister();
3452      if (EndReg == -1)
3453        return Error(AfterMinusLoc, "register expected");
3454      // Allow Q regs and just interpret them as the two D sub-registers.
3455      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3456        EndReg = getDRegFromQReg(EndReg) + 1;
3457      // If the register is the same as the start reg, there's nothing
3458      // more to do.
3459      if (Reg == EndReg)
3460        continue;
3461      // The register must be in the same register class as the first.
3462      if (!RC->contains(EndReg))
3463        return Error(AfterMinusLoc, "invalid register in register list");
3464      // Ranges must go from low to high.
3465      if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3466        return Error(AfterMinusLoc, "bad range in register list");
3467
3468      // Add all the registers in the range to the register list.
3469      while (Reg != EndReg) {
3470        Reg = getNextRegister(Reg);
3471        EReg = MRI->getEncodingValue(Reg);
3472        Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3473      }
3474      continue;
3475    }
3476    Parser.Lex(); // Eat the comma.
3477    RegLoc = Parser.getTok().getLoc();
3478    int OldReg = Reg;
3479    const AsmToken RegTok = Parser.getTok();
3480    Reg = tryParseRegister();
3481    if (Reg == -1)
3482      return Error(RegLoc, "register expected");
3483    // Allow Q regs and just interpret them as the two D sub-registers.
3484    bool isQReg = false;
3485    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3486      Reg = getDRegFromQReg(Reg);
3487      isQReg = true;
3488    }
3489    // The register must be in the same register class as the first.
3490    if (!RC->contains(Reg))
3491      return Error(RegLoc, "invalid register in register list");
3492    // List must be monotonically increasing.
3493    if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3494      if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3495        Warning(RegLoc, "register list not in ascending order");
3496      else
3497        return Error(RegLoc, "register list not in ascending order");
3498    }
3499    if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3500      Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3501              ") in register list");
3502      continue;
3503    }
3504    // VFP register lists must also be contiguous.
3505    if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3506        Reg != OldReg + 1)
3507      return Error(RegLoc, "non-contiguous register range");
3508    EReg = MRI->getEncodingValue(Reg);
3509    Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3510    if (isQReg) {
3511      EReg = MRI->getEncodingValue(++Reg);
3512      Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3513    }
3514  }
3515
3516  if (Parser.getTok().isNot(AsmToken::RCurly))
3517    return Error(Parser.getTok().getLoc(), "'}' expected");
3518  SMLoc E = Parser.getTok().getEndLoc();
3519  Parser.Lex(); // Eat '}' token.
3520
3521  // Push the register list operand.
3522  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3523
3524  // The ARM system instruction variants for LDM/STM have a '^' token here.
3525  if (Parser.getTok().is(AsmToken::Caret)) {
3526    Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3527    Parser.Lex(); // Eat '^' token.
3528  }
3529
3530  return false;
3531}
3532
3533// Helper function to parse the lane index for vector lists.
3534ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3535parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3536  MCAsmParser &Parser = getParser();
3537  Index = 0; // Always return a defined index value.
3538  if (Parser.getTok().is(AsmToken::LBrac)) {
3539    Parser.Lex(); // Eat the '['.
3540    if (Parser.getTok().is(AsmToken::RBrac)) {
3541      // "Dn[]" is the 'all lanes' syntax.
3542      LaneKind = AllLanes;
3543      EndLoc = Parser.getTok().getEndLoc();
3544      Parser.Lex(); // Eat the ']'.
3545      return MatchOperand_Success;
3546    }
3547
3548    // There's an optional '#' token here. Normally there wouldn't be, but
3549    // inline assemble puts one in, and it's friendly to accept that.
3550    if (Parser.getTok().is(AsmToken::Hash))
3551      Parser.Lex(); // Eat '#' or '$'.
3552
3553    const MCExpr *LaneIndex;
3554    SMLoc Loc = Parser.getTok().getLoc();
3555    if (getParser().parseExpression(LaneIndex)) {
3556      Error(Loc, "illegal expression");
3557      return MatchOperand_ParseFail;
3558    }
3559    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3560    if (!CE) {
3561      Error(Loc, "lane index must be empty or an integer");
3562      return MatchOperand_ParseFail;
3563    }
3564    if (Parser.getTok().isNot(AsmToken::RBrac)) {
3565      Error(Parser.getTok().getLoc(), "']' expected");
3566      return MatchOperand_ParseFail;
3567    }
3568    EndLoc = Parser.getTok().getEndLoc();
3569    Parser.Lex(); // Eat the ']'.
3570    int64_t Val = CE->getValue();
3571
3572    // FIXME: Make this range check context sensitive for .8, .16, .32.
3573    if (Val < 0 || Val > 7) {
3574      Error(Parser.getTok().getLoc(), "lane index out of range");
3575      return MatchOperand_ParseFail;
3576    }
3577    Index = Val;
3578    LaneKind = IndexedLane;
3579    return MatchOperand_Success;
3580  }
3581  LaneKind = NoLanes;
3582  return MatchOperand_Success;
3583}
3584
3585// parse a vector register list
3586ARMAsmParser::OperandMatchResultTy
3587ARMAsmParser::parseVectorList(OperandVector &Operands) {
3588  MCAsmParser &Parser = getParser();
3589  VectorLaneTy LaneKind;
3590  unsigned LaneIndex;
3591  SMLoc S = Parser.getTok().getLoc();
3592  // As an extension (to match gas), support a plain D register or Q register
3593  // (without encosing curly braces) as a single or double entry list,
3594  // respectively.
3595  if (Parser.getTok().is(AsmToken::Identifier)) {
3596    SMLoc E = Parser.getTok().getEndLoc();
3597    int Reg = tryParseRegister();
3598    if (Reg == -1)
3599      return MatchOperand_NoMatch;
3600    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3601      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3602      if (Res != MatchOperand_Success)
3603        return Res;
3604      switch (LaneKind) {
3605      case NoLanes:
3606        Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3607        break;
3608      case AllLanes:
3609        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3610                                                                S, E));
3611        break;
3612      case IndexedLane:
3613        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3614                                                               LaneIndex,
3615                                                               false, S, E));
3616        break;
3617      }
3618      return MatchOperand_Success;
3619    }
3620    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3621      Reg = getDRegFromQReg(Reg);
3622      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3623      if (Res != MatchOperand_Success)
3624        return Res;
3625      switch (LaneKind) {
3626      case NoLanes:
3627        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3628                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3629        Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3630        break;
3631      case AllLanes:
3632        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3633                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3634        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3635                                                                S, E));
3636        break;
3637      case IndexedLane:
3638        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3639                                                               LaneIndex,
3640                                                               false, S, E));
3641        break;
3642      }
3643      return MatchOperand_Success;
3644    }
3645    Error(S, "vector register expected");
3646    return MatchOperand_ParseFail;
3647  }
3648
3649  if (Parser.getTok().isNot(AsmToken::LCurly))
3650    return MatchOperand_NoMatch;
3651
3652  Parser.Lex(); // Eat '{' token.
3653  SMLoc RegLoc = Parser.getTok().getLoc();
3654
3655  int Reg = tryParseRegister();
3656  if (Reg == -1) {
3657    Error(RegLoc, "register expected");
3658    return MatchOperand_ParseFail;
3659  }
3660  unsigned Count = 1;
3661  int Spacing = 0;
3662  unsigned FirstReg = Reg;
3663  // The list is of D registers, but we also allow Q regs and just interpret
3664  // them as the two D sub-registers.
3665  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3666    FirstReg = Reg = getDRegFromQReg(Reg);
3667    Spacing = 1; // double-spacing requires explicit D registers, otherwise
3668                 // it's ambiguous with four-register single spaced.
3669    ++Reg;
3670    ++Count;
3671  }
3672
3673  SMLoc E;
3674  if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3675    return MatchOperand_ParseFail;
3676
3677  while (Parser.getTok().is(AsmToken::Comma) ||
3678         Parser.getTok().is(AsmToken::Minus)) {
3679    if (Parser.getTok().is(AsmToken::Minus)) {
3680      if (!Spacing)
3681        Spacing = 1; // Register range implies a single spaced list.
3682      else if (Spacing == 2) {
3683        Error(Parser.getTok().getLoc(),
3684              "sequential registers in double spaced list");
3685        return MatchOperand_ParseFail;
3686      }
3687      Parser.Lex(); // Eat the minus.
3688      SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3689      int EndReg = tryParseRegister();
3690      if (EndReg == -1) {
3691        Error(AfterMinusLoc, "register expected");
3692        return MatchOperand_ParseFail;
3693      }
3694      // Allow Q regs and just interpret them as the two D sub-registers.
3695      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3696        EndReg = getDRegFromQReg(EndReg) + 1;
3697      // If the register is the same as the start reg, there's nothing
3698      // more to do.
3699      if (Reg == EndReg)
3700        continue;
3701      // The register must be in the same register class as the first.
3702      if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3703        Error(AfterMinusLoc, "invalid register in register list");
3704        return MatchOperand_ParseFail;
3705      }
3706      // Ranges must go from low to high.
3707      if (Reg > EndReg) {
3708        Error(AfterMinusLoc, "bad range in register list");
3709        return MatchOperand_ParseFail;
3710      }
3711      // Parse the lane specifier if present.
3712      VectorLaneTy NextLaneKind;
3713      unsigned NextLaneIndex;
3714      if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3715          MatchOperand_Success)
3716        return MatchOperand_ParseFail;
3717      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3718        Error(AfterMinusLoc, "mismatched lane index in register list");
3719        return MatchOperand_ParseFail;
3720      }
3721
3722      // Add all the registers in the range to the register list.
3723      Count += EndReg - Reg;
3724      Reg = EndReg;
3725      continue;
3726    }
3727    Parser.Lex(); // Eat the comma.
3728    RegLoc = Parser.getTok().getLoc();
3729    int OldReg = Reg;
3730    Reg = tryParseRegister();
3731    if (Reg == -1) {
3732      Error(RegLoc, "register expected");
3733      return MatchOperand_ParseFail;
3734    }
3735    // vector register lists must be contiguous.
3736    // It's OK to use the enumeration values directly here rather, as the
3737    // VFP register classes have the enum sorted properly.
3738    //
3739    // The list is of D registers, but we also allow Q regs and just interpret
3740    // them as the two D sub-registers.
3741    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3742      if (!Spacing)
3743        Spacing = 1; // Register range implies a single spaced list.
3744      else if (Spacing == 2) {
3745        Error(RegLoc,
3746              "invalid register in double-spaced list (must be 'D' register')");
3747        return MatchOperand_ParseFail;
3748      }
3749      Reg = getDRegFromQReg(Reg);
3750      if (Reg != OldReg + 1) {
3751        Error(RegLoc, "non-contiguous register range");
3752        return MatchOperand_ParseFail;
3753      }
3754      ++Reg;
3755      Count += 2;
3756      // Parse the lane specifier if present.
3757      VectorLaneTy NextLaneKind;
3758      unsigned NextLaneIndex;
3759      SMLoc LaneLoc = Parser.getTok().getLoc();
3760      if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3761          MatchOperand_Success)
3762        return MatchOperand_ParseFail;
3763      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3764        Error(LaneLoc, "mismatched lane index in register list");
3765        return MatchOperand_ParseFail;
3766      }
3767      continue;
3768    }
3769    // Normal D register.
3770    // Figure out the register spacing (single or double) of the list if
3771    // we don't know it already.
3772    if (!Spacing)
3773      Spacing = 1 + (Reg == OldReg + 2);
3774
3775    // Just check that it's contiguous and keep going.
3776    if (Reg != OldReg + Spacing) {
3777      Error(RegLoc, "non-contiguous register range");
3778      return MatchOperand_ParseFail;
3779    }
3780    ++Count;
3781    // Parse the lane specifier if present.
3782    VectorLaneTy NextLaneKind;
3783    unsigned NextLaneIndex;
3784    SMLoc EndLoc = Parser.getTok().getLoc();
3785    if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3786      return MatchOperand_ParseFail;
3787    if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3788      Error(EndLoc, "mismatched lane index in register list");
3789      return MatchOperand_ParseFail;
3790    }
3791  }
3792
3793  if (Parser.getTok().isNot(AsmToken::RCurly)) {
3794    Error(Parser.getTok().getLoc(), "'}' expected");
3795    return MatchOperand_ParseFail;
3796  }
3797  E = Parser.getTok().getEndLoc();
3798  Parser.Lex(); // Eat '}' token.
3799
3800  switch (LaneKind) {
3801  case NoLanes:
3802    // Two-register operands have been converted to the
3803    // composite register classes.
3804    if (Count == 2) {
3805      const MCRegisterClass *RC = (Spacing == 1) ?
3806        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3807        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3808      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3809    }
3810
3811    Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3812                                                    (Spacing == 2), S, E));
3813    break;
3814  case AllLanes:
3815    // Two-register operands have been converted to the
3816    // composite register classes.
3817    if (Count == 2) {
3818      const MCRegisterClass *RC = (Spacing == 1) ?
3819        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3820        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3821      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3822    }
3823    Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3824                                                            (Spacing == 2),
3825                                                            S, E));
3826    break;
3827  case IndexedLane:
3828    Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3829                                                           LaneIndex,
3830                                                           (Spacing == 2),
3831                                                           S, E));
3832    break;
3833  }
3834  return MatchOperand_Success;
3835}
3836
3837/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3838ARMAsmParser::OperandMatchResultTy
3839ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
3840  MCAsmParser &Parser = getParser();
3841  SMLoc S = Parser.getTok().getLoc();
3842  const AsmToken &Tok = Parser.getTok();
3843  unsigned Opt;
3844
3845  if (Tok.is(AsmToken::Identifier)) {
3846    StringRef OptStr = Tok.getString();
3847
3848    Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3849      .Case("sy",    ARM_MB::SY)
3850      .Case("st",    ARM_MB::ST)
3851      .Case("ld",    ARM_MB::LD)
3852      .Case("sh",    ARM_MB::ISH)
3853      .Case("ish",   ARM_MB::ISH)
3854      .Case("shst",  ARM_MB::ISHST)
3855      .Case("ishst", ARM_MB::ISHST)
3856      .Case("ishld", ARM_MB::ISHLD)
3857      .Case("nsh",   ARM_MB::NSH)
3858      .Case("un",    ARM_MB::NSH)
3859      .Case("nshst", ARM_MB::NSHST)
3860      .Case("nshld", ARM_MB::NSHLD)
3861      .Case("unst",  ARM_MB::NSHST)
3862      .Case("osh",   ARM_MB::OSH)
3863      .Case("oshst", ARM_MB::OSHST)
3864      .Case("oshld", ARM_MB::OSHLD)
3865      .Default(~0U);
3866
3867    // ishld, oshld, nshld and ld are only available from ARMv8.
3868    if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3869                        Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3870      Opt = ~0U;
3871
3872    if (Opt == ~0U)
3873      return MatchOperand_NoMatch;
3874
3875    Parser.Lex(); // Eat identifier token.
3876  } else if (Tok.is(AsmToken::Hash) ||
3877             Tok.is(AsmToken::Dollar) ||
3878             Tok.is(AsmToken::Integer)) {
3879    if (Parser.getTok().isNot(AsmToken::Integer))
3880      Parser.Lex(); // Eat '#' or '$'.
3881    SMLoc Loc = Parser.getTok().getLoc();
3882
3883    const MCExpr *MemBarrierID;
3884    if (getParser().parseExpression(MemBarrierID)) {
3885      Error(Loc, "illegal expression");
3886      return MatchOperand_ParseFail;
3887    }
3888
3889    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3890    if (!CE) {
3891      Error(Loc, "constant expression expected");
3892      return MatchOperand_ParseFail;
3893    }
3894
3895    int Val = CE->getValue();
3896    if (Val & ~0xf) {
3897      Error(Loc, "immediate value out of range");
3898      return MatchOperand_ParseFail;
3899    }
3900
3901    Opt = ARM_MB::RESERVED_0 + Val;
3902  } else
3903    return MatchOperand_ParseFail;
3904
3905  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3906  return MatchOperand_Success;
3907}
3908
3909/// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3910ARMAsmParser::OperandMatchResultTy
3911ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
3912  MCAsmParser &Parser = getParser();
3913  SMLoc S = Parser.getTok().getLoc();
3914  const AsmToken &Tok = Parser.getTok();
3915  unsigned Opt;
3916
3917  if (Tok.is(AsmToken::Identifier)) {
3918    StringRef OptStr = Tok.getString();
3919
3920    if (OptStr.equals_lower("sy"))
3921      Opt = ARM_ISB::SY;
3922    else
3923      return MatchOperand_NoMatch;
3924
3925    Parser.Lex(); // Eat identifier token.
3926  } else if (Tok.is(AsmToken::Hash) ||
3927             Tok.is(AsmToken::Dollar) ||
3928             Tok.is(AsmToken::Integer)) {
3929    if (Parser.getTok().isNot(AsmToken::Integer))
3930      Parser.Lex(); // Eat '#' or '$'.
3931    SMLoc Loc = Parser.getTok().getLoc();
3932
3933    const MCExpr *ISBarrierID;
3934    if (getParser().parseExpression(ISBarrierID)) {
3935      Error(Loc, "illegal expression");
3936      return MatchOperand_ParseFail;
3937    }
3938
3939    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3940    if (!CE) {
3941      Error(Loc, "constant expression expected");
3942      return MatchOperand_ParseFail;
3943    }
3944
3945    int Val = CE->getValue();
3946    if (Val & ~0xf) {
3947      Error(Loc, "immediate value out of range");
3948      return MatchOperand_ParseFail;
3949    }
3950
3951    Opt = ARM_ISB::RESERVED_0 + Val;
3952  } else
3953    return MatchOperand_ParseFail;
3954
3955  Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3956          (ARM_ISB::InstSyncBOpt)Opt, S));
3957  return MatchOperand_Success;
3958}
3959
3960
3961/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3962ARMAsmParser::OperandMatchResultTy
3963ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
3964  MCAsmParser &Parser = getParser();
3965  SMLoc S = Parser.getTok().getLoc();
3966  const AsmToken &Tok = Parser.getTok();
3967  if (!Tok.is(AsmToken::Identifier))
3968    return MatchOperand_NoMatch;
3969  StringRef IFlagsStr = Tok.getString();
3970
3971  // An iflags string of "none" is interpreted to mean that none of the AIF
3972  // bits are set.  Not a terribly useful instruction, but a valid encoding.
3973  unsigned IFlags = 0;
3974  if (IFlagsStr != "none") {
3975        for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3976      unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3977        .Case("a", ARM_PROC::A)
3978        .Case("i", ARM_PROC::I)
3979        .Case("f", ARM_PROC::F)
3980        .Default(~0U);
3981
3982      // If some specific iflag is already set, it means that some letter is
3983      // present more than once, this is not acceptable.
3984      if (Flag == ~0U || (IFlags & Flag))
3985        return MatchOperand_NoMatch;
3986
3987      IFlags |= Flag;
3988    }
3989  }
3990
3991  Parser.Lex(); // Eat identifier token.
3992  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3993  return MatchOperand_Success;
3994}
3995
3996/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3997ARMAsmParser::OperandMatchResultTy
3998ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
3999  MCAsmParser &Parser = getParser();
4000  SMLoc S = Parser.getTok().getLoc();
4001  const AsmToken &Tok = Parser.getTok();
4002  if (!Tok.is(AsmToken::Identifier))
4003    return MatchOperand_NoMatch;
4004  StringRef Mask = Tok.getString();
4005
4006  if (isMClass()) {
4007    // See ARMv6-M 10.1.1
4008    std::string Name = Mask.lower();
4009    unsigned FlagsVal = StringSwitch<unsigned>(Name)
4010      // Note: in the documentation:
4011      //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
4012      //  for MSR APSR_nzcvq.
4013      // but we do make it an alias here.  This is so to get the "mask encoding"
4014      // bits correct on MSR APSR writes.
4015      //
4016      // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
4017      // should really only be allowed when writing a special register.  Note
4018      // they get dropped in the MRS instruction reading a special register as
4019      // the SYSm field is only 8 bits.
4020      .Case("apsr", 0x800)
4021      .Case("apsr_nzcvq", 0x800)
4022      .Case("apsr_g", 0x400)
4023      .Case("apsr_nzcvqg", 0xc00)
4024      .Case("iapsr", 0x801)
4025      .Case("iapsr_nzcvq", 0x801)
4026      .Case("iapsr_g", 0x401)
4027      .Case("iapsr_nzcvqg", 0xc01)
4028      .Case("eapsr", 0x802)
4029      .Case("eapsr_nzcvq", 0x802)
4030      .Case("eapsr_g", 0x402)
4031      .Case("eapsr_nzcvqg", 0xc02)
4032      .Case("xpsr", 0x803)
4033      .Case("xpsr_nzcvq", 0x803)
4034      .Case("xpsr_g", 0x403)
4035      .Case("xpsr_nzcvqg", 0xc03)
4036      .Case("ipsr", 0x805)
4037      .Case("epsr", 0x806)
4038      .Case("iepsr", 0x807)
4039      .Case("msp", 0x808)
4040      .Case("psp", 0x809)
4041      .Case("primask", 0x810)
4042      .Case("basepri", 0x811)
4043      .Case("basepri_max", 0x812)
4044      .Case("faultmask", 0x813)
4045      .Case("control", 0x814)
4046      .Default(~0U);
4047
4048    if (FlagsVal == ~0U)
4049      return MatchOperand_NoMatch;
4050
4051    if (!hasThumb2DSP() && (FlagsVal & 0x400))
4052      // The _g and _nzcvqg versions are only valid if the DSP extension is
4053      // available.
4054      return MatchOperand_NoMatch;
4055
4056    if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
4057      // basepri, basepri_max and faultmask only valid for V7m.
4058      return MatchOperand_NoMatch;
4059
4060    Parser.Lex(); // Eat identifier token.
4061    Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4062    return MatchOperand_Success;
4063  }
4064
4065  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
4066  size_t Start = 0, Next = Mask.find('_');
4067  StringRef Flags = "";
4068  std::string SpecReg = Mask.slice(Start, Next).lower();
4069  if (Next != StringRef::npos)
4070    Flags = Mask.slice(Next+1, Mask.size());
4071
4072  // FlagsVal contains the complete mask:
4073  // 3-0: Mask
4074  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4075  unsigned FlagsVal = 0;
4076
4077  if (SpecReg == "apsr") {
4078    FlagsVal = StringSwitch<unsigned>(Flags)
4079    .Case("nzcvq",  0x8) // same as CPSR_f
4080    .Case("g",      0x4) // same as CPSR_s
4081    .Case("nzcvqg", 0xc) // same as CPSR_fs
4082    .Default(~0U);
4083
4084    if (FlagsVal == ~0U) {
4085      if (!Flags.empty())
4086        return MatchOperand_NoMatch;
4087      else
4088        FlagsVal = 8; // No flag
4089    }
4090  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4091    // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4092    if (Flags == "all" || Flags == "")
4093      Flags = "fc";
4094    for (int i = 0, e = Flags.size(); i != e; ++i) {
4095      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4096      .Case("c", 1)
4097      .Case("x", 2)
4098      .Case("s", 4)
4099      .Case("f", 8)
4100      .Default(~0U);
4101
4102      // If some specific flag is already set, it means that some letter is
4103      // present more than once, this is not acceptable.
4104      if (FlagsVal == ~0U || (FlagsVal & Flag))
4105        return MatchOperand_NoMatch;
4106      FlagsVal |= Flag;
4107    }
4108  } else // No match for special register.
4109    return MatchOperand_NoMatch;
4110
4111  // Special register without flags is NOT equivalent to "fc" flags.
4112  // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
4113  // two lines would enable gas compatibility at the expense of breaking
4114  // round-tripping.
4115  //
4116  // if (!FlagsVal)
4117  //  FlagsVal = 0x9;
4118
4119  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4120  if (SpecReg == "spsr")
4121    FlagsVal |= 16;
4122
4123  Parser.Lex(); // Eat identifier token.
4124  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4125  return MatchOperand_Success;
4126}
4127
4128/// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
4129/// use in the MRS/MSR instructions added to support virtualization.
4130ARMAsmParser::OperandMatchResultTy
4131ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
4132  MCAsmParser &Parser = getParser();
4133  SMLoc S = Parser.getTok().getLoc();
4134  const AsmToken &Tok = Parser.getTok();
4135  if (!Tok.is(AsmToken::Identifier))
4136    return MatchOperand_NoMatch;
4137  StringRef RegName = Tok.getString();
4138
4139  // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
4140  // and bit 5 is R.
4141  unsigned Encoding = StringSwitch<unsigned>(RegName.lower())
4142                          .Case("r8_usr", 0x00)
4143                          .Case("r9_usr", 0x01)
4144                          .Case("r10_usr", 0x02)
4145                          .Case("r11_usr", 0x03)
4146                          .Case("r12_usr", 0x04)
4147                          .Case("sp_usr", 0x05)
4148                          .Case("lr_usr", 0x06)
4149                          .Case("r8_fiq", 0x08)
4150                          .Case("r9_fiq", 0x09)
4151                          .Case("r10_fiq", 0x0a)
4152                          .Case("r11_fiq", 0x0b)
4153                          .Case("r12_fiq", 0x0c)
4154                          .Case("sp_fiq", 0x0d)
4155                          .Case("lr_fiq", 0x0e)
4156                          .Case("lr_irq", 0x10)
4157                          .Case("sp_irq", 0x11)
4158                          .Case("lr_svc", 0x12)
4159                          .Case("sp_svc", 0x13)
4160                          .Case("lr_abt", 0x14)
4161                          .Case("sp_abt", 0x15)
4162                          .Case("lr_und", 0x16)
4163                          .Case("sp_und", 0x17)
4164                          .Case("lr_mon", 0x1c)
4165                          .Case("sp_mon", 0x1d)
4166                          .Case("elr_hyp", 0x1e)
4167                          .Case("sp_hyp", 0x1f)
4168                          .Case("spsr_fiq", 0x2e)
4169                          .Case("spsr_irq", 0x30)
4170                          .Case("spsr_svc", 0x32)
4171                          .Case("spsr_abt", 0x34)
4172                          .Case("spsr_und", 0x36)
4173                          .Case("spsr_mon", 0x3c)
4174                          .Case("spsr_hyp", 0x3e)
4175                          .Default(~0U);
4176
4177  if (Encoding == ~0U)
4178    return MatchOperand_NoMatch;
4179
4180  Parser.Lex(); // Eat identifier token.
4181  Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
4182  return MatchOperand_Success;
4183}
4184
4185ARMAsmParser::OperandMatchResultTy
4186ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
4187                          int High) {
4188  MCAsmParser &Parser = getParser();
4189  const AsmToken &Tok = Parser.getTok();
4190  if (Tok.isNot(AsmToken::Identifier)) {
4191    Error(Parser.getTok().getLoc(), Op + " operand expected.");
4192    return MatchOperand_ParseFail;
4193  }
4194  StringRef ShiftName = Tok.getString();
4195  std::string LowerOp = Op.lower();
4196  std::string UpperOp = Op.upper();
4197  if (ShiftName != LowerOp && ShiftName != UpperOp) {
4198    Error(Parser.getTok().getLoc(), Op + " operand expected.");
4199    return MatchOperand_ParseFail;
4200  }
4201  Parser.Lex(); // Eat shift type token.
4202
4203  // There must be a '#' and a shift amount.
4204  if (Parser.getTok().isNot(AsmToken::Hash) &&
4205      Parser.getTok().isNot(AsmToken::Dollar)) {
4206    Error(Parser.getTok().getLoc(), "'#' expected");
4207    return MatchOperand_ParseFail;
4208  }
4209  Parser.Lex(); // Eat hash token.
4210
4211  const MCExpr *ShiftAmount;
4212  SMLoc Loc = Parser.getTok().getLoc();
4213  SMLoc EndLoc;
4214  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4215    Error(Loc, "illegal expression");
4216    return MatchOperand_ParseFail;
4217  }
4218  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4219  if (!CE) {
4220    Error(Loc, "constant expression expected");
4221    return MatchOperand_ParseFail;
4222  }
4223  int Val = CE->getValue();
4224  if (Val < Low || Val > High) {
4225    Error(Loc, "immediate value out of range");
4226    return MatchOperand_ParseFail;
4227  }
4228
4229  Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4230
4231  return MatchOperand_Success;
4232}
4233
4234ARMAsmParser::OperandMatchResultTy
4235ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4236  MCAsmParser &Parser = getParser();
4237  const AsmToken &Tok = Parser.getTok();
4238  SMLoc S = Tok.getLoc();
4239  if (Tok.isNot(AsmToken::Identifier)) {
4240    Error(S, "'be' or 'le' operand expected");
4241    return MatchOperand_ParseFail;
4242  }
4243  int Val = StringSwitch<int>(Tok.getString().lower())
4244    .Case("be", 1)
4245    .Case("le", 0)
4246    .Default(-1);
4247  Parser.Lex(); // Eat the token.
4248
4249  if (Val == -1) {
4250    Error(S, "'be' or 'le' operand expected");
4251    return MatchOperand_ParseFail;
4252  }
4253  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
4254                                                                  getContext()),
4255                                           S, Tok.getEndLoc()));
4256  return MatchOperand_Success;
4257}
4258
4259/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4260/// instructions. Legal values are:
4261///     lsl #n  'n' in [0,31]
4262///     asr #n  'n' in [1,32]
4263///             n == 32 encoded as n == 0.
4264ARMAsmParser::OperandMatchResultTy
4265ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4266  MCAsmParser &Parser = getParser();
4267  const AsmToken &Tok = Parser.getTok();
4268  SMLoc S = Tok.getLoc();
4269  if (Tok.isNot(AsmToken::Identifier)) {
4270    Error(S, "shift operator 'asr' or 'lsl' expected");
4271    return MatchOperand_ParseFail;
4272  }
4273  StringRef ShiftName = Tok.getString();
4274  bool isASR;
4275  if (ShiftName == "lsl" || ShiftName == "LSL")
4276    isASR = false;
4277  else if (ShiftName == "asr" || ShiftName == "ASR")
4278    isASR = true;
4279  else {
4280    Error(S, "shift operator 'asr' or 'lsl' expected");
4281    return MatchOperand_ParseFail;
4282  }
4283  Parser.Lex(); // Eat the operator.
4284
4285  // A '#' and a shift amount.
4286  if (Parser.getTok().isNot(AsmToken::Hash) &&
4287      Parser.getTok().isNot(AsmToken::Dollar)) {
4288    Error(Parser.getTok().getLoc(), "'#' expected");
4289    return MatchOperand_ParseFail;
4290  }
4291  Parser.Lex(); // Eat hash token.
4292  SMLoc ExLoc = Parser.getTok().getLoc();
4293
4294  const MCExpr *ShiftAmount;
4295  SMLoc EndLoc;
4296  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4297    Error(ExLoc, "malformed shift expression");
4298    return MatchOperand_ParseFail;
4299  }
4300  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4301  if (!CE) {
4302    Error(ExLoc, "shift amount must be an immediate");
4303    return MatchOperand_ParseFail;
4304  }
4305
4306  int64_t Val = CE->getValue();
4307  if (isASR) {
4308    // Shift amount must be in [1,32]
4309    if (Val < 1 || Val > 32) {
4310      Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4311      return MatchOperand_ParseFail;
4312    }
4313    // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4314    if (isThumb() && Val == 32) {
4315      Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4316      return MatchOperand_ParseFail;
4317    }
4318    if (Val == 32) Val = 0;
4319  } else {
4320    // Shift amount must be in [1,32]
4321    if (Val < 0 || Val > 31) {
4322      Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4323      return MatchOperand_ParseFail;
4324    }
4325  }
4326
4327  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4328
4329  return MatchOperand_Success;
4330}
4331
4332/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4333/// of instructions. Legal values are:
4334///     ror #n  'n' in {0, 8, 16, 24}
4335ARMAsmParser::OperandMatchResultTy
4336ARMAsmParser::parseRotImm(OperandVector &Operands) {
4337  MCAsmParser &Parser = getParser();
4338  const AsmToken &Tok = Parser.getTok();
4339  SMLoc S = Tok.getLoc();
4340  if (Tok.isNot(AsmToken::Identifier))
4341    return MatchOperand_NoMatch;
4342  StringRef ShiftName = Tok.getString();
4343  if (ShiftName != "ror" && ShiftName != "ROR")
4344    return MatchOperand_NoMatch;
4345  Parser.Lex(); // Eat the operator.
4346
4347  // A '#' and a rotate amount.
4348  if (Parser.getTok().isNot(AsmToken::Hash) &&
4349      Parser.getTok().isNot(AsmToken::Dollar)) {
4350    Error(Parser.getTok().getLoc(), "'#' expected");
4351    return MatchOperand_ParseFail;
4352  }
4353  Parser.Lex(); // Eat hash token.
4354  SMLoc ExLoc = Parser.getTok().getLoc();
4355
4356  const MCExpr *ShiftAmount;
4357  SMLoc EndLoc;
4358  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4359    Error(ExLoc, "malformed rotate expression");
4360    return MatchOperand_ParseFail;
4361  }
4362  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4363  if (!CE) {
4364    Error(ExLoc, "rotate amount must be an immediate");
4365    return MatchOperand_ParseFail;
4366  }
4367
4368  int64_t Val = CE->getValue();
4369  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4370  // normally, zero is represented in asm by omitting the rotate operand
4371  // entirely.
4372  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4373    Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4374    return MatchOperand_ParseFail;
4375  }
4376
4377  Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4378
4379  return MatchOperand_Success;
4380}
4381
4382ARMAsmParser::OperandMatchResultTy
4383ARMAsmParser::parseModImm(OperandVector &Operands) {
4384  MCAsmParser &Parser = getParser();
4385  MCAsmLexer &Lexer = getLexer();
4386  int64_t Imm1, Imm2;
4387
4388  SMLoc S = Parser.getTok().getLoc();
4389
4390  // 1) A mod_imm operand can appear in the place of a register name:
4391  //   add r0, #mod_imm
4392  //   add r0, r0, #mod_imm
4393  // to correctly handle the latter, we bail out as soon as we see an
4394  // identifier.
4395  //
4396  // 2) Similarly, we do not want to parse into complex operands:
4397  //   mov r0, #mod_imm
4398  //   mov r0, :lower16:(_foo)
4399  if (Parser.getTok().is(AsmToken::Identifier) ||
4400      Parser.getTok().is(AsmToken::Colon))
4401    return MatchOperand_NoMatch;
4402
4403  // Hash (dollar) is optional as per the ARMARM
4404  if (Parser.getTok().is(AsmToken::Hash) ||
4405      Parser.getTok().is(AsmToken::Dollar)) {
4406    // Avoid parsing into complex operands (#:)
4407    if (Lexer.peekTok().is(AsmToken::Colon))
4408      return MatchOperand_NoMatch;
4409
4410    // Eat the hash (dollar)
4411    Parser.Lex();
4412  }
4413
4414  SMLoc Sx1, Ex1;
4415  Sx1 = Parser.getTok().getLoc();
4416  const MCExpr *Imm1Exp;
4417  if (getParser().parseExpression(Imm1Exp, Ex1)) {
4418    Error(Sx1, "malformed expression");
4419    return MatchOperand_ParseFail;
4420  }
4421
4422  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
4423
4424  if (CE) {
4425    // Immediate must fit within 32-bits
4426    Imm1 = CE->getValue();
4427    if (Imm1 < INT32_MIN || Imm1 > UINT32_MAX) {
4428      Error(Sx1, "immediate operand must be representable with 32 bits");
4429      return MatchOperand_ParseFail;
4430    }
4431
4432    int Enc = ARM_AM::getSOImmVal(Imm1);
4433    if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
4434      // We have a match!
4435      Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
4436                                                  (Enc & 0xF00) >> 7,
4437                                                  Sx1, Ex1));
4438      return MatchOperand_Success;
4439    }
4440
4441    // We have parsed an immediate which is not for us, fallback to a plain
4442    // immediate. This can happen for instruction aliases. For an example,
4443    // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
4444    // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
4445    // instruction with a mod_imm operand. The alias is defined such that the
4446    // parser method is shared, that's why we have to do this here.
4447    if (Parser.getTok().is(AsmToken::EndOfStatement)) {
4448      Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4449      return MatchOperand_Success;
4450    }
4451  } else {
4452    // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
4453    // MCFixup). Fallback to a plain immediate.
4454    Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4455    return MatchOperand_Success;
4456  }
4457
4458  // From this point onward, we expect the input to be a (#bits, #rot) pair
4459  if (Parser.getTok().isNot(AsmToken::Comma)) {
4460    Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
4461    return MatchOperand_ParseFail;
4462  }
4463
4464  if (Imm1 & ~0xFF) {
4465    Error(Sx1, "immediate operand must a number in the range [0, 255]");
4466    return MatchOperand_ParseFail;
4467  }
4468
4469  // Eat the comma
4470  Parser.Lex();
4471
4472  // Repeat for #rot
4473  SMLoc Sx2, Ex2;
4474  Sx2 = Parser.getTok().getLoc();
4475
4476  // Eat the optional hash (dollar)
4477  if (Parser.getTok().is(AsmToken::Hash) ||
4478      Parser.getTok().is(AsmToken::Dollar))
4479    Parser.Lex();
4480
4481  const MCExpr *Imm2Exp;
4482  if (getParser().parseExpression(Imm2Exp, Ex2)) {
4483    Error(Sx2, "malformed expression");
4484    return MatchOperand_ParseFail;
4485  }
4486
4487  CE = dyn_cast<MCConstantExpr>(Imm2Exp);
4488
4489  if (CE) {
4490    Imm2 = CE->getValue();
4491    if (!(Imm2 & ~0x1E)) {
4492      // We have a match!
4493      Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
4494      return MatchOperand_Success;
4495    }
4496    Error(Sx2, "immediate operand must an even number in the range [0, 30]");
4497    return MatchOperand_ParseFail;
4498  } else {
4499    Error(Sx2, "constant expression expected");
4500    return MatchOperand_ParseFail;
4501  }
4502}
4503
4504ARMAsmParser::OperandMatchResultTy
4505ARMAsmParser::parseBitfield(OperandVector &Operands) {
4506  MCAsmParser &Parser = getParser();
4507  SMLoc S = Parser.getTok().getLoc();
4508  // The bitfield descriptor is really two operands, the LSB and the width.
4509  if (Parser.getTok().isNot(AsmToken::Hash) &&
4510      Parser.getTok().isNot(AsmToken::Dollar)) {
4511    Error(Parser.getTok().getLoc(), "'#' expected");
4512    return MatchOperand_ParseFail;
4513  }
4514  Parser.Lex(); // Eat hash token.
4515
4516  const MCExpr *LSBExpr;
4517  SMLoc E = Parser.getTok().getLoc();
4518  if (getParser().parseExpression(LSBExpr)) {
4519    Error(E, "malformed immediate expression");
4520    return MatchOperand_ParseFail;
4521  }
4522  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4523  if (!CE) {
4524    Error(E, "'lsb' operand must be an immediate");
4525    return MatchOperand_ParseFail;
4526  }
4527
4528  int64_t LSB = CE->getValue();
4529  // The LSB must be in the range [0,31]
4530  if (LSB < 0 || LSB > 31) {
4531    Error(E, "'lsb' operand must be in the range [0,31]");
4532    return MatchOperand_ParseFail;
4533  }
4534  E = Parser.getTok().getLoc();
4535
4536  // Expect another immediate operand.
4537  if (Parser.getTok().isNot(AsmToken::Comma)) {
4538    Error(Parser.getTok().getLoc(), "too few operands");
4539    return MatchOperand_ParseFail;
4540  }
4541  Parser.Lex(); // Eat hash token.
4542  if (Parser.getTok().isNot(AsmToken::Hash) &&
4543      Parser.getTok().isNot(AsmToken::Dollar)) {
4544    Error(Parser.getTok().getLoc(), "'#' expected");
4545    return MatchOperand_ParseFail;
4546  }
4547  Parser.Lex(); // Eat hash token.
4548
4549  const MCExpr *WidthExpr;
4550  SMLoc EndLoc;
4551  if (getParser().parseExpression(WidthExpr, EndLoc)) {
4552    Error(E, "malformed immediate expression");
4553    return MatchOperand_ParseFail;
4554  }
4555  CE = dyn_cast<MCConstantExpr>(WidthExpr);
4556  if (!CE) {
4557    Error(E, "'width' operand must be an immediate");
4558    return MatchOperand_ParseFail;
4559  }
4560
4561  int64_t Width = CE->getValue();
4562  // The LSB must be in the range [1,32-lsb]
4563  if (Width < 1 || Width > 32 - LSB) {
4564    Error(E, "'width' operand must be in the range [1,32-lsb]");
4565    return MatchOperand_ParseFail;
4566  }
4567
4568  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4569
4570  return MatchOperand_Success;
4571}
4572
4573ARMAsmParser::OperandMatchResultTy
4574ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4575  // Check for a post-index addressing register operand. Specifically:
4576  // postidx_reg := '+' register {, shift}
4577  //              | '-' register {, shift}
4578  //              | register {, shift}
4579
4580  // This method must return MatchOperand_NoMatch without consuming any tokens
4581  // in the case where there is no match, as other alternatives take other
4582  // parse methods.
4583  MCAsmParser &Parser = getParser();
4584  AsmToken Tok = Parser.getTok();
4585  SMLoc S = Tok.getLoc();
4586  bool haveEaten = false;
4587  bool isAdd = true;
4588  if (Tok.is(AsmToken::Plus)) {
4589    Parser.Lex(); // Eat the '+' token.
4590    haveEaten = true;
4591  } else if (Tok.is(AsmToken::Minus)) {
4592    Parser.Lex(); // Eat the '-' token.
4593    isAdd = false;
4594    haveEaten = true;
4595  }
4596
4597  SMLoc E = Parser.getTok().getEndLoc();
4598  int Reg = tryParseRegister();
4599  if (Reg == -1) {
4600    if (!haveEaten)
4601      return MatchOperand_NoMatch;
4602    Error(Parser.getTok().getLoc(), "register expected");
4603    return MatchOperand_ParseFail;
4604  }
4605
4606  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4607  unsigned ShiftImm = 0;
4608  if (Parser.getTok().is(AsmToken::Comma)) {
4609    Parser.Lex(); // Eat the ','.
4610    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4611      return MatchOperand_ParseFail;
4612
4613    // FIXME: Only approximates end...may include intervening whitespace.
4614    E = Parser.getTok().getLoc();
4615  }
4616
4617  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4618                                                  ShiftImm, S, E));
4619
4620  return MatchOperand_Success;
4621}
4622
4623ARMAsmParser::OperandMatchResultTy
4624ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4625  // Check for a post-index addressing register operand. Specifically:
4626  // am3offset := '+' register
4627  //              | '-' register
4628  //              | register
4629  //              | # imm
4630  //              | # + imm
4631  //              | # - imm
4632
4633  // This method must return MatchOperand_NoMatch without consuming any tokens
4634  // in the case where there is no match, as other alternatives take other
4635  // parse methods.
4636  MCAsmParser &Parser = getParser();
4637  AsmToken Tok = Parser.getTok();
4638  SMLoc S = Tok.getLoc();
4639
4640  // Do immediates first, as we always parse those if we have a '#'.
4641  if (Parser.getTok().is(AsmToken::Hash) ||
4642      Parser.getTok().is(AsmToken::Dollar)) {
4643    Parser.Lex(); // Eat '#' or '$'.
4644    // Explicitly look for a '-', as we need to encode negative zero
4645    // differently.
4646    bool isNegative = Parser.getTok().is(AsmToken::Minus);
4647    const MCExpr *Offset;
4648    SMLoc E;
4649    if (getParser().parseExpression(Offset, E))
4650      return MatchOperand_ParseFail;
4651    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4652    if (!CE) {
4653      Error(S, "constant expression expected");
4654      return MatchOperand_ParseFail;
4655    }
4656    // Negative zero is encoded as the flag value INT32_MIN.
4657    int32_t Val = CE->getValue();
4658    if (isNegative && Val == 0)
4659      Val = INT32_MIN;
4660
4661    Operands.push_back(
4662      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4663
4664    return MatchOperand_Success;
4665  }
4666
4667
4668  bool haveEaten = false;
4669  bool isAdd = true;
4670  if (Tok.is(AsmToken::Plus)) {
4671    Parser.Lex(); // Eat the '+' token.
4672    haveEaten = true;
4673  } else if (Tok.is(AsmToken::Minus)) {
4674    Parser.Lex(); // Eat the '-' token.
4675    isAdd = false;
4676    haveEaten = true;
4677  }
4678
4679  Tok = Parser.getTok();
4680  int Reg = tryParseRegister();
4681  if (Reg == -1) {
4682    if (!haveEaten)
4683      return MatchOperand_NoMatch;
4684    Error(Tok.getLoc(), "register expected");
4685    return MatchOperand_ParseFail;
4686  }
4687
4688  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4689                                                  0, S, Tok.getEndLoc()));
4690
4691  return MatchOperand_Success;
4692}
4693
4694/// Convert parsed operands to MCInst.  Needed here because this instruction
4695/// only has two register operands, but multiplication is commutative so
4696/// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4697void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4698                                    const OperandVector &Operands) {
4699  ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4700  ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4701  // If we have a three-operand form, make sure to set Rn to be the operand
4702  // that isn't the same as Rd.
4703  unsigned RegOp = 4;
4704  if (Operands.size() == 6 &&
4705      ((ARMOperand &)*Operands[4]).getReg() ==
4706          ((ARMOperand &)*Operands[3]).getReg())
4707    RegOp = 5;
4708  ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4709  Inst.addOperand(Inst.getOperand(0));
4710  ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4711}
4712
4713void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4714                                    const OperandVector &Operands) {
4715  int CondOp = -1, ImmOp = -1;
4716  switch(Inst.getOpcode()) {
4717    case ARM::tB:
4718    case ARM::tBcc:  CondOp = 1; ImmOp = 2; break;
4719
4720    case ARM::t2B:
4721    case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4722
4723    default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4724  }
4725  // first decide whether or not the branch should be conditional
4726  // by looking at it's location relative to an IT block
4727  if(inITBlock()) {
4728    // inside an IT block we cannot have any conditional branches. any
4729    // such instructions needs to be converted to unconditional form
4730    switch(Inst.getOpcode()) {
4731      case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4732      case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4733    }
4734  } else {
4735    // outside IT blocks we can only have unconditional branches with AL
4736    // condition code or conditional branches with non-AL condition code
4737    unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
4738    switch(Inst.getOpcode()) {
4739      case ARM::tB:
4740      case ARM::tBcc:
4741        Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4742        break;
4743      case ARM::t2B:
4744      case ARM::t2Bcc:
4745        Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4746        break;
4747    }
4748  }
4749
4750  // now decide on encoding size based on branch target range
4751  switch(Inst.getOpcode()) {
4752    // classify tB as either t2B or t1B based on range of immediate operand
4753    case ARM::tB: {
4754      ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4755      if (!op.isSignedOffset<11, 1>() && isThumbTwo())
4756        Inst.setOpcode(ARM::t2B);
4757      break;
4758    }
4759    // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4760    case ARM::tBcc: {
4761      ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4762      if (!op.isSignedOffset<8, 1>() && isThumbTwo())
4763        Inst.setOpcode(ARM::t2Bcc);
4764      break;
4765    }
4766  }
4767  ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
4768  ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
4769}
4770
4771/// Parse an ARM memory expression, return false if successful else return true
4772/// or an error.  The first token must be a '[' when called.
4773bool ARMAsmParser::parseMemory(OperandVector &Operands) {
4774  MCAsmParser &Parser = getParser();
4775  SMLoc S, E;
4776  assert(Parser.getTok().is(AsmToken::LBrac) &&
4777         "Token is not a Left Bracket");
4778  S = Parser.getTok().getLoc();
4779  Parser.Lex(); // Eat left bracket token.
4780
4781  const AsmToken &BaseRegTok = Parser.getTok();
4782  int BaseRegNum = tryParseRegister();
4783  if (BaseRegNum == -1)
4784    return Error(BaseRegTok.getLoc(), "register expected");
4785
4786  // The next token must either be a comma, a colon or a closing bracket.
4787  const AsmToken &Tok = Parser.getTok();
4788  if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4789      !Tok.is(AsmToken::RBrac))
4790    return Error(Tok.getLoc(), "malformed memory operand");
4791
4792  if (Tok.is(AsmToken::RBrac)) {
4793    E = Tok.getEndLoc();
4794    Parser.Lex(); // Eat right bracket token.
4795
4796    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4797                                             ARM_AM::no_shift, 0, 0, false,
4798                                             S, E));
4799
4800    // If there's a pre-indexing writeback marker, '!', just add it as a token
4801    // operand. It's rather odd, but syntactically valid.
4802    if (Parser.getTok().is(AsmToken::Exclaim)) {
4803      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4804      Parser.Lex(); // Eat the '!'.
4805    }
4806
4807    return false;
4808  }
4809
4810  assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4811         "Lost colon or comma in memory operand?!");
4812  if (Tok.is(AsmToken::Comma)) {
4813    Parser.Lex(); // Eat the comma.
4814  }
4815
4816  // If we have a ':', it's an alignment specifier.
4817  if (Parser.getTok().is(AsmToken::Colon)) {
4818    Parser.Lex(); // Eat the ':'.
4819    E = Parser.getTok().getLoc();
4820    SMLoc AlignmentLoc = Tok.getLoc();
4821
4822    const MCExpr *Expr;
4823    if (getParser().parseExpression(Expr))
4824     return true;
4825
4826    // The expression has to be a constant. Memory references with relocations
4827    // don't come through here, as they use the <label> forms of the relevant
4828    // instructions.
4829    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4830    if (!CE)
4831      return Error (E, "constant expression expected");
4832
4833    unsigned Align = 0;
4834    switch (CE->getValue()) {
4835    default:
4836      return Error(E,
4837                   "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4838    case 16:  Align = 2; break;
4839    case 32:  Align = 4; break;
4840    case 64:  Align = 8; break;
4841    case 128: Align = 16; break;
4842    case 256: Align = 32; break;
4843    }
4844
4845    // Now we should have the closing ']'
4846    if (Parser.getTok().isNot(AsmToken::RBrac))
4847      return Error(Parser.getTok().getLoc(), "']' expected");
4848    E = Parser.getTok().getEndLoc();
4849    Parser.Lex(); // Eat right bracket token.
4850
4851    // Don't worry about range checking the value here. That's handled by
4852    // the is*() predicates.
4853    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4854                                             ARM_AM::no_shift, 0, Align,
4855                                             false, S, E, AlignmentLoc));
4856
4857    // If there's a pre-indexing writeback marker, '!', just add it as a token
4858    // operand.
4859    if (Parser.getTok().is(AsmToken::Exclaim)) {
4860      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4861      Parser.Lex(); // Eat the '!'.
4862    }
4863
4864    return false;
4865  }
4866
4867  // If we have a '#', it's an immediate offset, else assume it's a register
4868  // offset. Be friendly and also accept a plain integer (without a leading
4869  // hash) for gas compatibility.
4870  if (Parser.getTok().is(AsmToken::Hash) ||
4871      Parser.getTok().is(AsmToken::Dollar) ||
4872      Parser.getTok().is(AsmToken::Integer)) {
4873    if (Parser.getTok().isNot(AsmToken::Integer))
4874      Parser.Lex(); // Eat '#' or '$'.
4875    E = Parser.getTok().getLoc();
4876
4877    bool isNegative = getParser().getTok().is(AsmToken::Minus);
4878    const MCExpr *Offset;
4879    if (getParser().parseExpression(Offset))
4880     return true;
4881
4882    // The expression has to be a constant. Memory references with relocations
4883    // don't come through here, as they use the <label> forms of the relevant
4884    // instructions.
4885    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4886    if (!CE)
4887      return Error (E, "constant expression expected");
4888
4889    // If the constant was #-0, represent it as INT32_MIN.
4890    int32_t Val = CE->getValue();
4891    if (isNegative && Val == 0)
4892      CE = MCConstantExpr::Create(INT32_MIN, getContext());
4893
4894    // Now we should have the closing ']'
4895    if (Parser.getTok().isNot(AsmToken::RBrac))
4896      return Error(Parser.getTok().getLoc(), "']' expected");
4897    E = Parser.getTok().getEndLoc();
4898    Parser.Lex(); // Eat right bracket token.
4899
4900    // Don't worry about range checking the value here. That's handled by
4901    // the is*() predicates.
4902    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4903                                             ARM_AM::no_shift, 0, 0,
4904                                             false, S, E));
4905
4906    // If there's a pre-indexing writeback marker, '!', just add it as a token
4907    // operand.
4908    if (Parser.getTok().is(AsmToken::Exclaim)) {
4909      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4910      Parser.Lex(); // Eat the '!'.
4911    }
4912
4913    return false;
4914  }
4915
4916  // The register offset is optionally preceded by a '+' or '-'
4917  bool isNegative = false;
4918  if (Parser.getTok().is(AsmToken::Minus)) {
4919    isNegative = true;
4920    Parser.Lex(); // Eat the '-'.
4921  } else if (Parser.getTok().is(AsmToken::Plus)) {
4922    // Nothing to do.
4923    Parser.Lex(); // Eat the '+'.
4924  }
4925
4926  E = Parser.getTok().getLoc();
4927  int OffsetRegNum = tryParseRegister();
4928  if (OffsetRegNum == -1)
4929    return Error(E, "register expected");
4930
4931  // If there's a shift operator, handle it.
4932  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4933  unsigned ShiftImm = 0;
4934  if (Parser.getTok().is(AsmToken::Comma)) {
4935    Parser.Lex(); // Eat the ','.
4936    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4937      return true;
4938  }
4939
4940  // Now we should have the closing ']'
4941  if (Parser.getTok().isNot(AsmToken::RBrac))
4942    return Error(Parser.getTok().getLoc(), "']' expected");
4943  E = Parser.getTok().getEndLoc();
4944  Parser.Lex(); // Eat right bracket token.
4945
4946  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
4947                                           ShiftType, ShiftImm, 0, isNegative,
4948                                           S, E));
4949
4950  // If there's a pre-indexing writeback marker, '!', just add it as a token
4951  // operand.
4952  if (Parser.getTok().is(AsmToken::Exclaim)) {
4953    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4954    Parser.Lex(); // Eat the '!'.
4955  }
4956
4957  return false;
4958}
4959
4960/// parseMemRegOffsetShift - one of these two:
4961///   ( lsl | lsr | asr | ror ) , # shift_amount
4962///   rrx
4963/// return true if it parses a shift otherwise it returns false.
4964bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4965                                          unsigned &Amount) {
4966  MCAsmParser &Parser = getParser();
4967  SMLoc Loc = Parser.getTok().getLoc();
4968  const AsmToken &Tok = Parser.getTok();
4969  if (Tok.isNot(AsmToken::Identifier))
4970    return true;
4971  StringRef ShiftName = Tok.getString();
4972  if (ShiftName == "lsl" || ShiftName == "LSL" ||
4973      ShiftName == "asl" || ShiftName == "ASL")
4974    St = ARM_AM::lsl;
4975  else if (ShiftName == "lsr" || ShiftName == "LSR")
4976    St = ARM_AM::lsr;
4977  else if (ShiftName == "asr" || ShiftName == "ASR")
4978    St = ARM_AM::asr;
4979  else if (ShiftName == "ror" || ShiftName == "ROR")
4980    St = ARM_AM::ror;
4981  else if (ShiftName == "rrx" || ShiftName == "RRX")
4982    St = ARM_AM::rrx;
4983  else
4984    return Error(Loc, "illegal shift operator");
4985  Parser.Lex(); // Eat shift type token.
4986
4987  // rrx stands alone.
4988  Amount = 0;
4989  if (St != ARM_AM::rrx) {
4990    Loc = Parser.getTok().getLoc();
4991    // A '#' and a shift amount.
4992    const AsmToken &HashTok = Parser.getTok();
4993    if (HashTok.isNot(AsmToken::Hash) &&
4994        HashTok.isNot(AsmToken::Dollar))
4995      return Error(HashTok.getLoc(), "'#' expected");
4996    Parser.Lex(); // Eat hash token.
4997
4998    const MCExpr *Expr;
4999    if (getParser().parseExpression(Expr))
5000      return true;
5001    // Range check the immediate.
5002    // lsl, ror: 0 <= imm <= 31
5003    // lsr, asr: 0 <= imm <= 32
5004    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5005    if (!CE)
5006      return Error(Loc, "shift amount must be an immediate");
5007    int64_t Imm = CE->getValue();
5008    if (Imm < 0 ||
5009        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
5010        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
5011      return Error(Loc, "immediate shift value out of range");
5012    // If <ShiftTy> #0, turn it into a no_shift.
5013    if (Imm == 0)
5014      St = ARM_AM::lsl;
5015    // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
5016    if (Imm == 32)
5017      Imm = 0;
5018    Amount = Imm;
5019  }
5020
5021  return false;
5022}
5023
5024/// parseFPImm - A floating point immediate expression operand.
5025ARMAsmParser::OperandMatchResultTy
5026ARMAsmParser::parseFPImm(OperandVector &Operands) {
5027  MCAsmParser &Parser = getParser();
5028  // Anything that can accept a floating point constant as an operand
5029  // needs to go through here, as the regular parseExpression is
5030  // integer only.
5031  //
5032  // This routine still creates a generic Immediate operand, containing
5033  // a bitcast of the 64-bit floating point value. The various operands
5034  // that accept floats can check whether the value is valid for them
5035  // via the standard is*() predicates.
5036
5037  SMLoc S = Parser.getTok().getLoc();
5038
5039  if (Parser.getTok().isNot(AsmToken::Hash) &&
5040      Parser.getTok().isNot(AsmToken::Dollar))
5041    return MatchOperand_NoMatch;
5042
5043  // Disambiguate the VMOV forms that can accept an FP immediate.
5044  // vmov.f32 <sreg>, #imm
5045  // vmov.f64 <dreg>, #imm
5046  // vmov.f32 <dreg>, #imm  @ vector f32x2
5047  // vmov.f32 <qreg>, #imm  @ vector f32x4
5048  //
5049  // There are also the NEON VMOV instructions which expect an
5050  // integer constant. Make sure we don't try to parse an FPImm
5051  // for these:
5052  // vmov.i{8|16|32|64} <dreg|qreg>, #imm
5053  ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
5054  bool isVmovf = TyOp.isToken() &&
5055                 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64");
5056  ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
5057  bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
5058                                         Mnemonic.getToken() == "fconsts");
5059  if (!(isVmovf || isFconst))
5060    return MatchOperand_NoMatch;
5061
5062  Parser.Lex(); // Eat '#' or '$'.
5063
5064  // Handle negation, as that still comes through as a separate token.
5065  bool isNegative = false;
5066  if (Parser.getTok().is(AsmToken::Minus)) {
5067    isNegative = true;
5068    Parser.Lex();
5069  }
5070  const AsmToken &Tok = Parser.getTok();
5071  SMLoc Loc = Tok.getLoc();
5072  if (Tok.is(AsmToken::Real) && isVmovf) {
5073    APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
5074    uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
5075    // If we had a '-' in front, toggle the sign bit.
5076    IntVal ^= (uint64_t)isNegative << 31;
5077    Parser.Lex(); // Eat the token.
5078    Operands.push_back(ARMOperand::CreateImm(
5079          MCConstantExpr::Create(IntVal, getContext()),
5080          S, Parser.getTok().getLoc()));
5081    return MatchOperand_Success;
5082  }
5083  // Also handle plain integers. Instructions which allow floating point
5084  // immediates also allow a raw encoded 8-bit value.
5085  if (Tok.is(AsmToken::Integer) && isFconst) {
5086    int64_t Val = Tok.getIntVal();
5087    Parser.Lex(); // Eat the token.
5088    if (Val > 255 || Val < 0) {
5089      Error(Loc, "encoded floating point value out of range");
5090      return MatchOperand_ParseFail;
5091    }
5092    float RealVal = ARM_AM::getFPImmFloat(Val);
5093    Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
5094
5095    Operands.push_back(ARMOperand::CreateImm(
5096        MCConstantExpr::Create(Val, getContext()), S,
5097        Parser.getTok().getLoc()));
5098    return MatchOperand_Success;
5099  }
5100
5101  Error(Loc, "invalid floating point immediate");
5102  return MatchOperand_ParseFail;
5103}
5104
5105/// Parse a arm instruction operand.  For now this parses the operand regardless
5106/// of the mnemonic.
5107bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
5108  MCAsmParser &Parser = getParser();
5109  SMLoc S, E;
5110
5111  // Check if the current operand has a custom associated parser, if so, try to
5112  // custom parse the operand, or fallback to the general approach.
5113  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
5114  if (ResTy == MatchOperand_Success)
5115    return false;
5116  // If there wasn't a custom match, try the generic matcher below. Otherwise,
5117  // there was a match, but an error occurred, in which case, just return that
5118  // the operand parsing failed.
5119  if (ResTy == MatchOperand_ParseFail)
5120    return true;
5121
5122  switch (getLexer().getKind()) {
5123  default:
5124    Error(Parser.getTok().getLoc(), "unexpected token in operand");
5125    return true;
5126  case AsmToken::Identifier: {
5127    // If we've seen a branch mnemonic, the next operand must be a label.  This
5128    // is true even if the label is a register name.  So "br r1" means branch to
5129    // label "r1".
5130    bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
5131    if (!ExpectLabel) {
5132      if (!tryParseRegisterWithWriteBack(Operands))
5133        return false;
5134      int Res = tryParseShiftRegister(Operands);
5135      if (Res == 0) // success
5136        return false;
5137      else if (Res == -1) // irrecoverable error
5138        return true;
5139      // If this is VMRS, check for the apsr_nzcv operand.
5140      if (Mnemonic == "vmrs" &&
5141          Parser.getTok().getString().equals_lower("apsr_nzcv")) {
5142        S = Parser.getTok().getLoc();
5143        Parser.Lex();
5144        Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
5145        return false;
5146      }
5147    }
5148
5149    // Fall though for the Identifier case that is not a register or a
5150    // special name.
5151  }
5152  case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
5153  case AsmToken::Integer: // things like 1f and 2b as a branch targets
5154  case AsmToken::String:  // quoted label names.
5155  case AsmToken::Dot: {   // . as a branch target
5156    // This was not a register so parse other operands that start with an
5157    // identifier (like labels) as expressions and create them as immediates.
5158    const MCExpr *IdVal;
5159    S = Parser.getTok().getLoc();
5160    if (getParser().parseExpression(IdVal))
5161      return true;
5162    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5163    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
5164    return false;
5165  }
5166  case AsmToken::LBrac:
5167    return parseMemory(Operands);
5168  case AsmToken::LCurly:
5169    return parseRegisterList(Operands);
5170  case AsmToken::Dollar:
5171  case AsmToken::Hash: {
5172    // #42 -> immediate.
5173    S = Parser.getTok().getLoc();
5174    Parser.Lex();
5175
5176    if (Parser.getTok().isNot(AsmToken::Colon)) {
5177      bool isNegative = Parser.getTok().is(AsmToken::Minus);
5178      const MCExpr *ImmVal;
5179      if (getParser().parseExpression(ImmVal))
5180        return true;
5181      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
5182      if (CE) {
5183        int32_t Val = CE->getValue();
5184        if (isNegative && Val == 0)
5185          ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
5186      }
5187      E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5188      Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
5189
5190      // There can be a trailing '!' on operands that we want as a separate
5191      // '!' Token operand. Handle that here. For example, the compatibility
5192      // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
5193      if (Parser.getTok().is(AsmToken::Exclaim)) {
5194        Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
5195                                                   Parser.getTok().getLoc()));
5196        Parser.Lex(); // Eat exclaim token
5197      }
5198      return false;
5199    }
5200    // w/ a ':' after the '#', it's just like a plain ':'.
5201    // FALLTHROUGH
5202  }
5203  case AsmToken::Colon: {
5204    // ":lower16:" and ":upper16:" expression prefixes
5205    // FIXME: Check it's an expression prefix,
5206    // e.g. (FOO - :lower16:BAR) isn't legal.
5207    ARMMCExpr::VariantKind RefKind;
5208    if (parsePrefix(RefKind))
5209      return true;
5210
5211    const MCExpr *SubExprVal;
5212    if (getParser().parseExpression(SubExprVal))
5213      return true;
5214
5215    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
5216                                              getContext());
5217    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5218    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
5219    return false;
5220  }
5221  case AsmToken::Equal: {
5222    if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
5223      return Error(Parser.getTok().getLoc(), "unexpected token in operand");
5224
5225    Parser.Lex(); // Eat '='
5226    const MCExpr *SubExprVal;
5227    if (getParser().parseExpression(SubExprVal))
5228      return true;
5229    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5230
5231    const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
5232    Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
5233    return false;
5234  }
5235  }
5236}
5237
5238// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
5239//  :lower16: and :upper16:.
5240bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
5241  MCAsmParser &Parser = getParser();
5242  RefKind = ARMMCExpr::VK_ARM_None;
5243
5244  // consume an optional '#' (GNU compatibility)
5245  if (getLexer().is(AsmToken::Hash))
5246    Parser.Lex();
5247
5248  // :lower16: and :upper16: modifiers
5249  assert(getLexer().is(AsmToken::Colon) && "expected a :");
5250  Parser.Lex(); // Eat ':'
5251
5252  if (getLexer().isNot(AsmToken::Identifier)) {
5253    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
5254    return true;
5255  }
5256
5257  enum {
5258    COFF = (1 << MCObjectFileInfo::IsCOFF),
5259    ELF = (1 << MCObjectFileInfo::IsELF),
5260    MACHO = (1 << MCObjectFileInfo::IsMachO)
5261  };
5262  static const struct PrefixEntry {
5263    const char *Spelling;
5264    ARMMCExpr::VariantKind VariantKind;
5265    uint8_t SupportedFormats;
5266  } PrefixEntries[] = {
5267    { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO },
5268    { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO },
5269  };
5270
5271  StringRef IDVal = Parser.getTok().getIdentifier();
5272
5273  const auto &Prefix =
5274      std::find_if(std::begin(PrefixEntries), std::end(PrefixEntries),
5275                   [&IDVal](const PrefixEntry &PE) {
5276                      return PE.Spelling == IDVal;
5277                   });
5278  if (Prefix == std::end(PrefixEntries)) {
5279    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
5280    return true;
5281  }
5282
5283  uint8_t CurrentFormat;
5284  switch (getContext().getObjectFileInfo()->getObjectFileType()) {
5285  case MCObjectFileInfo::IsMachO:
5286    CurrentFormat = MACHO;
5287    break;
5288  case MCObjectFileInfo::IsELF:
5289    CurrentFormat = ELF;
5290    break;
5291  case MCObjectFileInfo::IsCOFF:
5292    CurrentFormat = COFF;
5293    break;
5294  }
5295
5296  if (~Prefix->SupportedFormats & CurrentFormat) {
5297    Error(Parser.getTok().getLoc(),
5298          "cannot represent relocation in the current file format");
5299    return true;
5300  }
5301
5302  RefKind = Prefix->VariantKind;
5303  Parser.Lex();
5304
5305  if (getLexer().isNot(AsmToken::Colon)) {
5306    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
5307    return true;
5308  }
5309  Parser.Lex(); // Eat the last ':'
5310
5311  return false;
5312}
5313
5314/// \brief Given a mnemonic, split out possible predication code and carry
5315/// setting letters to form a canonical mnemonic and flags.
5316//
5317// FIXME: Would be nice to autogen this.
5318// FIXME: This is a bit of a maze of special cases.
5319StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
5320                                      unsigned &PredicationCode,
5321                                      bool &CarrySetting,
5322                                      unsigned &ProcessorIMod,
5323                                      StringRef &ITMask) {
5324  PredicationCode = ARMCC::AL;
5325  CarrySetting = false;
5326  ProcessorIMod = 0;
5327
5328  // Ignore some mnemonics we know aren't predicated forms.
5329  //
5330  // FIXME: Would be nice to autogen this.
5331  if ((Mnemonic == "movs" && isThumb()) ||
5332      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
5333      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
5334      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
5335      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
5336      Mnemonic == "vaclt" || Mnemonic == "vacle"  || Mnemonic == "hlt" ||
5337      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
5338      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
5339      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
5340      Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
5341      Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
5342      Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
5343      Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
5344      Mnemonic.startswith("vsel"))
5345    return Mnemonic;
5346
5347  // First, split out any predication code. Ignore mnemonics we know aren't
5348  // predicated but do have a carry-set and so weren't caught above.
5349  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
5350      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
5351      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
5352      Mnemonic != "sbcs" && Mnemonic != "rscs") {
5353    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
5354      .Case("eq", ARMCC::EQ)
5355      .Case("ne", ARMCC::NE)
5356      .Case("hs", ARMCC::HS)
5357      .Case("cs", ARMCC::HS)
5358      .Case("lo", ARMCC::LO)
5359      .Case("cc", ARMCC::LO)
5360      .Case("mi", ARMCC::MI)
5361      .Case("pl", ARMCC::PL)
5362      .Case("vs", ARMCC::VS)
5363      .Case("vc", ARMCC::VC)
5364      .Case("hi", ARMCC::HI)
5365      .Case("ls", ARMCC::LS)
5366      .Case("ge", ARMCC::GE)
5367      .Case("lt", ARMCC::LT)
5368      .Case("gt", ARMCC::GT)
5369      .Case("le", ARMCC::LE)
5370      .Case("al", ARMCC::AL)
5371      .Default(~0U);
5372    if (CC != ~0U) {
5373      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
5374      PredicationCode = CC;
5375    }
5376  }
5377
5378  // Next, determine if we have a carry setting bit. We explicitly ignore all
5379  // the instructions we know end in 's'.
5380  if (Mnemonic.endswith("s") &&
5381      !(Mnemonic == "cps" || Mnemonic == "mls" ||
5382        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
5383        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
5384        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
5385        Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
5386        Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
5387        Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
5388        Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
5389        Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5390        (Mnemonic == "movs" && isThumb()))) {
5391    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
5392    CarrySetting = true;
5393  }
5394
5395  // The "cps" instruction can have a interrupt mode operand which is glued into
5396  // the mnemonic. Check if this is the case, split it and parse the imod op
5397  if (Mnemonic.startswith("cps")) {
5398    // Split out any imod code.
5399    unsigned IMod =
5400      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
5401      .Case("ie", ARM_PROC::IE)
5402      .Case("id", ARM_PROC::ID)
5403      .Default(~0U);
5404    if (IMod != ~0U) {
5405      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5406      ProcessorIMod = IMod;
5407    }
5408  }
5409
5410  // The "it" instruction has the condition mask on the end of the mnemonic.
5411  if (Mnemonic.startswith("it")) {
5412    ITMask = Mnemonic.slice(2, Mnemonic.size());
5413    Mnemonic = Mnemonic.slice(0, 2);
5414  }
5415
5416  return Mnemonic;
5417}
5418
5419/// \brief Given a canonical mnemonic, determine if the instruction ever allows
5420/// inclusion of carry set or predication code operands.
5421//
5422// FIXME: It would be nice to autogen this.
5423void ARMAsmParser::
5424getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5425                     bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
5426  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5427      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5428      Mnemonic == "add" || Mnemonic == "adc" ||
5429      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
5430      Mnemonic == "orr" || Mnemonic == "mvn" ||
5431      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
5432      Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
5433      Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5434      (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
5435                      Mnemonic == "mla" || Mnemonic == "smlal" ||
5436                      Mnemonic == "umlal" || Mnemonic == "umull"))) {
5437    CanAcceptCarrySet = true;
5438  } else
5439    CanAcceptCarrySet = false;
5440
5441  if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5442      Mnemonic == "cps" ||  Mnemonic == "it" ||  Mnemonic == "cbz" ||
5443      Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
5444      Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
5445      Mnemonic.startswith("vsel") ||
5446      Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
5447      Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
5448      Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
5449      Mnemonic == "vrintm" || Mnemonic.startswith("aes") || Mnemonic == "hvc" ||
5450      Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5451      (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
5452    // These mnemonics are never predicable
5453    CanAcceptPredicationCode = false;
5454  } else if (!isThumb()) {
5455    // Some instructions are only predicable in Thumb mode
5456    CanAcceptPredicationCode
5457      = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5458        Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5459        Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5460        Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5461        Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5462        Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5463        !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
5464  } else if (isThumbOne()) {
5465    if (hasV6MOps())
5466      CanAcceptPredicationCode = Mnemonic != "movs";
5467    else
5468      CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5469  } else
5470    CanAcceptPredicationCode = true;
5471}
5472
5473bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5474                                          OperandVector &Operands) {
5475  // FIXME: This is all horribly hacky. We really need a better way to deal
5476  // with optional operands like this in the matcher table.
5477
5478  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5479  // another does not. Specifically, the MOVW instruction does not. So we
5480  // special case it here and remove the defaulted (non-setting) cc_out
5481  // operand if that's the instruction we're trying to match.
5482  //
5483  // We do this as post-processing of the explicit operands rather than just
5484  // conditionally adding the cc_out in the first place because we need
5485  // to check the type of the parsed immediate operand.
5486  if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5487      !static_cast<ARMOperand &>(*Operands[4]).isModImm() &&
5488      static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
5489      static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5490    return true;
5491
5492  // Register-register 'add' for thumb does not have a cc_out operand
5493  // when there are only two register operands.
5494  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5495      static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5496      static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5497      static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5498    return true;
5499  // Register-register 'add' for thumb does not have a cc_out operand
5500  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5501  // have to check the immediate range here since Thumb2 has a variant
5502  // that can handle a different range and has a cc_out operand.
5503  if (((isThumb() && Mnemonic == "add") ||
5504       (isThumbTwo() && Mnemonic == "sub")) &&
5505      Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5506      static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5507      static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
5508      static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5509      ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
5510       static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
5511    return true;
5512  // For Thumb2, add/sub immediate does not have a cc_out operand for the
5513  // imm0_4095 variant. That's the least-preferred variant when
5514  // selecting via the generic "add" mnemonic, so to know that we
5515  // should remove the cc_out operand, we have to explicitly check that
5516  // it's not one of the other variants. Ugh.
5517  if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5518      Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5519      static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5520      static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5521    // Nest conditions rather than one big 'if' statement for readability.
5522    //
5523    // If both registers are low, we're in an IT block, and the immediate is
5524    // in range, we should use encoding T1 instead, which has a cc_out.
5525    if (inITBlock() &&
5526        isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
5527        isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
5528        static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
5529      return false;
5530    // Check against T3. If the second register is the PC, this is an
5531    // alternate form of ADR, which uses encoding T4, so check for that too.
5532    if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
5533        static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
5534      return false;
5535
5536    // Otherwise, we use encoding T4, which does not have a cc_out
5537    // operand.
5538    return true;
5539  }
5540
5541  // The thumb2 multiply instruction doesn't have a CCOut register, so
5542  // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5543  // use the 16-bit encoding or not.
5544  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5545      static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5546      static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5547      static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5548      static_cast<ARMOperand &>(*Operands[5]).isReg() &&
5549      // If the registers aren't low regs, the destination reg isn't the
5550      // same as one of the source regs, or the cc_out operand is zero
5551      // outside of an IT block, we have to use the 32-bit encoding, so
5552      // remove the cc_out operand.
5553      (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5554       !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5555       !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
5556       !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5557                            static_cast<ARMOperand &>(*Operands[5]).getReg() &&
5558                        static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5559                            static_cast<ARMOperand &>(*Operands[4]).getReg())))
5560    return true;
5561
5562  // Also check the 'mul' syntax variant that doesn't specify an explicit
5563  // destination register.
5564  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5565      static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5566      static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5567      static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5568      // If the registers aren't low regs  or the cc_out operand is zero
5569      // outside of an IT block, we have to use the 32-bit encoding, so
5570      // remove the cc_out operand.
5571      (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5572       !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5573       !inITBlock()))
5574    return true;
5575
5576
5577
5578  // Register-register 'add/sub' for thumb does not have a cc_out operand
5579  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5580  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5581  // right, this will result in better diagnostics (which operand is off)
5582  // anyway.
5583  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5584      (Operands.size() == 5 || Operands.size() == 6) &&
5585      static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5586      static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
5587      static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5588      (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
5589       (Operands.size() == 6 &&
5590        static_cast<ARMOperand &>(*Operands[5]).isImm())))
5591    return true;
5592
5593  return false;
5594}
5595
5596bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
5597                                              OperandVector &Operands) {
5598  // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5599  unsigned RegIdx = 3;
5600  if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5601      static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32") {
5602    if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5603        static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32")
5604      RegIdx = 4;
5605
5606    if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
5607        (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
5608             static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
5609         ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
5610             static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
5611      return true;
5612  }
5613  return false;
5614}
5615
5616static bool isDataTypeToken(StringRef Tok) {
5617  return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5618    Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5619    Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5620    Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5621    Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5622    Tok == ".f" || Tok == ".d";
5623}
5624
5625// FIXME: This bit should probably be handled via an explicit match class
5626// in the .td files that matches the suffix instead of having it be
5627// a literal string token the way it is now.
5628static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5629  return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5630}
5631static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
5632                                 unsigned VariantID);
5633
5634static bool RequiresVFPRegListValidation(StringRef Inst,
5635                                         bool &AcceptSinglePrecisionOnly,
5636                                         bool &AcceptDoublePrecisionOnly) {
5637  if (Inst.size() < 7)
5638    return false;
5639
5640  if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5641    StringRef AddressingMode = Inst.substr(4, 2);
5642    if (AddressingMode == "ia" || AddressingMode == "db" ||
5643        AddressingMode == "ea" || AddressingMode == "fd") {
5644      AcceptSinglePrecisionOnly = Inst[6] == 's';
5645      AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5646      return true;
5647    }
5648  }
5649
5650  return false;
5651}
5652
5653/// Parse an arm instruction mnemonic followed by its operands.
5654bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5655                                    SMLoc NameLoc, OperandVector &Operands) {
5656  MCAsmParser &Parser = getParser();
5657  // FIXME: Can this be done via tablegen in some fashion?
5658  bool RequireVFPRegisterListCheck;
5659  bool AcceptSinglePrecisionOnly;
5660  bool AcceptDoublePrecisionOnly;
5661  RequireVFPRegisterListCheck =
5662    RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5663                                 AcceptDoublePrecisionOnly);
5664
5665  // Apply mnemonic aliases before doing anything else, as the destination
5666  // mnemonic may include suffices and we want to handle them normally.
5667  // The generic tblgen'erated code does this later, at the start of
5668  // MatchInstructionImpl(), but that's too late for aliases that include
5669  // any sort of suffix.
5670  uint64_t AvailableFeatures = getAvailableFeatures();
5671  unsigned AssemblerDialect = getParser().getAssemblerDialect();
5672  applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5673
5674  // First check for the ARM-specific .req directive.
5675  if (Parser.getTok().is(AsmToken::Identifier) &&
5676      Parser.getTok().getIdentifier() == ".req") {
5677    parseDirectiveReq(Name, NameLoc);
5678    // We always return 'error' for this, as we're done with this
5679    // statement and don't need to match the 'instruction."
5680    return true;
5681  }
5682
5683  // Create the leading tokens for the mnemonic, split by '.' characters.
5684  size_t Start = 0, Next = Name.find('.');
5685  StringRef Mnemonic = Name.slice(Start, Next);
5686
5687  // Split out the predication code and carry setting flag from the mnemonic.
5688  unsigned PredicationCode;
5689  unsigned ProcessorIMod;
5690  bool CarrySetting;
5691  StringRef ITMask;
5692  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5693                           ProcessorIMod, ITMask);
5694
5695  // In Thumb1, only the branch (B) instruction can be predicated.
5696  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5697    Parser.eatToEndOfStatement();
5698    return Error(NameLoc, "conditional execution not supported in Thumb1");
5699  }
5700
5701  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5702
5703  // Handle the IT instruction ITMask. Convert it to a bitmask. This
5704  // is the mask as it will be for the IT encoding if the conditional
5705  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5706  // where the conditional bit0 is zero, the instruction post-processing
5707  // will adjust the mask accordingly.
5708  if (Mnemonic == "it") {
5709    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5710    if (ITMask.size() > 3) {
5711      Parser.eatToEndOfStatement();
5712      return Error(Loc, "too many conditions on IT instruction");
5713    }
5714    unsigned Mask = 8;
5715    for (unsigned i = ITMask.size(); i != 0; --i) {
5716      char pos = ITMask[i - 1];
5717      if (pos != 't' && pos != 'e') {
5718        Parser.eatToEndOfStatement();
5719        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5720      }
5721      Mask >>= 1;
5722      if (ITMask[i - 1] == 't')
5723        Mask |= 8;
5724    }
5725    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5726  }
5727
5728  // FIXME: This is all a pretty gross hack. We should automatically handle
5729  // optional operands like this via tblgen.
5730
5731  // Next, add the CCOut and ConditionCode operands, if needed.
5732  //
5733  // For mnemonics which can ever incorporate a carry setting bit or predication
5734  // code, our matching model involves us always generating CCOut and
5735  // ConditionCode operands to match the mnemonic "as written" and then we let
5736  // the matcher deal with finding the right instruction or generating an
5737  // appropriate error.
5738  bool CanAcceptCarrySet, CanAcceptPredicationCode;
5739  getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5740
5741  // If we had a carry-set on an instruction that can't do that, issue an
5742  // error.
5743  if (!CanAcceptCarrySet && CarrySetting) {
5744    Parser.eatToEndOfStatement();
5745    return Error(NameLoc, "instruction '" + Mnemonic +
5746                 "' can not set flags, but 's' suffix specified");
5747  }
5748  // If we had a predication code on an instruction that can't do that, issue an
5749  // error.
5750  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5751    Parser.eatToEndOfStatement();
5752    return Error(NameLoc, "instruction '" + Mnemonic +
5753                 "' is not predicable, but condition code specified");
5754  }
5755
5756  // Add the carry setting operand, if necessary.
5757  if (CanAcceptCarrySet) {
5758    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5759    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5760                                               Loc));
5761  }
5762
5763  // Add the predication code operand, if necessary.
5764  if (CanAcceptPredicationCode) {
5765    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5766                                      CarrySetting);
5767    Operands.push_back(ARMOperand::CreateCondCode(
5768                         ARMCC::CondCodes(PredicationCode), Loc));
5769  }
5770
5771  // Add the processor imod operand, if necessary.
5772  if (ProcessorIMod) {
5773    Operands.push_back(ARMOperand::CreateImm(
5774          MCConstantExpr::Create(ProcessorIMod, getContext()),
5775                                 NameLoc, NameLoc));
5776  } else if (Mnemonic == "cps" && isMClass()) {
5777    return Error(NameLoc, "instruction 'cps' requires effect for M-class");
5778  }
5779
5780  // Add the remaining tokens in the mnemonic.
5781  while (Next != StringRef::npos) {
5782    Start = Next;
5783    Next = Name.find('.', Start + 1);
5784    StringRef ExtraToken = Name.slice(Start, Next);
5785
5786    // Some NEON instructions have an optional datatype suffix that is
5787    // completely ignored. Check for that.
5788    if (isDataTypeToken(ExtraToken) &&
5789        doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5790      continue;
5791
5792    // For for ARM mode generate an error if the .n qualifier is used.
5793    if (ExtraToken == ".n" && !isThumb()) {
5794      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5795      Parser.eatToEndOfStatement();
5796      return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5797                   "arm mode");
5798    }
5799
5800    // The .n qualifier is always discarded as that is what the tables
5801    // and matcher expect.  In ARM mode the .w qualifier has no effect,
5802    // so discard it to avoid errors that can be caused by the matcher.
5803    if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5804      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5805      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5806    }
5807  }
5808
5809  // Read the remaining operands.
5810  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5811    // Read the first operand.
5812    if (parseOperand(Operands, Mnemonic)) {
5813      Parser.eatToEndOfStatement();
5814      return true;
5815    }
5816
5817    while (getLexer().is(AsmToken::Comma)) {
5818      Parser.Lex();  // Eat the comma.
5819
5820      // Parse and remember the operand.
5821      if (parseOperand(Operands, Mnemonic)) {
5822        Parser.eatToEndOfStatement();
5823        return true;
5824      }
5825    }
5826  }
5827
5828  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5829    SMLoc Loc = getLexer().getLoc();
5830    Parser.eatToEndOfStatement();
5831    return Error(Loc, "unexpected token in argument list");
5832  }
5833
5834  Parser.Lex(); // Consume the EndOfStatement
5835
5836  if (RequireVFPRegisterListCheck) {
5837    ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back());
5838    if (AcceptSinglePrecisionOnly && !Op.isSPRRegList())
5839      return Error(Op.getStartLoc(),
5840                   "VFP/Neon single precision register expected");
5841    if (AcceptDoublePrecisionOnly && !Op.isDPRRegList())
5842      return Error(Op.getStartLoc(),
5843                   "VFP/Neon double precision register expected");
5844  }
5845
5846  // Some instructions, mostly Thumb, have forms for the same mnemonic that
5847  // do and don't have a cc_out optional-def operand. With some spot-checks
5848  // of the operand list, we can figure out which variant we're trying to
5849  // parse and adjust accordingly before actually matching. We shouldn't ever
5850  // try to remove a cc_out operand that was explicitly set on the the
5851  // mnemonic, of course (CarrySetting == true). Reason number #317 the
5852  // table driven matcher doesn't fit well with the ARM instruction set.
5853  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
5854    Operands.erase(Operands.begin() + 1);
5855
5856  // Some instructions have the same mnemonic, but don't always
5857  // have a predicate. Distinguish them here and delete the
5858  // predicate if needed.
5859  if (shouldOmitPredicateOperand(Mnemonic, Operands))
5860    Operands.erase(Operands.begin() + 1);
5861
5862  // ARM mode 'blx' need special handling, as the register operand version
5863  // is predicable, but the label operand version is not. So, we can't rely
5864  // on the Mnemonic based checking to correctly figure out when to put
5865  // a k_CondCode operand in the list. If we're trying to match the label
5866  // version, remove the k_CondCode operand here.
5867  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5868      static_cast<ARMOperand &>(*Operands[2]).isImm())
5869    Operands.erase(Operands.begin() + 1);
5870
5871  // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5872  // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5873  // a single GPRPair reg operand is used in the .td file to replace the two
5874  // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5875  // expressed as a GPRPair, so we have to manually merge them.
5876  // FIXME: We would really like to be able to tablegen'erate this.
5877  if (!isThumb() && Operands.size() > 4 &&
5878      (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5879       Mnemonic == "stlexd")) {
5880    bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5881    unsigned Idx = isLoad ? 2 : 3;
5882    ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
5883    ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
5884
5885    const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5886    // Adjust only if Op1 and Op2 are GPRs.
5887    if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
5888        MRC.contains(Op2.getReg())) {
5889      unsigned Reg1 = Op1.getReg();
5890      unsigned Reg2 = Op2.getReg();
5891      unsigned Rt = MRI->getEncodingValue(Reg1);
5892      unsigned Rt2 = MRI->getEncodingValue(Reg2);
5893
5894      // Rt2 must be Rt + 1 and Rt must be even.
5895      if (Rt + 1 != Rt2 || (Rt & 1)) {
5896        Error(Op2.getStartLoc(), isLoad
5897                                     ? "destination operands must be sequential"
5898                                     : "source operands must be sequential");
5899        return true;
5900      }
5901      unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5902          &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5903      Operands[Idx] =
5904          ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
5905      Operands.erase(Operands.begin() + Idx + 1);
5906    }
5907  }
5908
5909  // If first 2 operands of a 3 operand instruction are the same
5910  // then transform to 2 operand version of the same instruction
5911  // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
5912  // FIXME: We would really like to be able to tablegen'erate this.
5913  if (isThumbOne() && Operands.size() == 6 &&
5914       (Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
5915        Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5916        Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
5917        Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic")) {
5918      ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5919      ARMOperand &Op4 = static_cast<ARMOperand &>(*Operands[4]);
5920      ARMOperand &Op5 = static_cast<ARMOperand &>(*Operands[5]);
5921
5922      // If both registers are the same then remove one of them from
5923      // the operand list.
5924      if (Op3.isReg() && Op4.isReg() && Op3.getReg() == Op4.getReg()) {
5925          // If 3rd operand (variable Op5) is a register and the instruction is adds/sub
5926          // then do not transform as the backend already handles this instruction
5927          // correctly.
5928          if (!Op5.isReg() || !((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub")) {
5929              Operands.erase(Operands.begin() + 3);
5930              if (Mnemonic == "add" && !CarrySetting) {
5931                  // Special case for 'add' (not 'adds') instruction must
5932                  // remove the CCOut operand as well.
5933                  Operands.erase(Operands.begin() + 1);
5934              }
5935          }
5936      }
5937  }
5938
5939  // If instruction is 'add' and first two register operands
5940  // use SP register, then remove one of the SP registers from
5941  // the instruction.
5942  // FIXME: We would really like to be able to tablegen'erate this.
5943  if (isThumbOne() && Operands.size() == 5 && Mnemonic == "add" && !CarrySetting) {
5944      ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
5945      ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5946      if (Op2.isReg() && Op3.isReg() && Op2.getReg() == ARM::SP && Op3.getReg() == ARM::SP) {
5947          Operands.erase(Operands.begin() + 2);
5948      }
5949  }
5950
5951  // GNU Assembler extension (compatibility)
5952  if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
5953    ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
5954    ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5955    if (Op3.isMem()) {
5956      assert(Op2.isReg() && "expected register argument");
5957
5958      unsigned SuperReg = MRI->getMatchingSuperReg(
5959          Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5960
5961      assert(SuperReg && "expected register pair");
5962
5963      unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
5964
5965      Operands.insert(
5966          Operands.begin() + 3,
5967          ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
5968    }
5969  }
5970
5971  // FIXME: As said above, this is all a pretty gross hack.  This instruction
5972  // does not fit with other "subs" and tblgen.
5973  // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5974  // so the Mnemonic is the original name "subs" and delete the predicate
5975  // operand so it will match the table entry.
5976  if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5977      static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5978      static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
5979      static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5980      static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
5981      static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5982    Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
5983    Operands.erase(Operands.begin() + 1);
5984  }
5985  return false;
5986}
5987
5988// Validate context-sensitive operand constraints.
5989
5990// return 'true' if register list contains non-low GPR registers,
5991// 'false' otherwise. If Reg is in the register list or is HiReg, set
5992// 'containsReg' to true.
5993static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5994                                 unsigned HiReg, bool &containsReg) {
5995  containsReg = false;
5996  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5997    unsigned OpReg = Inst.getOperand(i).getReg();
5998    if (OpReg == Reg)
5999      containsReg = true;
6000    // Anything other than a low register isn't legal here.
6001    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
6002      return true;
6003  }
6004  return false;
6005}
6006
6007// Check if the specified regisgter is in the register list of the inst,
6008// starting at the indicated operand number.
6009static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
6010  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
6011    unsigned OpReg = Inst.getOperand(i).getReg();
6012    if (OpReg == Reg)
6013      return true;
6014  }
6015  return false;
6016}
6017
6018// Return true if instruction has the interesting property of being
6019// allowed in IT blocks, but not being predicable.
6020static bool instIsBreakpoint(const MCInst &Inst) {
6021    return Inst.getOpcode() == ARM::tBKPT ||
6022           Inst.getOpcode() == ARM::BKPT ||
6023           Inst.getOpcode() == ARM::tHLT ||
6024           Inst.getOpcode() == ARM::HLT;
6025
6026}
6027
6028bool ARMAsmParser::validatetLDMRegList(MCInst Inst,
6029                                       const OperandVector &Operands,
6030                                       unsigned ListNo, bool IsARPop) {
6031  const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
6032  bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
6033
6034  bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6035  bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
6036  bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6037
6038  if (!IsARPop && ListContainsSP)
6039    return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6040                 "SP may not be in the register list");
6041  else if (ListContainsPC && ListContainsLR)
6042    return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6043                 "PC and LR may not be in the register list simultaneously");
6044  else if (inITBlock() && !lastInITBlock() && ListContainsPC)
6045    return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6046                 "instruction must be outside of IT block or the last "
6047                 "instruction in an IT block");
6048  return false;
6049}
6050
6051bool ARMAsmParser::validatetSTMRegList(MCInst Inst,
6052                                       const OperandVector &Operands,
6053                                       unsigned ListNo) {
6054  const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
6055  bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
6056
6057  bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6058  bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6059
6060  if (ListContainsSP && ListContainsPC)
6061    return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6062                 "SP and PC may not be in the register list");
6063  else if (ListContainsSP)
6064    return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6065                 "SP may not be in the register list");
6066  else if (ListContainsPC)
6067    return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6068                 "PC may not be in the register list");
6069  return false;
6070}
6071
6072// FIXME: We would really like to be able to tablegen'erate this.
6073bool ARMAsmParser::validateInstruction(MCInst &Inst,
6074                                       const OperandVector &Operands) {
6075  const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
6076  SMLoc Loc = Operands[0]->getStartLoc();
6077
6078  // Check the IT block state first.
6079  // NOTE: BKPT and HLT instructions have the interesting property of being
6080  // allowed in IT blocks, but not being predicable. They just always execute.
6081  if (inITBlock() && !instIsBreakpoint(Inst)) {
6082    unsigned Bit = 1;
6083    if (ITState.FirstCond)
6084      ITState.FirstCond = false;
6085    else
6086      Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
6087    // The instruction must be predicable.
6088    if (!MCID.isPredicable())
6089      return Error(Loc, "instructions in IT block must be predicable");
6090    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
6091    unsigned ITCond = Bit ? ITState.Cond :
6092      ARMCC::getOppositeCondition(ITState.Cond);
6093    if (Cond != ITCond) {
6094      // Find the condition code Operand to get its SMLoc information.
6095      SMLoc CondLoc;
6096      for (unsigned I = 1; I < Operands.size(); ++I)
6097        if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
6098          CondLoc = Operands[I]->getStartLoc();
6099      return Error(CondLoc, "incorrect condition in IT block; got '" +
6100                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
6101                   "', but expected '" +
6102                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
6103    }
6104  // Check for non-'al' condition codes outside of the IT block.
6105  } else if (isThumbTwo() && MCID.isPredicable() &&
6106             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
6107             ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
6108             Inst.getOpcode() != ARM::t2Bcc)
6109    return Error(Loc, "predicated instructions must be in IT block");
6110
6111  const unsigned Opcode = Inst.getOpcode();
6112  switch (Opcode) {
6113  case ARM::LDRD:
6114  case ARM::LDRD_PRE:
6115  case ARM::LDRD_POST: {
6116    const unsigned RtReg = Inst.getOperand(0).getReg();
6117
6118    // Rt can't be R14.
6119    if (RtReg == ARM::LR)
6120      return Error(Operands[3]->getStartLoc(),
6121                   "Rt can't be R14");
6122
6123    const unsigned Rt = MRI->getEncodingValue(RtReg);
6124    // Rt must be even-numbered.
6125    if ((Rt & 1) == 1)
6126      return Error(Operands[3]->getStartLoc(),
6127                   "Rt must be even-numbered");
6128
6129    // Rt2 must be Rt + 1.
6130    const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6131    if (Rt2 != Rt + 1)
6132      return Error(Operands[3]->getStartLoc(),
6133                   "destination operands must be sequential");
6134
6135    if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
6136      const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
6137      // For addressing modes with writeback, the base register needs to be
6138      // different from the destination registers.
6139      if (Rn == Rt || Rn == Rt2)
6140        return Error(Operands[3]->getStartLoc(),
6141                     "base register needs to be different from destination "
6142                     "registers");
6143    }
6144
6145    return false;
6146  }
6147  case ARM::t2LDRDi8:
6148  case ARM::t2LDRD_PRE:
6149  case ARM::t2LDRD_POST: {
6150    // Rt2 must be different from Rt.
6151    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6152    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6153    if (Rt2 == Rt)
6154      return Error(Operands[3]->getStartLoc(),
6155                   "destination operands can't be identical");
6156    return false;
6157  }
6158  case ARM::STRD: {
6159    // Rt2 must be Rt + 1.
6160    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6161    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6162    if (Rt2 != Rt + 1)
6163      return Error(Operands[3]->getStartLoc(),
6164                   "source operands must be sequential");
6165    return false;
6166  }
6167  case ARM::STRD_PRE:
6168  case ARM::STRD_POST: {
6169    // Rt2 must be Rt + 1.
6170    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6171    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6172    if (Rt2 != Rt + 1)
6173      return Error(Operands[3]->getStartLoc(),
6174                   "source operands must be sequential");
6175    return false;
6176  }
6177  case ARM::STR_PRE_IMM:
6178  case ARM::STR_PRE_REG:
6179  case ARM::STR_POST_IMM:
6180  case ARM::STR_POST_REG:
6181  case ARM::STRH_PRE:
6182  case ARM::STRH_POST:
6183  case ARM::STRB_PRE_IMM:
6184  case ARM::STRB_PRE_REG:
6185  case ARM::STRB_POST_IMM:
6186  case ARM::STRB_POST_REG: {
6187    // Rt must be different from Rn.
6188    const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6189    const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6190
6191    if (Rt == Rn)
6192      return Error(Operands[3]->getStartLoc(),
6193                   "source register and base register can't be identical");
6194    return false;
6195  }
6196  case ARM::LDR_PRE_IMM:
6197  case ARM::LDR_PRE_REG:
6198  case ARM::LDR_POST_IMM:
6199  case ARM::LDR_POST_REG:
6200  case ARM::LDRH_PRE:
6201  case ARM::LDRH_POST:
6202  case ARM::LDRSH_PRE:
6203  case ARM::LDRSH_POST:
6204  case ARM::LDRB_PRE_IMM:
6205  case ARM::LDRB_PRE_REG:
6206  case ARM::LDRB_POST_IMM:
6207  case ARM::LDRB_POST_REG:
6208  case ARM::LDRSB_PRE:
6209  case ARM::LDRSB_POST: {
6210    // Rt must be different from Rn.
6211    const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6212    const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6213
6214    if (Rt == Rn)
6215      return Error(Operands[3]->getStartLoc(),
6216                   "destination register and base register can't be identical");
6217    return false;
6218  }
6219  case ARM::SBFX:
6220  case ARM::UBFX: {
6221    // Width must be in range [1, 32-lsb].
6222    unsigned LSB = Inst.getOperand(2).getImm();
6223    unsigned Widthm1 = Inst.getOperand(3).getImm();
6224    if (Widthm1 >= 32 - LSB)
6225      return Error(Operands[5]->getStartLoc(),
6226                   "bitfield width must be in range [1,32-lsb]");
6227    return false;
6228  }
6229  // Notionally handles ARM::tLDMIA_UPD too.
6230  case ARM::tLDMIA: {
6231    // If we're parsing Thumb2, the .w variant is available and handles
6232    // most cases that are normally illegal for a Thumb1 LDM instruction.
6233    // We'll make the transformation in processInstruction() if necessary.
6234    //
6235    // Thumb LDM instructions are writeback iff the base register is not
6236    // in the register list.
6237    unsigned Rn = Inst.getOperand(0).getReg();
6238    bool HasWritebackToken =
6239        (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
6240         static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
6241    bool ListContainsBase;
6242    if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
6243      return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
6244                   "registers must be in range r0-r7");
6245    // If we should have writeback, then there should be a '!' token.
6246    if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
6247      return Error(Operands[2]->getStartLoc(),
6248                   "writeback operator '!' expected");
6249    // If we should not have writeback, there must not be a '!'. This is
6250    // true even for the 32-bit wide encodings.
6251    if (ListContainsBase && HasWritebackToken)
6252      return Error(Operands[3]->getStartLoc(),
6253                   "writeback operator '!' not allowed when base register "
6254                   "in register list");
6255
6256    if (validatetLDMRegList(Inst, Operands, 3))
6257      return true;
6258    break;
6259  }
6260  case ARM::LDMIA_UPD:
6261  case ARM::LDMDB_UPD:
6262  case ARM::LDMIB_UPD:
6263  case ARM::LDMDA_UPD:
6264    // ARM variants loading and updating the same register are only officially
6265    // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
6266    if (!hasV7Ops())
6267      break;
6268    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6269      return Error(Operands.back()->getStartLoc(),
6270                   "writeback register not allowed in register list");
6271    break;
6272  case ARM::t2LDMIA:
6273  case ARM::t2LDMDB:
6274    if (validatetLDMRegList(Inst, Operands, 3))
6275      return true;
6276    break;
6277  case ARM::t2STMIA:
6278  case ARM::t2STMDB:
6279    if (validatetSTMRegList(Inst, Operands, 3))
6280      return true;
6281    break;
6282  case ARM::t2LDMIA_UPD:
6283  case ARM::t2LDMDB_UPD:
6284  case ARM::t2STMIA_UPD:
6285  case ARM::t2STMDB_UPD: {
6286    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6287      return Error(Operands.back()->getStartLoc(),
6288                   "writeback register not allowed in register list");
6289
6290    if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
6291      if (validatetLDMRegList(Inst, Operands, 3))
6292        return true;
6293    } else {
6294      if (validatetSTMRegList(Inst, Operands, 3))
6295        return true;
6296    }
6297    break;
6298  }
6299  case ARM::sysLDMIA_UPD:
6300  case ARM::sysLDMDA_UPD:
6301  case ARM::sysLDMDB_UPD:
6302  case ARM::sysLDMIB_UPD:
6303    if (!listContainsReg(Inst, 3, ARM::PC))
6304      return Error(Operands[4]->getStartLoc(),
6305                   "writeback register only allowed on system LDM "
6306                   "if PC in register-list");
6307    break;
6308  case ARM::sysSTMIA_UPD:
6309  case ARM::sysSTMDA_UPD:
6310  case ARM::sysSTMDB_UPD:
6311  case ARM::sysSTMIB_UPD:
6312    return Error(Operands[2]->getStartLoc(),
6313                 "system STM cannot have writeback register");
6314  case ARM::tMUL: {
6315    // The second source operand must be the same register as the destination
6316    // operand.
6317    //
6318    // In this case, we must directly check the parsed operands because the
6319    // cvtThumbMultiply() function is written in such a way that it guarantees
6320    // this first statement is always true for the new Inst.  Essentially, the
6321    // destination is unconditionally copied into the second source operand
6322    // without checking to see if it matches what we actually parsed.
6323    if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
6324                                 ((ARMOperand &)*Operands[5]).getReg()) &&
6325        (((ARMOperand &)*Operands[3]).getReg() !=
6326         ((ARMOperand &)*Operands[4]).getReg())) {
6327      return Error(Operands[3]->getStartLoc(),
6328                   "destination register must match source register");
6329    }
6330    break;
6331  }
6332  // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
6333  // so only issue a diagnostic for thumb1. The instructions will be
6334  // switched to the t2 encodings in processInstruction() if necessary.
6335  case ARM::tPOP: {
6336    bool ListContainsBase;
6337    if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
6338        !isThumbTwo())
6339      return Error(Operands[2]->getStartLoc(),
6340                   "registers must be in range r0-r7 or pc");
6341    if (validatetLDMRegList(Inst, Operands, 2, !isMClass()))
6342      return true;
6343    break;
6344  }
6345  case ARM::tPUSH: {
6346    bool ListContainsBase;
6347    if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
6348        !isThumbTwo())
6349      return Error(Operands[2]->getStartLoc(),
6350                   "registers must be in range r0-r7 or lr");
6351    if (validatetSTMRegList(Inst, Operands, 2))
6352      return true;
6353    break;
6354  }
6355  case ARM::tSTMIA_UPD: {
6356    bool ListContainsBase, InvalidLowList;
6357    InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
6358                                          0, ListContainsBase);
6359    if (InvalidLowList && !isThumbTwo())
6360      return Error(Operands[4]->getStartLoc(),
6361                   "registers must be in range r0-r7");
6362
6363    // This would be converted to a 32-bit stm, but that's not valid if the
6364    // writeback register is in the list.
6365    if (InvalidLowList && ListContainsBase)
6366      return Error(Operands[4]->getStartLoc(),
6367                   "writeback operator '!' not allowed when base register "
6368                   "in register list");
6369
6370    if (validatetSTMRegList(Inst, Operands, 4))
6371      return true;
6372    break;
6373  }
6374  case ARM::tADDrSP: {
6375    // If the non-SP source operand and the destination operand are not the
6376    // same, we need thumb2 (for the wide encoding), or we have an error.
6377    if (!isThumbTwo() &&
6378        Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
6379      return Error(Operands[4]->getStartLoc(),
6380                   "source register must be the same as destination");
6381    }
6382    break;
6383  }
6384  // Final range checking for Thumb unconditional branch instructions.
6385  case ARM::tB:
6386    if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
6387      return Error(Operands[2]->getStartLoc(), "branch target out of range");
6388    break;
6389  case ARM::t2B: {
6390    int op = (Operands[2]->isImm()) ? 2 : 3;
6391    if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
6392      return Error(Operands[op]->getStartLoc(), "branch target out of range");
6393    break;
6394  }
6395  // Final range checking for Thumb conditional branch instructions.
6396  case ARM::tBcc:
6397    if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
6398      return Error(Operands[2]->getStartLoc(), "branch target out of range");
6399    break;
6400  case ARM::t2Bcc: {
6401    int Op = (Operands[2]->isImm()) ? 2 : 3;
6402    if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
6403      return Error(Operands[Op]->getStartLoc(), "branch target out of range");
6404    break;
6405  }
6406  case ARM::MOVi16:
6407  case ARM::t2MOVi16:
6408  case ARM::t2MOVTi16:
6409    {
6410    // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
6411    // especially when we turn it into a movw and the expression <symbol> does
6412    // not have a :lower16: or :upper16 as part of the expression.  We don't
6413    // want the behavior of silently truncating, which can be unexpected and
6414    // lead to bugs that are difficult to find since this is an easy mistake
6415    // to make.
6416    int i = (Operands[3]->isImm()) ? 3 : 4;
6417    ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
6418    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
6419    if (CE) break;
6420    const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
6421    if (!E) break;
6422    const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
6423    if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
6424                       ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
6425      return Error(
6426          Op.getStartLoc(),
6427          "immediate expression for mov requires :lower16: or :upper16");
6428    break;
6429  }
6430  }
6431
6432  return false;
6433}
6434
6435static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
6436  switch(Opc) {
6437  default: llvm_unreachable("unexpected opcode!");
6438  // VST1LN
6439  case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
6440  case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6441  case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6442  case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
6443  case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6444  case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6445  case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
6446  case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
6447  case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
6448
6449  // VST2LN
6450  case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
6451  case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6452  case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6453  case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6454  case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6455
6456  case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
6457  case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6458  case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6459  case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6460  case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6461
6462  case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
6463  case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
6464  case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
6465  case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
6466  case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
6467
6468  // VST3LN
6469  case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
6470  case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6471  case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6472  case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
6473  case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6474  case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
6475  case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6476  case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6477  case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
6478  case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6479  case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
6480  case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
6481  case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
6482  case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
6483  case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
6484
6485  // VST3
6486  case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
6487  case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6488  case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6489  case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
6490  case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6491  case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6492  case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
6493  case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6494  case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6495  case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
6496  case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6497  case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6498  case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
6499  case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
6500  case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
6501  case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
6502  case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
6503  case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
6504
6505  // VST4LN
6506  case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
6507  case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6508  case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6509  case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
6510  case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6511  case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
6512  case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6513  case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6514  case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
6515  case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6516  case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
6517  case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
6518  case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
6519  case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
6520  case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
6521
6522  // VST4
6523  case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
6524  case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6525  case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6526  case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
6527  case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6528  case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6529  case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
6530  case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6531  case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6532  case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
6533  case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6534  case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6535  case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
6536  case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
6537  case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
6538  case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
6539  case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
6540  case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6541  }
6542}
6543
6544static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6545  switch(Opc) {
6546  default: llvm_unreachable("unexpected opcode!");
6547  // VLD1LN
6548  case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
6549  case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6550  case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6551  case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
6552  case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6553  case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6554  case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
6555  case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6556  case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6557
6558  // VLD2LN
6559  case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
6560  case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6561  case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6562  case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6563  case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6564  case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
6565  case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6566  case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6567  case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6568  case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6569  case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
6570  case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6571  case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6572  case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6573  case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6574
6575  // VLD3DUP
6576  case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
6577  case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6578  case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6579  case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6580  case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6581  case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6582  case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
6583  case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6584  case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6585  case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6586  case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6587  case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6588  case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
6589  case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
6590  case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
6591  case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
6592  case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
6593  case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
6594
6595  // VLD3LN
6596  case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
6597  case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6598  case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6599  case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
6600  case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6601  case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
6602  case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6603  case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6604  case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
6605  case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6606  case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
6607  case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
6608  case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
6609  case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
6610  case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
6611
6612  // VLD3
6613  case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
6614  case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6615  case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6616  case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
6617  case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6618  case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6619  case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
6620  case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6621  case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6622  case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
6623  case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6624  case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6625  case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
6626  case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6627  case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6628  case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
6629  case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6630  case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6631
6632  // VLD4LN
6633  case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
6634  case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6635  case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6636  case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6637  case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6638  case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
6639  case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6640  case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6641  case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6642  case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6643  case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
6644  case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6645  case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6646  case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6647  case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6648
6649  // VLD4DUP
6650  case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
6651  case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6652  case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6653  case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6654  case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6655  case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6656  case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
6657  case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6658  case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6659  case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6660  case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6661  case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6662  case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
6663  case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6664  case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6665  case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6666  case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6667  case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6668
6669  // VLD4
6670  case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
6671  case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6672  case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6673  case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
6674  case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6675  case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6676  case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
6677  case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6678  case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6679  case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
6680  case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6681  case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6682  case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
6683  case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6684  case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6685  case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
6686  case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6687  case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6688  }
6689}
6690
6691bool ARMAsmParser::processInstruction(MCInst &Inst,
6692                                      const OperandVector &Operands,
6693                                      MCStreamer &Out) {
6694  switch (Inst.getOpcode()) {
6695  // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6696  case ARM::LDRT_POST:
6697  case ARM::LDRBT_POST: {
6698    const unsigned Opcode =
6699      (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6700                                           : ARM::LDRBT_POST_IMM;
6701    MCInst TmpInst;
6702    TmpInst.setOpcode(Opcode);
6703    TmpInst.addOperand(Inst.getOperand(0));
6704    TmpInst.addOperand(Inst.getOperand(1));
6705    TmpInst.addOperand(Inst.getOperand(1));
6706    TmpInst.addOperand(MCOperand::CreateReg(0));
6707    TmpInst.addOperand(MCOperand::CreateImm(0));
6708    TmpInst.addOperand(Inst.getOperand(2));
6709    TmpInst.addOperand(Inst.getOperand(3));
6710    Inst = TmpInst;
6711    return true;
6712  }
6713  // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6714  case ARM::STRT_POST:
6715  case ARM::STRBT_POST: {
6716    const unsigned Opcode =
6717      (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6718                                           : ARM::STRBT_POST_IMM;
6719    MCInst TmpInst;
6720    TmpInst.setOpcode(Opcode);
6721    TmpInst.addOperand(Inst.getOperand(1));
6722    TmpInst.addOperand(Inst.getOperand(0));
6723    TmpInst.addOperand(Inst.getOperand(1));
6724    TmpInst.addOperand(MCOperand::CreateReg(0));
6725    TmpInst.addOperand(MCOperand::CreateImm(0));
6726    TmpInst.addOperand(Inst.getOperand(2));
6727    TmpInst.addOperand(Inst.getOperand(3));
6728    Inst = TmpInst;
6729    return true;
6730  }
6731  // Alias for alternate form of 'ADR Rd, #imm' instruction.
6732  case ARM::ADDri: {
6733    if (Inst.getOperand(1).getReg() != ARM::PC ||
6734        Inst.getOperand(5).getReg() != 0 ||
6735        !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
6736      return false;
6737    MCInst TmpInst;
6738    TmpInst.setOpcode(ARM::ADR);
6739    TmpInst.addOperand(Inst.getOperand(0));
6740    if (Inst.getOperand(2).isImm()) {
6741      // Immediate (mod_imm) will be in its encoded form, we must unencode it
6742      // before passing it to the ADR instruction.
6743      unsigned Enc = Inst.getOperand(2).getImm();
6744      TmpInst.addOperand(MCOperand::CreateImm(
6745        ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
6746    } else {
6747      // Turn PC-relative expression into absolute expression.
6748      // Reading PC provides the start of the current instruction + 8 and
6749      // the transform to adr is biased by that.
6750      MCSymbol *Dot = getContext().CreateTempSymbol();
6751      Out.EmitLabel(Dot);
6752      const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
6753      const MCExpr *InstPC = MCSymbolRefExpr::Create(Dot,
6754                                                     MCSymbolRefExpr::VK_None,
6755                                                     getContext());
6756      const MCExpr *Const8 = MCConstantExpr::Create(8, getContext());
6757      const MCExpr *ReadPC = MCBinaryExpr::CreateAdd(InstPC, Const8,
6758                                                     getContext());
6759      const MCExpr *FixupAddr = MCBinaryExpr::CreateAdd(ReadPC, OpExpr,
6760                                                        getContext());
6761      TmpInst.addOperand(MCOperand::CreateExpr(FixupAddr));
6762    }
6763    TmpInst.addOperand(Inst.getOperand(3));
6764    TmpInst.addOperand(Inst.getOperand(4));
6765    Inst = TmpInst;
6766    return true;
6767  }
6768  // Aliases for alternate PC+imm syntax of LDR instructions.
6769  case ARM::t2LDRpcrel:
6770    // Select the narrow version if the immediate will fit.
6771    if (Inst.getOperand(1).getImm() > 0 &&
6772        Inst.getOperand(1).getImm() <= 0xff &&
6773        !(static_cast<ARMOperand &>(*Operands[2]).isToken() &&
6774          static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w"))
6775      Inst.setOpcode(ARM::tLDRpci);
6776    else
6777      Inst.setOpcode(ARM::t2LDRpci);
6778    return true;
6779  case ARM::t2LDRBpcrel:
6780    Inst.setOpcode(ARM::t2LDRBpci);
6781    return true;
6782  case ARM::t2LDRHpcrel:
6783    Inst.setOpcode(ARM::t2LDRHpci);
6784    return true;
6785  case ARM::t2LDRSBpcrel:
6786    Inst.setOpcode(ARM::t2LDRSBpci);
6787    return true;
6788  case ARM::t2LDRSHpcrel:
6789    Inst.setOpcode(ARM::t2LDRSHpci);
6790    return true;
6791  // Handle NEON VST complex aliases.
6792  case ARM::VST1LNdWB_register_Asm_8:
6793  case ARM::VST1LNdWB_register_Asm_16:
6794  case ARM::VST1LNdWB_register_Asm_32: {
6795    MCInst TmpInst;
6796    // Shuffle the operands around so the lane index operand is in the
6797    // right place.
6798    unsigned Spacing;
6799    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6800    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6801    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6802    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6803    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6804    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6805    TmpInst.addOperand(Inst.getOperand(1)); // lane
6806    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6807    TmpInst.addOperand(Inst.getOperand(6));
6808    Inst = TmpInst;
6809    return true;
6810  }
6811
6812  case ARM::VST2LNdWB_register_Asm_8:
6813  case ARM::VST2LNdWB_register_Asm_16:
6814  case ARM::VST2LNdWB_register_Asm_32:
6815  case ARM::VST2LNqWB_register_Asm_16:
6816  case ARM::VST2LNqWB_register_Asm_32: {
6817    MCInst TmpInst;
6818    // Shuffle the operands around so the lane index operand is in the
6819    // right place.
6820    unsigned Spacing;
6821    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6822    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6823    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6824    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6825    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6826    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6827    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6828                                            Spacing));
6829    TmpInst.addOperand(Inst.getOperand(1)); // lane
6830    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6831    TmpInst.addOperand(Inst.getOperand(6));
6832    Inst = TmpInst;
6833    return true;
6834  }
6835
6836  case ARM::VST3LNdWB_register_Asm_8:
6837  case ARM::VST3LNdWB_register_Asm_16:
6838  case ARM::VST3LNdWB_register_Asm_32:
6839  case ARM::VST3LNqWB_register_Asm_16:
6840  case ARM::VST3LNqWB_register_Asm_32: {
6841    MCInst TmpInst;
6842    // Shuffle the operands around so the lane index operand is in the
6843    // right place.
6844    unsigned Spacing;
6845    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6846    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6847    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6848    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6849    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6850    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6851    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6852                                            Spacing));
6853    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6854                                            Spacing * 2));
6855    TmpInst.addOperand(Inst.getOperand(1)); // lane
6856    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6857    TmpInst.addOperand(Inst.getOperand(6));
6858    Inst = TmpInst;
6859    return true;
6860  }
6861
6862  case ARM::VST4LNdWB_register_Asm_8:
6863  case ARM::VST4LNdWB_register_Asm_16:
6864  case ARM::VST4LNdWB_register_Asm_32:
6865  case ARM::VST4LNqWB_register_Asm_16:
6866  case ARM::VST4LNqWB_register_Asm_32: {
6867    MCInst TmpInst;
6868    // Shuffle the operands around so the lane index operand is in the
6869    // right place.
6870    unsigned Spacing;
6871    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6872    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6873    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6874    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6875    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6876    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6877    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6878                                            Spacing));
6879    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6880                                            Spacing * 2));
6881    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6882                                            Spacing * 3));
6883    TmpInst.addOperand(Inst.getOperand(1)); // lane
6884    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6885    TmpInst.addOperand(Inst.getOperand(6));
6886    Inst = TmpInst;
6887    return true;
6888  }
6889
6890  case ARM::VST1LNdWB_fixed_Asm_8:
6891  case ARM::VST1LNdWB_fixed_Asm_16:
6892  case ARM::VST1LNdWB_fixed_Asm_32: {
6893    MCInst TmpInst;
6894    // Shuffle the operands around so the lane index operand is in the
6895    // right place.
6896    unsigned Spacing;
6897    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6898    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6899    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6900    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6901    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6902    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6903    TmpInst.addOperand(Inst.getOperand(1)); // lane
6904    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6905    TmpInst.addOperand(Inst.getOperand(5));
6906    Inst = TmpInst;
6907    return true;
6908  }
6909
6910  case ARM::VST2LNdWB_fixed_Asm_8:
6911  case ARM::VST2LNdWB_fixed_Asm_16:
6912  case ARM::VST2LNdWB_fixed_Asm_32:
6913  case ARM::VST2LNqWB_fixed_Asm_16:
6914  case ARM::VST2LNqWB_fixed_Asm_32: {
6915    MCInst TmpInst;
6916    // Shuffle the operands around so the lane index operand is in the
6917    // right place.
6918    unsigned Spacing;
6919    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6920    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6921    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6922    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6923    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6924    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6925    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6926                                            Spacing));
6927    TmpInst.addOperand(Inst.getOperand(1)); // lane
6928    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6929    TmpInst.addOperand(Inst.getOperand(5));
6930    Inst = TmpInst;
6931    return true;
6932  }
6933
6934  case ARM::VST3LNdWB_fixed_Asm_8:
6935  case ARM::VST3LNdWB_fixed_Asm_16:
6936  case ARM::VST3LNdWB_fixed_Asm_32:
6937  case ARM::VST3LNqWB_fixed_Asm_16:
6938  case ARM::VST3LNqWB_fixed_Asm_32: {
6939    MCInst TmpInst;
6940    // Shuffle the operands around so the lane index operand is in the
6941    // right place.
6942    unsigned Spacing;
6943    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6944    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6945    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6946    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6947    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6948    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6949    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6950                                            Spacing));
6951    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6952                                            Spacing * 2));
6953    TmpInst.addOperand(Inst.getOperand(1)); // lane
6954    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6955    TmpInst.addOperand(Inst.getOperand(5));
6956    Inst = TmpInst;
6957    return true;
6958  }
6959
6960  case ARM::VST4LNdWB_fixed_Asm_8:
6961  case ARM::VST4LNdWB_fixed_Asm_16:
6962  case ARM::VST4LNdWB_fixed_Asm_32:
6963  case ARM::VST4LNqWB_fixed_Asm_16:
6964  case ARM::VST4LNqWB_fixed_Asm_32: {
6965    MCInst TmpInst;
6966    // Shuffle the operands around so the lane index operand is in the
6967    // right place.
6968    unsigned Spacing;
6969    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6970    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6971    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6972    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6973    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6974    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6975    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6976                                            Spacing));
6977    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6978                                            Spacing * 2));
6979    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6980                                            Spacing * 3));
6981    TmpInst.addOperand(Inst.getOperand(1)); // lane
6982    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6983    TmpInst.addOperand(Inst.getOperand(5));
6984    Inst = TmpInst;
6985    return true;
6986  }
6987
6988  case ARM::VST1LNdAsm_8:
6989  case ARM::VST1LNdAsm_16:
6990  case ARM::VST1LNdAsm_32: {
6991    MCInst TmpInst;
6992    // Shuffle the operands around so the lane index operand is in the
6993    // right place.
6994    unsigned Spacing;
6995    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6996    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6997    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6998    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6999    TmpInst.addOperand(Inst.getOperand(1)); // lane
7000    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7001    TmpInst.addOperand(Inst.getOperand(5));
7002    Inst = TmpInst;
7003    return true;
7004  }
7005
7006  case ARM::VST2LNdAsm_8:
7007  case ARM::VST2LNdAsm_16:
7008  case ARM::VST2LNdAsm_32:
7009  case ARM::VST2LNqAsm_16:
7010  case ARM::VST2LNqAsm_32: {
7011    MCInst TmpInst;
7012    // Shuffle the operands around so the lane index operand is in the
7013    // right place.
7014    unsigned Spacing;
7015    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7016    TmpInst.addOperand(Inst.getOperand(2)); // Rn
7017    TmpInst.addOperand(Inst.getOperand(3)); // alignment
7018    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7019    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7020                                            Spacing));
7021    TmpInst.addOperand(Inst.getOperand(1)); // lane
7022    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7023    TmpInst.addOperand(Inst.getOperand(5));
7024    Inst = TmpInst;
7025    return true;
7026  }
7027
7028  case ARM::VST3LNdAsm_8:
7029  case ARM::VST3LNdAsm_16:
7030  case ARM::VST3LNdAsm_32:
7031  case ARM::VST3LNqAsm_16:
7032  case ARM::VST3LNqAsm_32: {
7033    MCInst TmpInst;
7034    // Shuffle the operands around so the lane index operand is in the
7035    // right place.
7036    unsigned Spacing;
7037    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7038    TmpInst.addOperand(Inst.getOperand(2)); // Rn
7039    TmpInst.addOperand(Inst.getOperand(3)); // alignment
7040    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7041    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7042                                            Spacing));
7043    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7044                                            Spacing * 2));
7045    TmpInst.addOperand(Inst.getOperand(1)); // lane
7046    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7047    TmpInst.addOperand(Inst.getOperand(5));
7048    Inst = TmpInst;
7049    return true;
7050  }
7051
7052  case ARM::VST4LNdAsm_8:
7053  case ARM::VST4LNdAsm_16:
7054  case ARM::VST4LNdAsm_32:
7055  case ARM::VST4LNqAsm_16:
7056  case ARM::VST4LNqAsm_32: {
7057    MCInst TmpInst;
7058    // Shuffle the operands around so the lane index operand is in the
7059    // right place.
7060    unsigned Spacing;
7061    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7062    TmpInst.addOperand(Inst.getOperand(2)); // Rn
7063    TmpInst.addOperand(Inst.getOperand(3)); // alignment
7064    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7065    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7066                                            Spacing));
7067    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7068                                            Spacing * 2));
7069    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7070                                            Spacing * 3));
7071    TmpInst.addOperand(Inst.getOperand(1)); // lane
7072    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7073    TmpInst.addOperand(Inst.getOperand(5));
7074    Inst = TmpInst;
7075    return true;
7076  }
7077
7078  // Handle NEON VLD complex aliases.
7079  case ARM::VLD1LNdWB_register_Asm_8:
7080  case ARM::VLD1LNdWB_register_Asm_16:
7081  case ARM::VLD1LNdWB_register_Asm_32: {
7082    MCInst TmpInst;
7083    // Shuffle the operands around so the lane index operand is in the
7084    // right place.
7085    unsigned Spacing;
7086    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7087    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7088    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7089    TmpInst.addOperand(Inst.getOperand(2)); // Rn
7090    TmpInst.addOperand(Inst.getOperand(3)); // alignment
7091    TmpInst.addOperand(Inst.getOperand(4)); // Rm
7092    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7093    TmpInst.addOperand(Inst.getOperand(1)); // lane
7094    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7095    TmpInst.addOperand(Inst.getOperand(6));
7096    Inst = TmpInst;
7097    return true;
7098  }
7099
7100  case ARM::VLD2LNdWB_register_Asm_8:
7101  case ARM::VLD2LNdWB_register_Asm_16:
7102  case ARM::VLD2LNdWB_register_Asm_32:
7103  case ARM::VLD2LNqWB_register_Asm_16:
7104  case ARM::VLD2LNqWB_register_Asm_32: {
7105    MCInst TmpInst;
7106    // Shuffle the operands around so the lane index operand is in the
7107    // right place.
7108    unsigned Spacing;
7109    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7110    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7111    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7112                                            Spacing));
7113    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7114    TmpInst.addOperand(Inst.getOperand(2)); // Rn
7115    TmpInst.addOperand(Inst.getOperand(3)); // alignment
7116    TmpInst.addOperand(Inst.getOperand(4)); // Rm
7117    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7118    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7119                                            Spacing));
7120    TmpInst.addOperand(Inst.getOperand(1)); // lane
7121    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7122    TmpInst.addOperand(Inst.getOperand(6));
7123    Inst = TmpInst;
7124    return true;
7125  }
7126
7127  case ARM::VLD3LNdWB_register_Asm_8:
7128  case ARM::VLD3LNdWB_register_Asm_16:
7129  case ARM::VLD3LNdWB_register_Asm_32:
7130  case ARM::VLD3LNqWB_register_Asm_16:
7131  case ARM::VLD3LNqWB_register_Asm_32: {
7132    MCInst TmpInst;
7133    // Shuffle the operands around so the lane index operand is in the
7134    // right place.
7135    unsigned Spacing;
7136    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7137    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7138    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7139                                            Spacing));
7140    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7141                                            Spacing * 2));
7142    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7143    TmpInst.addOperand(Inst.getOperand(2)); // Rn
7144    TmpInst.addOperand(Inst.getOperand(3)); // alignment
7145    TmpInst.addOperand(Inst.getOperand(4)); // Rm
7146    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7147    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7148                                            Spacing));
7149    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7150                                            Spacing * 2));
7151    TmpInst.addOperand(Inst.getOperand(1)); // lane
7152    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7153    TmpInst.addOperand(Inst.getOperand(6));
7154    Inst = TmpInst;
7155    return true;
7156  }
7157
7158  case ARM::VLD4LNdWB_register_Asm_8:
7159  case ARM::VLD4LNdWB_register_Asm_16:
7160  case ARM::VLD4LNdWB_register_Asm_32:
7161  case ARM::VLD4LNqWB_register_Asm_16:
7162  case ARM::VLD4LNqWB_register_Asm_32: {
7163    MCInst TmpInst;
7164    // Shuffle the operands around so the lane index operand is in the
7165    // right place.
7166    unsigned Spacing;
7167    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7168    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7169    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7170                                            Spacing));
7171    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7172                                            Spacing * 2));
7173    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7174                                            Spacing * 3));
7175    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7176    TmpInst.addOperand(Inst.getOperand(2)); // Rn
7177    TmpInst.addOperand(Inst.getOperand(3)); // alignment
7178    TmpInst.addOperand(Inst.getOperand(4)); // Rm
7179    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7180    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7181                                            Spacing));
7182    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7183                                            Spacing * 2));
7184    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7185                                            Spacing * 3));
7186    TmpInst.addOperand(Inst.getOperand(1)); // lane
7187    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7188    TmpInst.addOperand(Inst.getOperand(6));
7189    Inst = TmpInst;
7190    return true;
7191  }
7192
7193  case ARM::VLD1LNdWB_fixed_Asm_8:
7194  case ARM::VLD1LNdWB_fixed_Asm_16:
7195  case ARM::VLD1LNdWB_fixed_Asm_32: {
7196    MCInst TmpInst;
7197    // Shuffle the operands around so the lane index operand is in the
7198    // right place.
7199    unsigned Spacing;
7200    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7201    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7202    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7203    TmpInst.addOperand(Inst.getOperand(2)); // Rn
7204    TmpInst.addOperand(Inst.getOperand(3)); // alignment
7205    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7206    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7207    TmpInst.addOperand(Inst.getOperand(1)); // lane
7208    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7209    TmpInst.addOperand(Inst.getOperand(5));
7210    Inst = TmpInst;
7211    return true;
7212  }
7213
7214  case ARM::VLD2LNdWB_fixed_Asm_8:
7215  case ARM::VLD2LNdWB_fixed_Asm_16:
7216  case ARM::VLD2LNdWB_fixed_Asm_32:
7217  case ARM::VLD2LNqWB_fixed_Asm_16:
7218  case ARM::VLD2LNqWB_fixed_Asm_32: {
7219    MCInst TmpInst;
7220    // Shuffle the operands around so the lane index operand is in the
7221    // right place.
7222    unsigned Spacing;
7223    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7224    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7225    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7226                                            Spacing));
7227    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7228    TmpInst.addOperand(Inst.getOperand(2)); // Rn
7229    TmpInst.addOperand(Inst.getOperand(3)); // alignment
7230    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7231    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7232    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7233                                            Spacing));
7234    TmpInst.addOperand(Inst.getOperand(1)); // lane
7235    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7236    TmpInst.addOperand(Inst.getOperand(5));
7237    Inst = TmpInst;
7238    return true;
7239  }
7240
7241  case ARM::VLD3LNdWB_fixed_Asm_8:
7242  case ARM::VLD3LNdWB_fixed_Asm_16:
7243  case ARM::VLD3LNdWB_fixed_Asm_32:
7244  case ARM::VLD3LNqWB_fixed_Asm_16:
7245  case ARM::VLD3LNqWB_fixed_Asm_32: {
7246    MCInst TmpInst;
7247    // Shuffle the operands around so the lane index operand is in the
7248    // right place.
7249    unsigned Spacing;
7250    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7251    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7252    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7253                                            Spacing));
7254    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7255                                            Spacing * 2));
7256    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7257    TmpInst.addOperand(Inst.getOperand(2)); // Rn
7258    TmpInst.addOperand(Inst.getOperand(3)); // alignment
7259    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7260    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7261    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7262                                            Spacing));
7263    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7264                                            Spacing * 2));
7265    TmpInst.addOperand(Inst.getOperand(1)); // lane
7266    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7267    TmpInst.addOperand(Inst.getOperand(5));
7268    Inst = TmpInst;
7269    return true;
7270  }
7271
7272  case ARM::VLD4LNdWB_fixed_Asm_8:
7273  case ARM::VLD4LNdWB_fixed_Asm_16:
7274  case ARM::VLD4LNdWB_fixed_Asm_32:
7275  case ARM::VLD4LNqWB_fixed_Asm_16:
7276  case ARM::VLD4LNqWB_fixed_Asm_32: {
7277    MCInst TmpInst;
7278    // Shuffle the operands around so the lane index operand is in the
7279    // right place.
7280    unsigned Spacing;
7281    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7282    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7283    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7284                                            Spacing));
7285    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7286                                            Spacing * 2));
7287    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7288                                            Spacing * 3));
7289    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7290    TmpInst.addOperand(Inst.getOperand(2)); // Rn
7291    TmpInst.addOperand(Inst.getOperand(3)); // alignment
7292    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7293    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7294    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7295                                            Spacing));
7296    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7297                                            Spacing * 2));
7298    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7299                                            Spacing * 3));
7300    TmpInst.addOperand(Inst.getOperand(1)); // lane
7301    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7302    TmpInst.addOperand(Inst.getOperand(5));
7303    Inst = TmpInst;
7304    return true;
7305  }
7306
7307  case ARM::VLD1LNdAsm_8:
7308  case ARM::VLD1LNdAsm_16:
7309  case ARM::VLD1LNdAsm_32: {
7310    MCInst TmpInst;
7311    // Shuffle the operands around so the lane index operand is in the
7312    // right place.
7313    unsigned Spacing;
7314    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7315    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7316    TmpInst.addOperand(Inst.getOperand(2)); // Rn
7317    TmpInst.addOperand(Inst.getOperand(3)); // alignment
7318    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7319    TmpInst.addOperand(Inst.getOperand(1)); // lane
7320    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7321    TmpInst.addOperand(Inst.getOperand(5));
7322    Inst = TmpInst;
7323    return true;
7324  }
7325
7326  case ARM::VLD2LNdAsm_8:
7327  case ARM::VLD2LNdAsm_16:
7328  case ARM::VLD2LNdAsm_32:
7329  case ARM::VLD2LNqAsm_16:
7330  case ARM::VLD2LNqAsm_32: {
7331    MCInst TmpInst;
7332    // Shuffle the operands around so the lane index operand is in the
7333    // right place.
7334    unsigned Spacing;
7335    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7336    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7337    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7338                                            Spacing));
7339    TmpInst.addOperand(Inst.getOperand(2)); // Rn
7340    TmpInst.addOperand(Inst.getOperand(3)); // alignment
7341    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7342    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7343                                            Spacing));
7344    TmpInst.addOperand(Inst.getOperand(1)); // lane
7345    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7346    TmpInst.addOperand(Inst.getOperand(5));
7347    Inst = TmpInst;
7348    return true;
7349  }
7350
7351  case ARM::VLD3LNdAsm_8:
7352  case ARM::VLD3LNdAsm_16:
7353  case ARM::VLD3LNdAsm_32:
7354  case ARM::VLD3LNqAsm_16:
7355  case ARM::VLD3LNqAsm_32: {
7356    MCInst TmpInst;
7357    // Shuffle the operands around so the lane index operand is in the
7358    // right place.
7359    unsigned Spacing;
7360    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7361    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7362    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7363                                            Spacing));
7364    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7365                                            Spacing * 2));
7366    TmpInst.addOperand(Inst.getOperand(2)); // Rn
7367    TmpInst.addOperand(Inst.getOperand(3)); // alignment
7368    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7369    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7370                                            Spacing));
7371    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7372                                            Spacing * 2));
7373    TmpInst.addOperand(Inst.getOperand(1)); // lane
7374    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7375    TmpInst.addOperand(Inst.getOperand(5));
7376    Inst = TmpInst;
7377    return true;
7378  }
7379
7380  case ARM::VLD4LNdAsm_8:
7381  case ARM::VLD4LNdAsm_16:
7382  case ARM::VLD4LNdAsm_32:
7383  case ARM::VLD4LNqAsm_16:
7384  case ARM::VLD4LNqAsm_32: {
7385    MCInst TmpInst;
7386    // Shuffle the operands around so the lane index operand is in the
7387    // right place.
7388    unsigned Spacing;
7389    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7390    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7391    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7392                                            Spacing));
7393    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7394                                            Spacing * 2));
7395    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7396                                            Spacing * 3));
7397    TmpInst.addOperand(Inst.getOperand(2)); // Rn
7398    TmpInst.addOperand(Inst.getOperand(3)); // alignment
7399    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7400    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7401                                            Spacing));
7402    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7403                                            Spacing * 2));
7404    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7405                                            Spacing * 3));
7406    TmpInst.addOperand(Inst.getOperand(1)); // lane
7407    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7408    TmpInst.addOperand(Inst.getOperand(5));
7409    Inst = TmpInst;
7410    return true;
7411  }
7412
7413  // VLD3DUP single 3-element structure to all lanes instructions.
7414  case ARM::VLD3DUPdAsm_8:
7415  case ARM::VLD3DUPdAsm_16:
7416  case ARM::VLD3DUPdAsm_32:
7417  case ARM::VLD3DUPqAsm_8:
7418  case ARM::VLD3DUPqAsm_16:
7419  case ARM::VLD3DUPqAsm_32: {
7420    MCInst TmpInst;
7421    unsigned Spacing;
7422    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7423    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7424    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7425                                            Spacing));
7426    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7427                                            Spacing * 2));
7428    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7429    TmpInst.addOperand(Inst.getOperand(2)); // alignment
7430    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7431    TmpInst.addOperand(Inst.getOperand(4));
7432    Inst = TmpInst;
7433    return true;
7434  }
7435
7436  case ARM::VLD3DUPdWB_fixed_Asm_8:
7437  case ARM::VLD3DUPdWB_fixed_Asm_16:
7438  case ARM::VLD3DUPdWB_fixed_Asm_32:
7439  case ARM::VLD3DUPqWB_fixed_Asm_8:
7440  case ARM::VLD3DUPqWB_fixed_Asm_16:
7441  case ARM::VLD3DUPqWB_fixed_Asm_32: {
7442    MCInst TmpInst;
7443    unsigned Spacing;
7444    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7445    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7446    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7447                                            Spacing));
7448    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7449                                            Spacing * 2));
7450    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7451    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7452    TmpInst.addOperand(Inst.getOperand(2)); // alignment
7453    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7454    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7455    TmpInst.addOperand(Inst.getOperand(4));
7456    Inst = TmpInst;
7457    return true;
7458  }
7459
7460  case ARM::VLD3DUPdWB_register_Asm_8:
7461  case ARM::VLD3DUPdWB_register_Asm_16:
7462  case ARM::VLD3DUPdWB_register_Asm_32:
7463  case ARM::VLD3DUPqWB_register_Asm_8:
7464  case ARM::VLD3DUPqWB_register_Asm_16:
7465  case ARM::VLD3DUPqWB_register_Asm_32: {
7466    MCInst TmpInst;
7467    unsigned Spacing;
7468    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7469    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7470    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7471                                            Spacing));
7472    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7473                                            Spacing * 2));
7474    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7475    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7476    TmpInst.addOperand(Inst.getOperand(2)); // alignment
7477    TmpInst.addOperand(Inst.getOperand(3)); // Rm
7478    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7479    TmpInst.addOperand(Inst.getOperand(5));
7480    Inst = TmpInst;
7481    return true;
7482  }
7483
7484  // VLD3 multiple 3-element structure instructions.
7485  case ARM::VLD3dAsm_8:
7486  case ARM::VLD3dAsm_16:
7487  case ARM::VLD3dAsm_32:
7488  case ARM::VLD3qAsm_8:
7489  case ARM::VLD3qAsm_16:
7490  case ARM::VLD3qAsm_32: {
7491    MCInst TmpInst;
7492    unsigned Spacing;
7493    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7494    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7495    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7496                                            Spacing));
7497    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7498                                            Spacing * 2));
7499    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7500    TmpInst.addOperand(Inst.getOperand(2)); // alignment
7501    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7502    TmpInst.addOperand(Inst.getOperand(4));
7503    Inst = TmpInst;
7504    return true;
7505  }
7506
7507  case ARM::VLD3dWB_fixed_Asm_8:
7508  case ARM::VLD3dWB_fixed_Asm_16:
7509  case ARM::VLD3dWB_fixed_Asm_32:
7510  case ARM::VLD3qWB_fixed_Asm_8:
7511  case ARM::VLD3qWB_fixed_Asm_16:
7512  case ARM::VLD3qWB_fixed_Asm_32: {
7513    MCInst TmpInst;
7514    unsigned Spacing;
7515    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7516    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7517    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7518                                            Spacing));
7519    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7520                                            Spacing * 2));
7521    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7522    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7523    TmpInst.addOperand(Inst.getOperand(2)); // alignment
7524    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7525    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7526    TmpInst.addOperand(Inst.getOperand(4));
7527    Inst = TmpInst;
7528    return true;
7529  }
7530
7531  case ARM::VLD3dWB_register_Asm_8:
7532  case ARM::VLD3dWB_register_Asm_16:
7533  case ARM::VLD3dWB_register_Asm_32:
7534  case ARM::VLD3qWB_register_Asm_8:
7535  case ARM::VLD3qWB_register_Asm_16:
7536  case ARM::VLD3qWB_register_Asm_32: {
7537    MCInst TmpInst;
7538    unsigned Spacing;
7539    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7540    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7541    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7542                                            Spacing));
7543    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7544                                            Spacing * 2));
7545    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7546    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7547    TmpInst.addOperand(Inst.getOperand(2)); // alignment
7548    TmpInst.addOperand(Inst.getOperand(3)); // Rm
7549    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7550    TmpInst.addOperand(Inst.getOperand(5));
7551    Inst = TmpInst;
7552    return true;
7553  }
7554
7555  // VLD4DUP single 3-element structure to all lanes instructions.
7556  case ARM::VLD4DUPdAsm_8:
7557  case ARM::VLD4DUPdAsm_16:
7558  case ARM::VLD4DUPdAsm_32:
7559  case ARM::VLD4DUPqAsm_8:
7560  case ARM::VLD4DUPqAsm_16:
7561  case ARM::VLD4DUPqAsm_32: {
7562    MCInst TmpInst;
7563    unsigned Spacing;
7564    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7565    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7566    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7567                                            Spacing));
7568    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7569                                            Spacing * 2));
7570    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7571                                            Spacing * 3));
7572    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7573    TmpInst.addOperand(Inst.getOperand(2)); // alignment
7574    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7575    TmpInst.addOperand(Inst.getOperand(4));
7576    Inst = TmpInst;
7577    return true;
7578  }
7579
7580  case ARM::VLD4DUPdWB_fixed_Asm_8:
7581  case ARM::VLD4DUPdWB_fixed_Asm_16:
7582  case ARM::VLD4DUPdWB_fixed_Asm_32:
7583  case ARM::VLD4DUPqWB_fixed_Asm_8:
7584  case ARM::VLD4DUPqWB_fixed_Asm_16:
7585  case ARM::VLD4DUPqWB_fixed_Asm_32: {
7586    MCInst TmpInst;
7587    unsigned Spacing;
7588    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7589    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7590    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7591                                            Spacing));
7592    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7593                                            Spacing * 2));
7594    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7595                                            Spacing * 3));
7596    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7597    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7598    TmpInst.addOperand(Inst.getOperand(2)); // alignment
7599    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7600    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7601    TmpInst.addOperand(Inst.getOperand(4));
7602    Inst = TmpInst;
7603    return true;
7604  }
7605
7606  case ARM::VLD4DUPdWB_register_Asm_8:
7607  case ARM::VLD4DUPdWB_register_Asm_16:
7608  case ARM::VLD4DUPdWB_register_Asm_32:
7609  case ARM::VLD4DUPqWB_register_Asm_8:
7610  case ARM::VLD4DUPqWB_register_Asm_16:
7611  case ARM::VLD4DUPqWB_register_Asm_32: {
7612    MCInst TmpInst;
7613    unsigned Spacing;
7614    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7615    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7616    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7617                                            Spacing));
7618    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7619                                            Spacing * 2));
7620    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7621                                            Spacing * 3));
7622    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7623    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7624    TmpInst.addOperand(Inst.getOperand(2)); // alignment
7625    TmpInst.addOperand(Inst.getOperand(3)); // Rm
7626    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7627    TmpInst.addOperand(Inst.getOperand(5));
7628    Inst = TmpInst;
7629    return true;
7630  }
7631
7632  // VLD4 multiple 4-element structure instructions.
7633  case ARM::VLD4dAsm_8:
7634  case ARM::VLD4dAsm_16:
7635  case ARM::VLD4dAsm_32:
7636  case ARM::VLD4qAsm_8:
7637  case ARM::VLD4qAsm_16:
7638  case ARM::VLD4qAsm_32: {
7639    MCInst TmpInst;
7640    unsigned Spacing;
7641    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7642    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7643    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7644                                            Spacing));
7645    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7646                                            Spacing * 2));
7647    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7648                                            Spacing * 3));
7649    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7650    TmpInst.addOperand(Inst.getOperand(2)); // alignment
7651    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7652    TmpInst.addOperand(Inst.getOperand(4));
7653    Inst = TmpInst;
7654    return true;
7655  }
7656
7657  case ARM::VLD4dWB_fixed_Asm_8:
7658  case ARM::VLD4dWB_fixed_Asm_16:
7659  case ARM::VLD4dWB_fixed_Asm_32:
7660  case ARM::VLD4qWB_fixed_Asm_8:
7661  case ARM::VLD4qWB_fixed_Asm_16:
7662  case ARM::VLD4qWB_fixed_Asm_32: {
7663    MCInst TmpInst;
7664    unsigned Spacing;
7665    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7666    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7667    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7668                                            Spacing));
7669    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7670                                            Spacing * 2));
7671    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7672                                            Spacing * 3));
7673    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7674    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7675    TmpInst.addOperand(Inst.getOperand(2)); // alignment
7676    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7677    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7678    TmpInst.addOperand(Inst.getOperand(4));
7679    Inst = TmpInst;
7680    return true;
7681  }
7682
7683  case ARM::VLD4dWB_register_Asm_8:
7684  case ARM::VLD4dWB_register_Asm_16:
7685  case ARM::VLD4dWB_register_Asm_32:
7686  case ARM::VLD4qWB_register_Asm_8:
7687  case ARM::VLD4qWB_register_Asm_16:
7688  case ARM::VLD4qWB_register_Asm_32: {
7689    MCInst TmpInst;
7690    unsigned Spacing;
7691    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7692    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7693    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7694                                            Spacing));
7695    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7696                                            Spacing * 2));
7697    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7698                                            Spacing * 3));
7699    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7700    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7701    TmpInst.addOperand(Inst.getOperand(2)); // alignment
7702    TmpInst.addOperand(Inst.getOperand(3)); // Rm
7703    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7704    TmpInst.addOperand(Inst.getOperand(5));
7705    Inst = TmpInst;
7706    return true;
7707  }
7708
7709  // VST3 multiple 3-element structure instructions.
7710  case ARM::VST3dAsm_8:
7711  case ARM::VST3dAsm_16:
7712  case ARM::VST3dAsm_32:
7713  case ARM::VST3qAsm_8:
7714  case ARM::VST3qAsm_16:
7715  case ARM::VST3qAsm_32: {
7716    MCInst TmpInst;
7717    unsigned Spacing;
7718    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7719    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7720    TmpInst.addOperand(Inst.getOperand(2)); // alignment
7721    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7722    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7723                                            Spacing));
7724    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7725                                            Spacing * 2));
7726    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7727    TmpInst.addOperand(Inst.getOperand(4));
7728    Inst = TmpInst;
7729    return true;
7730  }
7731
7732  case ARM::VST3dWB_fixed_Asm_8:
7733  case ARM::VST3dWB_fixed_Asm_16:
7734  case ARM::VST3dWB_fixed_Asm_32:
7735  case ARM::VST3qWB_fixed_Asm_8:
7736  case ARM::VST3qWB_fixed_Asm_16:
7737  case ARM::VST3qWB_fixed_Asm_32: {
7738    MCInst TmpInst;
7739    unsigned Spacing;
7740    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7741    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7742    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7743    TmpInst.addOperand(Inst.getOperand(2)); // alignment
7744    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7745    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7746    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7747                                            Spacing));
7748    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7749                                            Spacing * 2));
7750    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7751    TmpInst.addOperand(Inst.getOperand(4));
7752    Inst = TmpInst;
7753    return true;
7754  }
7755
7756  case ARM::VST3dWB_register_Asm_8:
7757  case ARM::VST3dWB_register_Asm_16:
7758  case ARM::VST3dWB_register_Asm_32:
7759  case ARM::VST3qWB_register_Asm_8:
7760  case ARM::VST3qWB_register_Asm_16:
7761  case ARM::VST3qWB_register_Asm_32: {
7762    MCInst TmpInst;
7763    unsigned Spacing;
7764    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7765    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7766    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7767    TmpInst.addOperand(Inst.getOperand(2)); // alignment
7768    TmpInst.addOperand(Inst.getOperand(3)); // Rm
7769    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7770    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7771                                            Spacing));
7772    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7773                                            Spacing * 2));
7774    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7775    TmpInst.addOperand(Inst.getOperand(5));
7776    Inst = TmpInst;
7777    return true;
7778  }
7779
7780  // VST4 multiple 3-element structure instructions.
7781  case ARM::VST4dAsm_8:
7782  case ARM::VST4dAsm_16:
7783  case ARM::VST4dAsm_32:
7784  case ARM::VST4qAsm_8:
7785  case ARM::VST4qAsm_16:
7786  case ARM::VST4qAsm_32: {
7787    MCInst TmpInst;
7788    unsigned Spacing;
7789    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7790    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7791    TmpInst.addOperand(Inst.getOperand(2)); // alignment
7792    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7793    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7794                                            Spacing));
7795    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7796                                            Spacing * 2));
7797    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7798                                            Spacing * 3));
7799    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7800    TmpInst.addOperand(Inst.getOperand(4));
7801    Inst = TmpInst;
7802    return true;
7803  }
7804
7805  case ARM::VST4dWB_fixed_Asm_8:
7806  case ARM::VST4dWB_fixed_Asm_16:
7807  case ARM::VST4dWB_fixed_Asm_32:
7808  case ARM::VST4qWB_fixed_Asm_8:
7809  case ARM::VST4qWB_fixed_Asm_16:
7810  case ARM::VST4qWB_fixed_Asm_32: {
7811    MCInst TmpInst;
7812    unsigned Spacing;
7813    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7814    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7815    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7816    TmpInst.addOperand(Inst.getOperand(2)); // alignment
7817    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7818    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7819    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7820                                            Spacing));
7821    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7822                                            Spacing * 2));
7823    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7824                                            Spacing * 3));
7825    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7826    TmpInst.addOperand(Inst.getOperand(4));
7827    Inst = TmpInst;
7828    return true;
7829  }
7830
7831  case ARM::VST4dWB_register_Asm_8:
7832  case ARM::VST4dWB_register_Asm_16:
7833  case ARM::VST4dWB_register_Asm_32:
7834  case ARM::VST4qWB_register_Asm_8:
7835  case ARM::VST4qWB_register_Asm_16:
7836  case ARM::VST4qWB_register_Asm_32: {
7837    MCInst TmpInst;
7838    unsigned Spacing;
7839    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7840    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7841    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7842    TmpInst.addOperand(Inst.getOperand(2)); // alignment
7843    TmpInst.addOperand(Inst.getOperand(3)); // Rm
7844    TmpInst.addOperand(Inst.getOperand(0)); // Vd
7845    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7846                                            Spacing));
7847    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7848                                            Spacing * 2));
7849    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7850                                            Spacing * 3));
7851    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7852    TmpInst.addOperand(Inst.getOperand(5));
7853    Inst = TmpInst;
7854    return true;
7855  }
7856
7857  // Handle encoding choice for the shift-immediate instructions.
7858  case ARM::t2LSLri:
7859  case ARM::t2LSRri:
7860  case ARM::t2ASRri: {
7861    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7862        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7863        Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7864        !(static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7865          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) {
7866      unsigned NewOpc;
7867      switch (Inst.getOpcode()) {
7868      default: llvm_unreachable("unexpected opcode");
7869      case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7870      case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7871      case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7872      }
7873      // The Thumb1 operands aren't in the same order. Awesome, eh?
7874      MCInst TmpInst;
7875      TmpInst.setOpcode(NewOpc);
7876      TmpInst.addOperand(Inst.getOperand(0));
7877      TmpInst.addOperand(Inst.getOperand(5));
7878      TmpInst.addOperand(Inst.getOperand(1));
7879      TmpInst.addOperand(Inst.getOperand(2));
7880      TmpInst.addOperand(Inst.getOperand(3));
7881      TmpInst.addOperand(Inst.getOperand(4));
7882      Inst = TmpInst;
7883      return true;
7884    }
7885    return false;
7886  }
7887
7888  // Handle the Thumb2 mode MOV complex aliases.
7889  case ARM::t2MOVsr:
7890  case ARM::t2MOVSsr: {
7891    // Which instruction to expand to depends on the CCOut operand and
7892    // whether we're in an IT block if the register operands are low
7893    // registers.
7894    bool isNarrow = false;
7895    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7896        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7897        isARMLowRegister(Inst.getOperand(2).getReg()) &&
7898        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7899        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7900      isNarrow = true;
7901    MCInst TmpInst;
7902    unsigned newOpc;
7903    switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7904    default: llvm_unreachable("unexpected opcode!");
7905    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7906    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7907    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7908    case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
7909    }
7910    TmpInst.setOpcode(newOpc);
7911    TmpInst.addOperand(Inst.getOperand(0)); // Rd
7912    if (isNarrow)
7913      TmpInst.addOperand(MCOperand::CreateReg(
7914          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7915    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7916    TmpInst.addOperand(Inst.getOperand(2)); // Rm
7917    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7918    TmpInst.addOperand(Inst.getOperand(5));
7919    if (!isNarrow)
7920      TmpInst.addOperand(MCOperand::CreateReg(
7921          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7922    Inst = TmpInst;
7923    return true;
7924  }
7925  case ARM::t2MOVsi:
7926  case ARM::t2MOVSsi: {
7927    // Which instruction to expand to depends on the CCOut operand and
7928    // whether we're in an IT block if the register operands are low
7929    // registers.
7930    bool isNarrow = false;
7931    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7932        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7933        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7934      isNarrow = true;
7935    MCInst TmpInst;
7936    unsigned newOpc;
7937    switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7938    default: llvm_unreachable("unexpected opcode!");
7939    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7940    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7941    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7942    case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7943    case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7944    }
7945    unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7946    if (Amount == 32) Amount = 0;
7947    TmpInst.setOpcode(newOpc);
7948    TmpInst.addOperand(Inst.getOperand(0)); // Rd
7949    if (isNarrow)
7950      TmpInst.addOperand(MCOperand::CreateReg(
7951          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7952    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7953    if (newOpc != ARM::t2RRX)
7954      TmpInst.addOperand(MCOperand::CreateImm(Amount));
7955    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7956    TmpInst.addOperand(Inst.getOperand(4));
7957    if (!isNarrow)
7958      TmpInst.addOperand(MCOperand::CreateReg(
7959          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7960    Inst = TmpInst;
7961    return true;
7962  }
7963  // Handle the ARM mode MOV complex aliases.
7964  case ARM::ASRr:
7965  case ARM::LSRr:
7966  case ARM::LSLr:
7967  case ARM::RORr: {
7968    ARM_AM::ShiftOpc ShiftTy;
7969    switch(Inst.getOpcode()) {
7970    default: llvm_unreachable("unexpected opcode!");
7971    case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7972    case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7973    case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7974    case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7975    }
7976    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7977    MCInst TmpInst;
7978    TmpInst.setOpcode(ARM::MOVsr);
7979    TmpInst.addOperand(Inst.getOperand(0)); // Rd
7980    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7981    TmpInst.addOperand(Inst.getOperand(2)); // Rm
7982    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7983    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7984    TmpInst.addOperand(Inst.getOperand(4));
7985    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7986    Inst = TmpInst;
7987    return true;
7988  }
7989  case ARM::ASRi:
7990  case ARM::LSRi:
7991  case ARM::LSLi:
7992  case ARM::RORi: {
7993    ARM_AM::ShiftOpc ShiftTy;
7994    switch(Inst.getOpcode()) {
7995    default: llvm_unreachable("unexpected opcode!");
7996    case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7997    case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7998    case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7999    case ARM::RORi: ShiftTy = ARM_AM::ror; break;
8000    }
8001    // A shift by zero is a plain MOVr, not a MOVsi.
8002    unsigned Amt = Inst.getOperand(2).getImm();
8003    unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
8004    // A shift by 32 should be encoded as 0 when permitted
8005    if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
8006      Amt = 0;
8007    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
8008    MCInst TmpInst;
8009    TmpInst.setOpcode(Opc);
8010    TmpInst.addOperand(Inst.getOperand(0)); // Rd
8011    TmpInst.addOperand(Inst.getOperand(1)); // Rn
8012    if (Opc == ARM::MOVsi)
8013      TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
8014    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8015    TmpInst.addOperand(Inst.getOperand(4));
8016    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
8017    Inst = TmpInst;
8018    return true;
8019  }
8020  case ARM::RRXi: {
8021    unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
8022    MCInst TmpInst;
8023    TmpInst.setOpcode(ARM::MOVsi);
8024    TmpInst.addOperand(Inst.getOperand(0)); // Rd
8025    TmpInst.addOperand(Inst.getOperand(1)); // Rn
8026    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
8027    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8028    TmpInst.addOperand(Inst.getOperand(3));
8029    TmpInst.addOperand(Inst.getOperand(4)); // cc_out
8030    Inst = TmpInst;
8031    return true;
8032  }
8033  case ARM::t2LDMIA_UPD: {
8034    // If this is a load of a single register, then we should use
8035    // a post-indexed LDR instruction instead, per the ARM ARM.
8036    if (Inst.getNumOperands() != 5)
8037      return false;
8038    MCInst TmpInst;
8039    TmpInst.setOpcode(ARM::t2LDR_POST);
8040    TmpInst.addOperand(Inst.getOperand(4)); // Rt
8041    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8042    TmpInst.addOperand(Inst.getOperand(1)); // Rn
8043    TmpInst.addOperand(MCOperand::CreateImm(4));
8044    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8045    TmpInst.addOperand(Inst.getOperand(3));
8046    Inst = TmpInst;
8047    return true;
8048  }
8049  case ARM::t2STMDB_UPD: {
8050    // If this is a store of a single register, then we should use
8051    // a pre-indexed STR instruction instead, per the ARM ARM.
8052    if (Inst.getNumOperands() != 5)
8053      return false;
8054    MCInst TmpInst;
8055    TmpInst.setOpcode(ARM::t2STR_PRE);
8056    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8057    TmpInst.addOperand(Inst.getOperand(4)); // Rt
8058    TmpInst.addOperand(Inst.getOperand(1)); // Rn
8059    TmpInst.addOperand(MCOperand::CreateImm(-4));
8060    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8061    TmpInst.addOperand(Inst.getOperand(3));
8062    Inst = TmpInst;
8063    return true;
8064  }
8065  case ARM::LDMIA_UPD:
8066    // If this is a load of a single register via a 'pop', then we should use
8067    // a post-indexed LDR instruction instead, per the ARM ARM.
8068    if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
8069        Inst.getNumOperands() == 5) {
8070      MCInst TmpInst;
8071      TmpInst.setOpcode(ARM::LDR_POST_IMM);
8072      TmpInst.addOperand(Inst.getOperand(4)); // Rt
8073      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8074      TmpInst.addOperand(Inst.getOperand(1)); // Rn
8075      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
8076      TmpInst.addOperand(MCOperand::CreateImm(4));
8077      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8078      TmpInst.addOperand(Inst.getOperand(3));
8079      Inst = TmpInst;
8080      return true;
8081    }
8082    break;
8083  case ARM::STMDB_UPD:
8084    // If this is a store of a single register via a 'push', then we should use
8085    // a pre-indexed STR instruction instead, per the ARM ARM.
8086    if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
8087        Inst.getNumOperands() == 5) {
8088      MCInst TmpInst;
8089      TmpInst.setOpcode(ARM::STR_PRE_IMM);
8090      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8091      TmpInst.addOperand(Inst.getOperand(4)); // Rt
8092      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
8093      TmpInst.addOperand(MCOperand::CreateImm(-4));
8094      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8095      TmpInst.addOperand(Inst.getOperand(3));
8096      Inst = TmpInst;
8097    }
8098    break;
8099  case ARM::t2ADDri12:
8100    // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
8101    // mnemonic was used (not "addw"), encoding T3 is preferred.
8102    if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
8103        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8104      break;
8105    Inst.setOpcode(ARM::t2ADDri);
8106    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
8107    break;
8108  case ARM::t2SUBri12:
8109    // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
8110    // mnemonic was used (not "subw"), encoding T3 is preferred.
8111    if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
8112        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8113      break;
8114    Inst.setOpcode(ARM::t2SUBri);
8115    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
8116    break;
8117  case ARM::tADDi8:
8118    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8119    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8120    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8121    // to encoding T1 if <Rd> is omitted."
8122    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8123      Inst.setOpcode(ARM::tADDi3);
8124      return true;
8125    }
8126    break;
8127  case ARM::tSUBi8:
8128    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8129    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8130    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8131    // to encoding T1 if <Rd> is omitted."
8132    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8133      Inst.setOpcode(ARM::tSUBi3);
8134      return true;
8135    }
8136    break;
8137  case ARM::t2ADDri:
8138  case ARM::t2SUBri: {
8139    // If the destination and first source operand are the same, and
8140    // the flags are compatible with the current IT status, use encoding T2
8141    // instead of T3. For compatibility with the system 'as'. Make sure the
8142    // wide encoding wasn't explicit.
8143    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
8144        !isARMLowRegister(Inst.getOperand(0).getReg()) ||
8145        (unsigned)Inst.getOperand(2).getImm() > 255 ||
8146        ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
8147         (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
8148        (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8149         static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
8150      break;
8151    MCInst TmpInst;
8152    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
8153                      ARM::tADDi8 : ARM::tSUBi8);
8154    TmpInst.addOperand(Inst.getOperand(0));
8155    TmpInst.addOperand(Inst.getOperand(5));
8156    TmpInst.addOperand(Inst.getOperand(0));
8157    TmpInst.addOperand(Inst.getOperand(2));
8158    TmpInst.addOperand(Inst.getOperand(3));
8159    TmpInst.addOperand(Inst.getOperand(4));
8160    Inst = TmpInst;
8161    return true;
8162  }
8163  case ARM::t2ADDrr: {
8164    // If the destination and first source operand are the same, and
8165    // there's no setting of the flags, use encoding T2 instead of T3.
8166    // Note that this is only for ADD, not SUB. This mirrors the system
8167    // 'as' behaviour. Make sure the wide encoding wasn't explicit.
8168    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
8169        Inst.getOperand(5).getReg() != 0 ||
8170        (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8171         static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
8172      break;
8173    MCInst TmpInst;
8174    TmpInst.setOpcode(ARM::tADDhirr);
8175    TmpInst.addOperand(Inst.getOperand(0));
8176    TmpInst.addOperand(Inst.getOperand(0));
8177    TmpInst.addOperand(Inst.getOperand(2));
8178    TmpInst.addOperand(Inst.getOperand(3));
8179    TmpInst.addOperand(Inst.getOperand(4));
8180    Inst = TmpInst;
8181    return true;
8182  }
8183  case ARM::tADDrSP: {
8184    // If the non-SP source operand and the destination operand are not the
8185    // same, we need to use the 32-bit encoding if it's available.
8186    if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
8187      Inst.setOpcode(ARM::t2ADDrr);
8188      Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
8189      return true;
8190    }
8191    break;
8192  }
8193  case ARM::tB:
8194    // A Thumb conditional branch outside of an IT block is a tBcc.
8195    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
8196      Inst.setOpcode(ARM::tBcc);
8197      return true;
8198    }
8199    break;
8200  case ARM::t2B:
8201    // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
8202    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
8203      Inst.setOpcode(ARM::t2Bcc);
8204      return true;
8205    }
8206    break;
8207  case ARM::t2Bcc:
8208    // If the conditional is AL or we're in an IT block, we really want t2B.
8209    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
8210      Inst.setOpcode(ARM::t2B);
8211      return true;
8212    }
8213    break;
8214  case ARM::tBcc:
8215    // If the conditional is AL, we really want tB.
8216    if (Inst.getOperand(1).getImm() == ARMCC::AL) {
8217      Inst.setOpcode(ARM::tB);
8218      return true;
8219    }
8220    break;
8221  case ARM::tLDMIA: {
8222    // If the register list contains any high registers, or if the writeback
8223    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
8224    // instead if we're in Thumb2. Otherwise, this should have generated
8225    // an error in validateInstruction().
8226    unsigned Rn = Inst.getOperand(0).getReg();
8227    bool hasWritebackToken =
8228        (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8229         static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
8230    bool listContainsBase;
8231    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
8232        (!listContainsBase && !hasWritebackToken) ||
8233        (listContainsBase && hasWritebackToken)) {
8234      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8235      assert (isThumbTwo());
8236      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
8237      // If we're switching to the updating version, we need to insert
8238      // the writeback tied operand.
8239      if (hasWritebackToken)
8240        Inst.insert(Inst.begin(),
8241                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
8242      return true;
8243    }
8244    break;
8245  }
8246  case ARM::tSTMIA_UPD: {
8247    // If the register list contains any high registers, we need to use
8248    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8249    // should have generated an error in validateInstruction().
8250    unsigned Rn = Inst.getOperand(0).getReg();
8251    bool listContainsBase;
8252    if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
8253      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8254      assert (isThumbTwo());
8255      Inst.setOpcode(ARM::t2STMIA_UPD);
8256      return true;
8257    }
8258    break;
8259  }
8260  case ARM::tPOP: {
8261    bool listContainsBase;
8262    // If the register list contains any high registers, we need to use
8263    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8264    // should have generated an error in validateInstruction().
8265    if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
8266      return false;
8267    assert (isThumbTwo());
8268    Inst.setOpcode(ARM::t2LDMIA_UPD);
8269    // Add the base register and writeback operands.
8270    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
8271    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
8272    return true;
8273  }
8274  case ARM::tPUSH: {
8275    bool listContainsBase;
8276    if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
8277      return false;
8278    assert (isThumbTwo());
8279    Inst.setOpcode(ARM::t2STMDB_UPD);
8280    // Add the base register and writeback operands.
8281    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
8282    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
8283    return true;
8284  }
8285  case ARM::t2MOVi: {
8286    // If we can use the 16-bit encoding and the user didn't explicitly
8287    // request the 32-bit variant, transform it here.
8288    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8289        (unsigned)Inst.getOperand(1).getImm() <= 255 &&
8290        ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
8291          Inst.getOperand(4).getReg() == ARM::CPSR) ||
8292         (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
8293        (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8294         static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8295      // The operands aren't in the same order for tMOVi8...
8296      MCInst TmpInst;
8297      TmpInst.setOpcode(ARM::tMOVi8);
8298      TmpInst.addOperand(Inst.getOperand(0));
8299      TmpInst.addOperand(Inst.getOperand(4));
8300      TmpInst.addOperand(Inst.getOperand(1));
8301      TmpInst.addOperand(Inst.getOperand(2));
8302      TmpInst.addOperand(Inst.getOperand(3));
8303      Inst = TmpInst;
8304      return true;
8305    }
8306    break;
8307  }
8308  case ARM::t2MOVr: {
8309    // If we can use the 16-bit encoding and the user didn't explicitly
8310    // request the 32-bit variant, transform it here.
8311    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8312        isARMLowRegister(Inst.getOperand(1).getReg()) &&
8313        Inst.getOperand(2).getImm() == ARMCC::AL &&
8314        Inst.getOperand(4).getReg() == ARM::CPSR &&
8315        (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8316         static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8317      // The operands aren't the same for tMOV[S]r... (no cc_out)
8318      MCInst TmpInst;
8319      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
8320      TmpInst.addOperand(Inst.getOperand(0));
8321      TmpInst.addOperand(Inst.getOperand(1));
8322      TmpInst.addOperand(Inst.getOperand(2));
8323      TmpInst.addOperand(Inst.getOperand(3));
8324      Inst = TmpInst;
8325      return true;
8326    }
8327    break;
8328  }
8329  case ARM::t2SXTH:
8330  case ARM::t2SXTB:
8331  case ARM::t2UXTH:
8332  case ARM::t2UXTB: {
8333    // If we can use the 16-bit encoding and the user didn't explicitly
8334    // request the 32-bit variant, transform it here.
8335    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8336        isARMLowRegister(Inst.getOperand(1).getReg()) &&
8337        Inst.getOperand(2).getImm() == 0 &&
8338        (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8339         static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8340      unsigned NewOpc;
8341      switch (Inst.getOpcode()) {
8342      default: llvm_unreachable("Illegal opcode!");
8343      case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
8344      case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
8345      case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
8346      case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
8347      }
8348      // The operands aren't the same for thumb1 (no rotate operand).
8349      MCInst TmpInst;
8350      TmpInst.setOpcode(NewOpc);
8351      TmpInst.addOperand(Inst.getOperand(0));
8352      TmpInst.addOperand(Inst.getOperand(1));
8353      TmpInst.addOperand(Inst.getOperand(3));
8354      TmpInst.addOperand(Inst.getOperand(4));
8355      Inst = TmpInst;
8356      return true;
8357    }
8358    break;
8359  }
8360  case ARM::MOVsi: {
8361    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
8362    // rrx shifts and asr/lsr of #32 is encoded as 0
8363    if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
8364      return false;
8365    if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
8366      // Shifting by zero is accepted as a vanilla 'MOVr'
8367      MCInst TmpInst;
8368      TmpInst.setOpcode(ARM::MOVr);
8369      TmpInst.addOperand(Inst.getOperand(0));
8370      TmpInst.addOperand(Inst.getOperand(1));
8371      TmpInst.addOperand(Inst.getOperand(3));
8372      TmpInst.addOperand(Inst.getOperand(4));
8373      TmpInst.addOperand(Inst.getOperand(5));
8374      Inst = TmpInst;
8375      return true;
8376    }
8377    return false;
8378  }
8379  case ARM::ANDrsi:
8380  case ARM::ORRrsi:
8381  case ARM::EORrsi:
8382  case ARM::BICrsi:
8383  case ARM::SUBrsi:
8384  case ARM::ADDrsi: {
8385    unsigned newOpc;
8386    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
8387    if (SOpc == ARM_AM::rrx) return false;
8388    switch (Inst.getOpcode()) {
8389    default: llvm_unreachable("unexpected opcode!");
8390    case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
8391    case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
8392    case ARM::EORrsi: newOpc = ARM::EORrr; break;
8393    case ARM::BICrsi: newOpc = ARM::BICrr; break;
8394    case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
8395    case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
8396    }
8397    // If the shift is by zero, use the non-shifted instruction definition.
8398    // The exception is for right shifts, where 0 == 32
8399    if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
8400        !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
8401      MCInst TmpInst;
8402      TmpInst.setOpcode(newOpc);
8403      TmpInst.addOperand(Inst.getOperand(0));
8404      TmpInst.addOperand(Inst.getOperand(1));
8405      TmpInst.addOperand(Inst.getOperand(2));
8406      TmpInst.addOperand(Inst.getOperand(4));
8407      TmpInst.addOperand(Inst.getOperand(5));
8408      TmpInst.addOperand(Inst.getOperand(6));
8409      Inst = TmpInst;
8410      return true;
8411    }
8412    return false;
8413  }
8414  case ARM::ITasm:
8415  case ARM::t2IT: {
8416    // The mask bits for all but the first condition are represented as
8417    // the low bit of the condition code value implies 't'. We currently
8418    // always have 1 implies 't', so XOR toggle the bits if the low bit
8419    // of the condition code is zero.
8420    MCOperand &MO = Inst.getOperand(1);
8421    unsigned Mask = MO.getImm();
8422    unsigned OrigMask = Mask;
8423    unsigned TZ = countTrailingZeros(Mask);
8424    if ((Inst.getOperand(0).getImm() & 1) == 0) {
8425      assert(Mask && TZ <= 3 && "illegal IT mask value!");
8426      Mask ^= (0xE << TZ) & 0xF;
8427    }
8428    MO.setImm(Mask);
8429
8430    // Set up the IT block state according to the IT instruction we just
8431    // matched.
8432    assert(!inITBlock() && "nested IT blocks?!");
8433    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
8434    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
8435    ITState.CurPosition = 0;
8436    ITState.FirstCond = true;
8437    break;
8438  }
8439  case ARM::t2LSLrr:
8440  case ARM::t2LSRrr:
8441  case ARM::t2ASRrr:
8442  case ARM::t2SBCrr:
8443  case ARM::t2RORrr:
8444  case ARM::t2BICrr:
8445  {
8446    // Assemblers should use the narrow encodings of these instructions when permissible.
8447    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8448         isARMLowRegister(Inst.getOperand(2).getReg())) &&
8449        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8450        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8451         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8452        (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8453         !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8454             ".w"))) {
8455      unsigned NewOpc;
8456      switch (Inst.getOpcode()) {
8457        default: llvm_unreachable("unexpected opcode");
8458        case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
8459        case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
8460        case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
8461        case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
8462        case ARM::t2RORrr: NewOpc = ARM::tROR; break;
8463        case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
8464      }
8465      MCInst TmpInst;
8466      TmpInst.setOpcode(NewOpc);
8467      TmpInst.addOperand(Inst.getOperand(0));
8468      TmpInst.addOperand(Inst.getOperand(5));
8469      TmpInst.addOperand(Inst.getOperand(1));
8470      TmpInst.addOperand(Inst.getOperand(2));
8471      TmpInst.addOperand(Inst.getOperand(3));
8472      TmpInst.addOperand(Inst.getOperand(4));
8473      Inst = TmpInst;
8474      return true;
8475    }
8476    return false;
8477  }
8478  case ARM::t2ANDrr:
8479  case ARM::t2EORrr:
8480  case ARM::t2ADCrr:
8481  case ARM::t2ORRrr:
8482  {
8483    // Assemblers should use the narrow encodings of these instructions when permissible.
8484    // These instructions are special in that they are commutable, so shorter encodings
8485    // are available more often.
8486    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8487         isARMLowRegister(Inst.getOperand(2).getReg())) &&
8488        (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
8489         Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
8490        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8491         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8492        (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8493         !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8494             ".w"))) {
8495      unsigned NewOpc;
8496      switch (Inst.getOpcode()) {
8497        default: llvm_unreachable("unexpected opcode");
8498        case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
8499        case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
8500        case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
8501        case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
8502      }
8503      MCInst TmpInst;
8504      TmpInst.setOpcode(NewOpc);
8505      TmpInst.addOperand(Inst.getOperand(0));
8506      TmpInst.addOperand(Inst.getOperand(5));
8507      if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
8508        TmpInst.addOperand(Inst.getOperand(1));
8509        TmpInst.addOperand(Inst.getOperand(2));
8510      } else {
8511        TmpInst.addOperand(Inst.getOperand(2));
8512        TmpInst.addOperand(Inst.getOperand(1));
8513      }
8514      TmpInst.addOperand(Inst.getOperand(3));
8515      TmpInst.addOperand(Inst.getOperand(4));
8516      Inst = TmpInst;
8517      return true;
8518    }
8519    return false;
8520  }
8521  }
8522  return false;
8523}
8524
8525unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
8526  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
8527  // suffix depending on whether they're in an IT block or not.
8528  unsigned Opc = Inst.getOpcode();
8529  const MCInstrDesc &MCID = MII.get(Opc);
8530  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
8531    assert(MCID.hasOptionalDef() &&
8532           "optionally flag setting instruction missing optional def operand");
8533    assert(MCID.NumOperands == Inst.getNumOperands() &&
8534           "operand count mismatch!");
8535    // Find the optional-def operand (cc_out).
8536    unsigned OpNo;
8537    for (OpNo = 0;
8538         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
8539         ++OpNo)
8540      ;
8541    // If we're parsing Thumb1, reject it completely.
8542    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
8543      return Match_MnemonicFail;
8544    // If we're parsing Thumb2, which form is legal depends on whether we're
8545    // in an IT block.
8546    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
8547        !inITBlock())
8548      return Match_RequiresITBlock;
8549    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
8550        inITBlock())
8551      return Match_RequiresNotITBlock;
8552  }
8553  // Some high-register supporting Thumb1 encodings only allow both registers
8554  // to be from r0-r7 when in Thumb2.
8555  else if (Opc == ARM::tADDhirr && isThumbOne() && !hasV6MOps() &&
8556           isARMLowRegister(Inst.getOperand(1).getReg()) &&
8557           isARMLowRegister(Inst.getOperand(2).getReg()))
8558    return Match_RequiresThumb2;
8559  // Others only require ARMv6 or later.
8560  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
8561           isARMLowRegister(Inst.getOperand(0).getReg()) &&
8562           isARMLowRegister(Inst.getOperand(1).getReg()))
8563    return Match_RequiresV6;
8564  return Match_Success;
8565}
8566
8567namespace llvm {
8568template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
8569  return true; // In an assembly source, no need to second-guess
8570}
8571}
8572
8573static const char *getSubtargetFeatureName(uint64_t Val);
8574bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8575                                           OperandVector &Operands,
8576                                           MCStreamer &Out, uint64_t &ErrorInfo,
8577                                           bool MatchingInlineAsm) {
8578  MCInst Inst;
8579  unsigned MatchResult;
8580
8581  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8582                                     MatchingInlineAsm);
8583  switch (MatchResult) {
8584  case Match_Success:
8585    // Context sensitive operand constraints aren't handled by the matcher,
8586    // so check them here.
8587    if (validateInstruction(Inst, Operands)) {
8588      // Still progress the IT block, otherwise one wrong condition causes
8589      // nasty cascading errors.
8590      forwardITPosition();
8591      return true;
8592    }
8593
8594    { // processInstruction() updates inITBlock state, we need to save it away
8595      bool wasInITBlock = inITBlock();
8596
8597      // Some instructions need post-processing to, for example, tweak which
8598      // encoding is selected. Loop on it while changes happen so the
8599      // individual transformations can chain off each other. E.g.,
8600      // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
8601      while (processInstruction(Inst, Operands, Out))
8602        ;
8603
8604      // Only after the instruction is fully processed, we can validate it
8605      if (wasInITBlock && hasV8Ops() && isThumb() &&
8606          !isV8EligibleForIT(&Inst)) {
8607        Warning(IDLoc, "deprecated instruction in IT block");
8608      }
8609    }
8610
8611    // Only move forward at the very end so that everything in validate
8612    // and process gets a consistent answer about whether we're in an IT
8613    // block.
8614    forwardITPosition();
8615
8616    // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
8617    // doesn't actually encode.
8618    if (Inst.getOpcode() == ARM::ITasm)
8619      return false;
8620
8621    Inst.setLoc(IDLoc);
8622    Out.EmitInstruction(Inst, STI);
8623    return false;
8624  case Match_MissingFeature: {
8625    assert(ErrorInfo && "Unknown missing feature!");
8626    // Special case the error message for the very common case where only
8627    // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
8628    std::string Msg = "instruction requires:";
8629    uint64_t Mask = 1;
8630    for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
8631      if (ErrorInfo & Mask) {
8632        Msg += " ";
8633        Msg += getSubtargetFeatureName(ErrorInfo & Mask);
8634      }
8635      Mask <<= 1;
8636    }
8637    return Error(IDLoc, Msg);
8638  }
8639  case Match_InvalidOperand: {
8640    SMLoc ErrorLoc = IDLoc;
8641    if (ErrorInfo != ~0ULL) {
8642      if (ErrorInfo >= Operands.size())
8643        return Error(IDLoc, "too few operands for instruction");
8644
8645      ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8646      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8647    }
8648
8649    return Error(ErrorLoc, "invalid operand for instruction");
8650  }
8651  case Match_MnemonicFail:
8652    return Error(IDLoc, "invalid instruction",
8653                 ((ARMOperand &)*Operands[0]).getLocRange());
8654  case Match_RequiresNotITBlock:
8655    return Error(IDLoc, "flag setting instruction only valid outside IT block");
8656  case Match_RequiresITBlock:
8657    return Error(IDLoc, "instruction only valid inside IT block");
8658  case Match_RequiresV6:
8659    return Error(IDLoc, "instruction variant requires ARMv6 or later");
8660  case Match_RequiresThumb2:
8661    return Error(IDLoc, "instruction variant requires Thumb2");
8662  case Match_ImmRange0_15: {
8663    SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8664    if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8665    return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
8666  }
8667  case Match_ImmRange0_239: {
8668    SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8669    if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8670    return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8671  }
8672  case Match_AlignedMemoryRequiresNone:
8673  case Match_DupAlignedMemoryRequiresNone:
8674  case Match_AlignedMemoryRequires16:
8675  case Match_DupAlignedMemoryRequires16:
8676  case Match_AlignedMemoryRequires32:
8677  case Match_DupAlignedMemoryRequires32:
8678  case Match_AlignedMemoryRequires64:
8679  case Match_DupAlignedMemoryRequires64:
8680  case Match_AlignedMemoryRequires64or128:
8681  case Match_DupAlignedMemoryRequires64or128:
8682  case Match_AlignedMemoryRequires64or128or256:
8683  {
8684    SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc();
8685    if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8686    switch (MatchResult) {
8687      default:
8688        llvm_unreachable("Missing Match_Aligned type");
8689      case Match_AlignedMemoryRequiresNone:
8690      case Match_DupAlignedMemoryRequiresNone:
8691        return Error(ErrorLoc, "alignment must be omitted");
8692      case Match_AlignedMemoryRequires16:
8693      case Match_DupAlignedMemoryRequires16:
8694        return Error(ErrorLoc, "alignment must be 16 or omitted");
8695      case Match_AlignedMemoryRequires32:
8696      case Match_DupAlignedMemoryRequires32:
8697        return Error(ErrorLoc, "alignment must be 32 or omitted");
8698      case Match_AlignedMemoryRequires64:
8699      case Match_DupAlignedMemoryRequires64:
8700        return Error(ErrorLoc, "alignment must be 64 or omitted");
8701      case Match_AlignedMemoryRequires64or128:
8702      case Match_DupAlignedMemoryRequires64or128:
8703        return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
8704      case Match_AlignedMemoryRequires64or128or256:
8705        return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
8706    }
8707  }
8708  }
8709
8710  llvm_unreachable("Implement any new match types added!");
8711}
8712
8713/// parseDirective parses the arm specific directives
8714bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
8715  const MCObjectFileInfo::Environment Format =
8716    getContext().getObjectFileInfo()->getObjectFileType();
8717  bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8718  bool IsCOFF = Format == MCObjectFileInfo::IsCOFF;
8719
8720  StringRef IDVal = DirectiveID.getIdentifier();
8721  if (IDVal == ".word")
8722    return parseLiteralValues(4, DirectiveID.getLoc());
8723  else if (IDVal == ".short" || IDVal == ".hword")
8724    return parseLiteralValues(2, DirectiveID.getLoc());
8725  else if (IDVal == ".thumb")
8726    return parseDirectiveThumb(DirectiveID.getLoc());
8727  else if (IDVal == ".arm")
8728    return parseDirectiveARM(DirectiveID.getLoc());
8729  else if (IDVal == ".thumb_func")
8730    return parseDirectiveThumbFunc(DirectiveID.getLoc());
8731  else if (IDVal == ".code")
8732    return parseDirectiveCode(DirectiveID.getLoc());
8733  else if (IDVal == ".syntax")
8734    return parseDirectiveSyntax(DirectiveID.getLoc());
8735  else if (IDVal == ".unreq")
8736    return parseDirectiveUnreq(DirectiveID.getLoc());
8737  else if (IDVal == ".fnend")
8738    return parseDirectiveFnEnd(DirectiveID.getLoc());
8739  else if (IDVal == ".cantunwind")
8740    return parseDirectiveCantUnwind(DirectiveID.getLoc());
8741  else if (IDVal == ".personality")
8742    return parseDirectivePersonality(DirectiveID.getLoc());
8743  else if (IDVal == ".handlerdata")
8744    return parseDirectiveHandlerData(DirectiveID.getLoc());
8745  else if (IDVal == ".setfp")
8746    return parseDirectiveSetFP(DirectiveID.getLoc());
8747  else if (IDVal == ".pad")
8748    return parseDirectivePad(DirectiveID.getLoc());
8749  else if (IDVal == ".save")
8750    return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8751  else if (IDVal == ".vsave")
8752    return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8753  else if (IDVal == ".ltorg" || IDVal == ".pool")
8754    return parseDirectiveLtorg(DirectiveID.getLoc());
8755  else if (IDVal == ".even")
8756    return parseDirectiveEven(DirectiveID.getLoc());
8757  else if (IDVal == ".personalityindex")
8758    return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8759  else if (IDVal == ".unwind_raw")
8760    return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8761  else if (IDVal == ".movsp")
8762    return parseDirectiveMovSP(DirectiveID.getLoc());
8763  else if (IDVal == ".arch_extension")
8764    return parseDirectiveArchExtension(DirectiveID.getLoc());
8765  else if (IDVal == ".align")
8766    return parseDirectiveAlign(DirectiveID.getLoc());
8767  else if (IDVal == ".thumb_set")
8768    return parseDirectiveThumbSet(DirectiveID.getLoc());
8769
8770  if (!IsMachO && !IsCOFF) {
8771    if (IDVal == ".arch")
8772      return parseDirectiveArch(DirectiveID.getLoc());
8773    else if (IDVal == ".cpu")
8774      return parseDirectiveCPU(DirectiveID.getLoc());
8775    else if (IDVal == ".eabi_attribute")
8776      return parseDirectiveEabiAttr(DirectiveID.getLoc());
8777    else if (IDVal == ".fpu")
8778      return parseDirectiveFPU(DirectiveID.getLoc());
8779    else if (IDVal == ".fnstart")
8780      return parseDirectiveFnStart(DirectiveID.getLoc());
8781    else if (IDVal == ".inst")
8782      return parseDirectiveInst(DirectiveID.getLoc());
8783    else if (IDVal == ".inst.n")
8784      return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8785    else if (IDVal == ".inst.w")
8786      return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8787    else if (IDVal == ".object_arch")
8788      return parseDirectiveObjectArch(DirectiveID.getLoc());
8789    else if (IDVal == ".tlsdescseq")
8790      return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8791  }
8792
8793  return true;
8794}
8795
8796/// parseLiteralValues
8797///  ::= .hword expression [, expression]*
8798///  ::= .short expression [, expression]*
8799///  ::= .word expression [, expression]*
8800bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8801  MCAsmParser &Parser = getParser();
8802  if (getLexer().isNot(AsmToken::EndOfStatement)) {
8803    for (;;) {
8804      const MCExpr *Value;
8805      if (getParser().parseExpression(Value)) {
8806        Parser.eatToEndOfStatement();
8807        return false;
8808      }
8809
8810      getParser().getStreamer().EmitValue(Value, Size);
8811
8812      if (getLexer().is(AsmToken::EndOfStatement))
8813        break;
8814
8815      // FIXME: Improve diagnostic.
8816      if (getLexer().isNot(AsmToken::Comma)) {
8817        Error(L, "unexpected token in directive");
8818        return false;
8819      }
8820      Parser.Lex();
8821    }
8822  }
8823
8824  Parser.Lex();
8825  return false;
8826}
8827
8828/// parseDirectiveThumb
8829///  ::= .thumb
8830bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8831  MCAsmParser &Parser = getParser();
8832  if (getLexer().isNot(AsmToken::EndOfStatement)) {
8833    Error(L, "unexpected token in directive");
8834    return false;
8835  }
8836  Parser.Lex();
8837
8838  if (!hasThumb()) {
8839    Error(L, "target does not support Thumb mode");
8840    return false;
8841  }
8842
8843  if (!isThumb())
8844    SwitchMode();
8845
8846  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8847  return false;
8848}
8849
8850/// parseDirectiveARM
8851///  ::= .arm
8852bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8853  MCAsmParser &Parser = getParser();
8854  if (getLexer().isNot(AsmToken::EndOfStatement)) {
8855    Error(L, "unexpected token in directive");
8856    return false;
8857  }
8858  Parser.Lex();
8859
8860  if (!hasARM()) {
8861    Error(L, "target does not support ARM mode");
8862    return false;
8863  }
8864
8865  if (isThumb())
8866    SwitchMode();
8867
8868  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8869  return false;
8870}
8871
8872void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8873  if (NextSymbolIsThumb) {
8874    getParser().getStreamer().EmitThumbFunc(Symbol);
8875    NextSymbolIsThumb = false;
8876  }
8877}
8878
8879/// parseDirectiveThumbFunc
8880///  ::= .thumbfunc symbol_name
8881bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8882  MCAsmParser &Parser = getParser();
8883  const auto Format = getContext().getObjectFileInfo()->getObjectFileType();
8884  bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8885
8886  // Darwin asm has (optionally) function name after .thumb_func direction
8887  // ELF doesn't
8888  if (IsMachO) {
8889    const AsmToken &Tok = Parser.getTok();
8890    if (Tok.isNot(AsmToken::EndOfStatement)) {
8891      if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8892        Error(L, "unexpected token in .thumb_func directive");
8893        return false;
8894      }
8895
8896      MCSymbol *Func =
8897          getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8898      getParser().getStreamer().EmitThumbFunc(Func);
8899      Parser.Lex(); // Consume the identifier token.
8900      return false;
8901    }
8902  }
8903
8904  if (getLexer().isNot(AsmToken::EndOfStatement)) {
8905    Error(Parser.getTok().getLoc(), "unexpected token in directive");
8906    Parser.eatToEndOfStatement();
8907    return false;
8908  }
8909
8910  NextSymbolIsThumb = true;
8911  return false;
8912}
8913
8914/// parseDirectiveSyntax
8915///  ::= .syntax unified | divided
8916bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8917  MCAsmParser &Parser = getParser();
8918  const AsmToken &Tok = Parser.getTok();
8919  if (Tok.isNot(AsmToken::Identifier)) {
8920    Error(L, "unexpected token in .syntax directive");
8921    return false;
8922  }
8923
8924  StringRef Mode = Tok.getString();
8925  if (Mode == "unified" || Mode == "UNIFIED") {
8926    Parser.Lex();
8927  } else if (Mode == "divided" || Mode == "DIVIDED") {
8928    Error(L, "'.syntax divided' arm asssembly not supported");
8929    return false;
8930  } else {
8931    Error(L, "unrecognized syntax mode in .syntax directive");
8932    return false;
8933  }
8934
8935  if (getLexer().isNot(AsmToken::EndOfStatement)) {
8936    Error(Parser.getTok().getLoc(), "unexpected token in directive");
8937    return false;
8938  }
8939  Parser.Lex();
8940
8941  // TODO tell the MC streamer the mode
8942  // getParser().getStreamer().Emit???();
8943  return false;
8944}
8945
8946/// parseDirectiveCode
8947///  ::= .code 16 | 32
8948bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8949  MCAsmParser &Parser = getParser();
8950  const AsmToken &Tok = Parser.getTok();
8951  if (Tok.isNot(AsmToken::Integer)) {
8952    Error(L, "unexpected token in .code directive");
8953    return false;
8954  }
8955  int64_t Val = Parser.getTok().getIntVal();
8956  if (Val != 16 && Val != 32) {
8957    Error(L, "invalid operand to .code directive");
8958    return false;
8959  }
8960  Parser.Lex();
8961
8962  if (getLexer().isNot(AsmToken::EndOfStatement)) {
8963    Error(Parser.getTok().getLoc(), "unexpected token in directive");
8964    return false;
8965  }
8966  Parser.Lex();
8967
8968  if (Val == 16) {
8969    if (!hasThumb()) {
8970      Error(L, "target does not support Thumb mode");
8971      return false;
8972    }
8973
8974    if (!isThumb())
8975      SwitchMode();
8976    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8977  } else {
8978    if (!hasARM()) {
8979      Error(L, "target does not support ARM mode");
8980      return false;
8981    }
8982
8983    if (isThumb())
8984      SwitchMode();
8985    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8986  }
8987
8988  return false;
8989}
8990
8991/// parseDirectiveReq
8992///  ::= name .req registername
8993bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8994  MCAsmParser &Parser = getParser();
8995  Parser.Lex(); // Eat the '.req' token.
8996  unsigned Reg;
8997  SMLoc SRegLoc, ERegLoc;
8998  if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8999    Parser.eatToEndOfStatement();
9000    Error(SRegLoc, "register name expected");
9001    return false;
9002  }
9003
9004  // Shouldn't be anything else.
9005  if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
9006    Parser.eatToEndOfStatement();
9007    Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
9008    return false;
9009  }
9010
9011  Parser.Lex(); // Consume the EndOfStatement
9012
9013  if (!RegisterReqs.insert(std::make_pair(Name, Reg)).second) {
9014    Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
9015    return false;
9016  }
9017
9018  return false;
9019}
9020
9021/// parseDirectiveUneq
9022///  ::= .unreq registername
9023bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
9024  MCAsmParser &Parser = getParser();
9025  if (Parser.getTok().isNot(AsmToken::Identifier)) {
9026    Parser.eatToEndOfStatement();
9027    Error(L, "unexpected input in .unreq directive.");
9028    return false;
9029  }
9030  RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
9031  Parser.Lex(); // Eat the identifier.
9032  return false;
9033}
9034
9035/// parseDirectiveArch
9036///  ::= .arch token
9037bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
9038  StringRef Arch = getParser().parseStringToEndOfStatement().trim();
9039
9040  unsigned ID = StringSwitch<unsigned>(Arch)
9041#define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
9042    .Case(NAME, ARM::ID)
9043#define ARM_ARCH_ALIAS(NAME, ID) \
9044    .Case(NAME, ARM::ID)
9045#include "MCTargetDesc/ARMArchName.def"
9046    .Default(ARM::INVALID_ARCH);
9047
9048  if (ID == ARM::INVALID_ARCH) {
9049    Error(L, "Unknown arch name");
9050    return false;
9051  }
9052
9053  getTargetStreamer().emitArch(ID);
9054  return false;
9055}
9056
9057/// parseDirectiveEabiAttr
9058///  ::= .eabi_attribute int, int [, "str"]
9059///  ::= .eabi_attribute Tag_name, int [, "str"]
9060bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
9061  MCAsmParser &Parser = getParser();
9062  int64_t Tag;
9063  SMLoc TagLoc;
9064  TagLoc = Parser.getTok().getLoc();
9065  if (Parser.getTok().is(AsmToken::Identifier)) {
9066    StringRef Name = Parser.getTok().getIdentifier();
9067    Tag = ARMBuildAttrs::AttrTypeFromString(Name);
9068    if (Tag == -1) {
9069      Error(TagLoc, "attribute name not recognised: " + Name);
9070      Parser.eatToEndOfStatement();
9071      return false;
9072    }
9073    Parser.Lex();
9074  } else {
9075    const MCExpr *AttrExpr;
9076
9077    TagLoc = Parser.getTok().getLoc();
9078    if (Parser.parseExpression(AttrExpr)) {
9079      Parser.eatToEndOfStatement();
9080      return false;
9081    }
9082
9083    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
9084    if (!CE) {
9085      Error(TagLoc, "expected numeric constant");
9086      Parser.eatToEndOfStatement();
9087      return false;
9088    }
9089
9090    Tag = CE->getValue();
9091  }
9092
9093  if (Parser.getTok().isNot(AsmToken::Comma)) {
9094    Error(Parser.getTok().getLoc(), "comma expected");
9095    Parser.eatToEndOfStatement();
9096    return false;
9097  }
9098  Parser.Lex(); // skip comma
9099
9100  StringRef StringValue = "";
9101  bool IsStringValue = false;
9102
9103  int64_t IntegerValue = 0;
9104  bool IsIntegerValue = false;
9105
9106  if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
9107    IsStringValue = true;
9108  else if (Tag == ARMBuildAttrs::compatibility) {
9109    IsStringValue = true;
9110    IsIntegerValue = true;
9111  } else if (Tag < 32 || Tag % 2 == 0)
9112    IsIntegerValue = true;
9113  else if (Tag % 2 == 1)
9114    IsStringValue = true;
9115  else
9116    llvm_unreachable("invalid tag type");
9117
9118  if (IsIntegerValue) {
9119    const MCExpr *ValueExpr;
9120    SMLoc ValueExprLoc = Parser.getTok().getLoc();
9121    if (Parser.parseExpression(ValueExpr)) {
9122      Parser.eatToEndOfStatement();
9123      return false;
9124    }
9125
9126    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
9127    if (!CE) {
9128      Error(ValueExprLoc, "expected numeric constant");
9129      Parser.eatToEndOfStatement();
9130      return false;
9131    }
9132
9133    IntegerValue = CE->getValue();
9134  }
9135
9136  if (Tag == ARMBuildAttrs::compatibility) {
9137    if (Parser.getTok().isNot(AsmToken::Comma))
9138      IsStringValue = false;
9139    if (Parser.getTok().isNot(AsmToken::Comma)) {
9140      Error(Parser.getTok().getLoc(), "comma expected");
9141      Parser.eatToEndOfStatement();
9142      return false;
9143    } else {
9144       Parser.Lex();
9145    }
9146  }
9147
9148  if (IsStringValue) {
9149    if (Parser.getTok().isNot(AsmToken::String)) {
9150      Error(Parser.getTok().getLoc(), "bad string constant");
9151      Parser.eatToEndOfStatement();
9152      return false;
9153    }
9154
9155    StringValue = Parser.getTok().getStringContents();
9156    Parser.Lex();
9157  }
9158
9159  if (IsIntegerValue && IsStringValue) {
9160    assert(Tag == ARMBuildAttrs::compatibility);
9161    getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
9162  } else if (IsIntegerValue)
9163    getTargetStreamer().emitAttribute(Tag, IntegerValue);
9164  else if (IsStringValue)
9165    getTargetStreamer().emitTextAttribute(Tag, StringValue);
9166  return false;
9167}
9168
9169/// parseDirectiveCPU
9170///  ::= .cpu str
9171bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
9172  StringRef CPU = getParser().parseStringToEndOfStatement().trim();
9173  getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
9174
9175  if (!STI.isCPUStringValid(CPU)) {
9176    Error(L, "Unknown CPU name");
9177    return false;
9178  }
9179
9180  // FIXME: This switches the CPU features globally, therefore it might
9181  // happen that code you would not expect to assemble will. For details
9182  // see: http://llvm.org/bugs/show_bug.cgi?id=20757
9183  STI.InitMCProcessorInfo(CPU, "");
9184  STI.InitCPUSchedModel(CPU);
9185  unsigned FB = ComputeAvailableFeatures(STI.getFeatureBits());
9186  setAvailableFeatures(FB);
9187
9188  return false;
9189}
9190
9191// FIXME: This is duplicated in getARMFPUFeatures() in
9192// tools/clang/lib/Driver/Tools.cpp
9193static const struct {
9194  const unsigned ID;
9195  const uint64_t Enabled;
9196  const uint64_t Disabled;
9197} FPUs[] = {
9198    {/* ID */ ARM::VFP,
9199     /* Enabled */ ARM::FeatureVFP2,
9200     /* Disabled */ ARM::FeatureNEON},
9201    {/* ID */ ARM::VFPV2,
9202     /* Enabled */ ARM::FeatureVFP2,
9203     /* Disabled */ ARM::FeatureNEON},
9204    {/* ID */ ARM::VFPV3,
9205     /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3,
9206     /* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
9207    {/* ID */ ARM::VFPV3_D16,
9208     /* Enable */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureD16,
9209     /* Disabled */ ARM::FeatureNEON},
9210    {/* ID */ ARM::VFPV4,
9211     /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4,
9212     /* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
9213    {/* ID */ ARM::VFPV4_D16,
9214     /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9215         ARM::FeatureD16,
9216     /* Disabled */ ARM::FeatureNEON},
9217    {/* ID */ ARM::FPV5_D16,
9218     /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9219         ARM::FeatureFPARMv8 | ARM::FeatureD16,
9220     /* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto},
9221    {/* ID */ ARM::FP_ARMV8,
9222     /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9223         ARM::FeatureFPARMv8,
9224     /* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto | ARM::FeatureD16},
9225    {/* ID */ ARM::NEON,
9226     /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureNEON,
9227     /* Disabled */ ARM::FeatureD16},
9228    {/* ID */ ARM::NEON_VFPV4,
9229     /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9230         ARM::FeatureNEON,
9231     /* Disabled */ ARM::FeatureD16},
9232    {/* ID */ ARM::NEON_FP_ARMV8,
9233     /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9234         ARM::FeatureFPARMv8 | ARM::FeatureNEON,
9235     /* Disabled */ ARM::FeatureCrypto | ARM::FeatureD16},
9236    {/* ID */ ARM::CRYPTO_NEON_FP_ARMV8,
9237     /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9238         ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto,
9239     /* Disabled */ ARM::FeatureD16},
9240    {ARM::SOFTVFP, 0, 0},
9241};
9242
9243/// parseDirectiveFPU
9244///  ::= .fpu str
9245bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
9246  StringRef FPU = getParser().parseStringToEndOfStatement().trim();
9247
9248  unsigned ID = StringSwitch<unsigned>(FPU)
9249#define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
9250#include "ARMFPUName.def"
9251    .Default(ARM::INVALID_FPU);
9252
9253  if (ID == ARM::INVALID_FPU) {
9254    Error(L, "Unknown FPU name");
9255    return false;
9256  }
9257
9258  for (const auto &Entry : FPUs) {
9259    if (Entry.ID != ID)
9260      continue;
9261
9262    // Need to toggle features that should be on but are off and that
9263    // should off but are on.
9264    uint64_t Toggle = (Entry.Enabled & ~STI.getFeatureBits()) |
9265                      (Entry.Disabled & STI.getFeatureBits());
9266    setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(Toggle)));
9267    break;
9268  }
9269
9270  getTargetStreamer().emitFPU(ID);
9271  return false;
9272}
9273
9274/// parseDirectiveFnStart
9275///  ::= .fnstart
9276bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
9277  if (UC.hasFnStart()) {
9278    Error(L, ".fnstart starts before the end of previous one");
9279    UC.emitFnStartLocNotes();
9280    return false;
9281  }
9282
9283  // Reset the unwind directives parser state
9284  UC.reset();
9285
9286  getTargetStreamer().emitFnStart();
9287
9288  UC.recordFnStart(L);
9289  return false;
9290}
9291
9292/// parseDirectiveFnEnd
9293///  ::= .fnend
9294bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
9295  // Check the ordering of unwind directives
9296  if (!UC.hasFnStart()) {
9297    Error(L, ".fnstart must precede .fnend directive");
9298    return false;
9299  }
9300
9301  // Reset the unwind directives parser state
9302  getTargetStreamer().emitFnEnd();
9303
9304  UC.reset();
9305  return false;
9306}
9307
9308/// parseDirectiveCantUnwind
9309///  ::= .cantunwind
9310bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
9311  UC.recordCantUnwind(L);
9312
9313  // Check the ordering of unwind directives
9314  if (!UC.hasFnStart()) {
9315    Error(L, ".fnstart must precede .cantunwind directive");
9316    return false;
9317  }
9318  if (UC.hasHandlerData()) {
9319    Error(L, ".cantunwind can't be used with .handlerdata directive");
9320    UC.emitHandlerDataLocNotes();
9321    return false;
9322  }
9323  if (UC.hasPersonality()) {
9324    Error(L, ".cantunwind can't be used with .personality directive");
9325    UC.emitPersonalityLocNotes();
9326    return false;
9327  }
9328
9329  getTargetStreamer().emitCantUnwind();
9330  return false;
9331}
9332
9333/// parseDirectivePersonality
9334///  ::= .personality name
9335bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
9336  MCAsmParser &Parser = getParser();
9337  bool HasExistingPersonality = UC.hasPersonality();
9338
9339  UC.recordPersonality(L);
9340
9341  // Check the ordering of unwind directives
9342  if (!UC.hasFnStart()) {
9343    Error(L, ".fnstart must precede .personality directive");
9344    return false;
9345  }
9346  if (UC.cantUnwind()) {
9347    Error(L, ".personality can't be used with .cantunwind directive");
9348    UC.emitCantUnwindLocNotes();
9349    return false;
9350  }
9351  if (UC.hasHandlerData()) {
9352    Error(L, ".personality must precede .handlerdata directive");
9353    UC.emitHandlerDataLocNotes();
9354    return false;
9355  }
9356  if (HasExistingPersonality) {
9357    Parser.eatToEndOfStatement();
9358    Error(L, "multiple personality directives");
9359    UC.emitPersonalityLocNotes();
9360    return false;
9361  }
9362
9363  // Parse the name of the personality routine
9364  if (Parser.getTok().isNot(AsmToken::Identifier)) {
9365    Parser.eatToEndOfStatement();
9366    Error(L, "unexpected input in .personality directive.");
9367    return false;
9368  }
9369  StringRef Name(Parser.getTok().getIdentifier());
9370  Parser.Lex();
9371
9372  MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
9373  getTargetStreamer().emitPersonality(PR);
9374  return false;
9375}
9376
9377/// parseDirectiveHandlerData
9378///  ::= .handlerdata
9379bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
9380  UC.recordHandlerData(L);
9381
9382  // Check the ordering of unwind directives
9383  if (!UC.hasFnStart()) {
9384    Error(L, ".fnstart must precede .personality directive");
9385    return false;
9386  }
9387  if (UC.cantUnwind()) {
9388    Error(L, ".handlerdata can't be used with .cantunwind directive");
9389    UC.emitCantUnwindLocNotes();
9390    return false;
9391  }
9392
9393  getTargetStreamer().emitHandlerData();
9394  return false;
9395}
9396
9397/// parseDirectiveSetFP
9398///  ::= .setfp fpreg, spreg [, offset]
9399bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
9400  MCAsmParser &Parser = getParser();
9401  // Check the ordering of unwind directives
9402  if (!UC.hasFnStart()) {
9403    Error(L, ".fnstart must precede .setfp directive");
9404    return false;
9405  }
9406  if (UC.hasHandlerData()) {
9407    Error(L, ".setfp must precede .handlerdata directive");
9408    return false;
9409  }
9410
9411  // Parse fpreg
9412  SMLoc FPRegLoc = Parser.getTok().getLoc();
9413  int FPReg = tryParseRegister();
9414  if (FPReg == -1) {
9415    Error(FPRegLoc, "frame pointer register expected");
9416    return false;
9417  }
9418
9419  // Consume comma
9420  if (Parser.getTok().isNot(AsmToken::Comma)) {
9421    Error(Parser.getTok().getLoc(), "comma expected");
9422    return false;
9423  }
9424  Parser.Lex(); // skip comma
9425
9426  // Parse spreg
9427  SMLoc SPRegLoc = Parser.getTok().getLoc();
9428  int SPReg = tryParseRegister();
9429  if (SPReg == -1) {
9430    Error(SPRegLoc, "stack pointer register expected");
9431    return false;
9432  }
9433
9434  if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
9435    Error(SPRegLoc, "register should be either $sp or the latest fp register");
9436    return false;
9437  }
9438
9439  // Update the frame pointer register
9440  UC.saveFPReg(FPReg);
9441
9442  // Parse offset
9443  int64_t Offset = 0;
9444  if (Parser.getTok().is(AsmToken::Comma)) {
9445    Parser.Lex(); // skip comma
9446
9447    if (Parser.getTok().isNot(AsmToken::Hash) &&
9448        Parser.getTok().isNot(AsmToken::Dollar)) {
9449      Error(Parser.getTok().getLoc(), "'#' expected");
9450      return false;
9451    }
9452    Parser.Lex(); // skip hash token.
9453
9454    const MCExpr *OffsetExpr;
9455    SMLoc ExLoc = Parser.getTok().getLoc();
9456    SMLoc EndLoc;
9457    if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9458      Error(ExLoc, "malformed setfp offset");
9459      return false;
9460    }
9461    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9462    if (!CE) {
9463      Error(ExLoc, "setfp offset must be an immediate");
9464      return false;
9465    }
9466
9467    Offset = CE->getValue();
9468  }
9469
9470  getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
9471                                static_cast<unsigned>(SPReg), Offset);
9472  return false;
9473}
9474
9475/// parseDirective
9476///  ::= .pad offset
9477bool ARMAsmParser::parseDirectivePad(SMLoc L) {
9478  MCAsmParser &Parser = getParser();
9479  // Check the ordering of unwind directives
9480  if (!UC.hasFnStart()) {
9481    Error(L, ".fnstart must precede .pad directive");
9482    return false;
9483  }
9484  if (UC.hasHandlerData()) {
9485    Error(L, ".pad must precede .handlerdata directive");
9486    return false;
9487  }
9488
9489  // Parse the offset
9490  if (Parser.getTok().isNot(AsmToken::Hash) &&
9491      Parser.getTok().isNot(AsmToken::Dollar)) {
9492    Error(Parser.getTok().getLoc(), "'#' expected");
9493    return false;
9494  }
9495  Parser.Lex(); // skip hash token.
9496
9497  const MCExpr *OffsetExpr;
9498  SMLoc ExLoc = Parser.getTok().getLoc();
9499  SMLoc EndLoc;
9500  if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9501    Error(ExLoc, "malformed pad offset");
9502    return false;
9503  }
9504  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9505  if (!CE) {
9506    Error(ExLoc, "pad offset must be an immediate");
9507    return false;
9508  }
9509
9510  getTargetStreamer().emitPad(CE->getValue());
9511  return false;
9512}
9513
9514/// parseDirectiveRegSave
9515///  ::= .save  { registers }
9516///  ::= .vsave { registers }
9517bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
9518  // Check the ordering of unwind directives
9519  if (!UC.hasFnStart()) {
9520    Error(L, ".fnstart must precede .save or .vsave directives");
9521    return false;
9522  }
9523  if (UC.hasHandlerData()) {
9524    Error(L, ".save or .vsave must precede .handlerdata directive");
9525    return false;
9526  }
9527
9528  // RAII object to make sure parsed operands are deleted.
9529  SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
9530
9531  // Parse the register list
9532  if (parseRegisterList(Operands))
9533    return false;
9534  ARMOperand &Op = (ARMOperand &)*Operands[0];
9535  if (!IsVector && !Op.isRegList()) {
9536    Error(L, ".save expects GPR registers");
9537    return false;
9538  }
9539  if (IsVector && !Op.isDPRRegList()) {
9540    Error(L, ".vsave expects DPR registers");
9541    return false;
9542  }
9543
9544  getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
9545  return false;
9546}
9547
9548/// parseDirectiveInst
9549///  ::= .inst opcode [, ...]
9550///  ::= .inst.n opcode [, ...]
9551///  ::= .inst.w opcode [, ...]
9552bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
9553  MCAsmParser &Parser = getParser();
9554  int Width;
9555
9556  if (isThumb()) {
9557    switch (Suffix) {
9558    case 'n':
9559      Width = 2;
9560      break;
9561    case 'w':
9562      Width = 4;
9563      break;
9564    default:
9565      Parser.eatToEndOfStatement();
9566      Error(Loc, "cannot determine Thumb instruction size, "
9567                 "use inst.n/inst.w instead");
9568      return false;
9569    }
9570  } else {
9571    if (Suffix) {
9572      Parser.eatToEndOfStatement();
9573      Error(Loc, "width suffixes are invalid in ARM mode");
9574      return false;
9575    }
9576    Width = 4;
9577  }
9578
9579  if (getLexer().is(AsmToken::EndOfStatement)) {
9580    Parser.eatToEndOfStatement();
9581    Error(Loc, "expected expression following directive");
9582    return false;
9583  }
9584
9585  for (;;) {
9586    const MCExpr *Expr;
9587
9588    if (getParser().parseExpression(Expr)) {
9589      Error(Loc, "expected expression");
9590      return false;
9591    }
9592
9593    const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
9594    if (!Value) {
9595      Error(Loc, "expected constant expression");
9596      return false;
9597    }
9598
9599    switch (Width) {
9600    case 2:
9601      if (Value->getValue() > 0xffff) {
9602        Error(Loc, "inst.n operand is too big, use inst.w instead");
9603        return false;
9604      }
9605      break;
9606    case 4:
9607      if (Value->getValue() > 0xffffffff) {
9608        Error(Loc,
9609              StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
9610        return false;
9611      }
9612      break;
9613    default:
9614      llvm_unreachable("only supported widths are 2 and 4");
9615    }
9616
9617    getTargetStreamer().emitInst(Value->getValue(), Suffix);
9618
9619    if (getLexer().is(AsmToken::EndOfStatement))
9620      break;
9621
9622    if (getLexer().isNot(AsmToken::Comma)) {
9623      Error(Loc, "unexpected token in directive");
9624      return false;
9625    }
9626
9627    Parser.Lex();
9628  }
9629
9630  Parser.Lex();
9631  return false;
9632}
9633
9634/// parseDirectiveLtorg
9635///  ::= .ltorg | .pool
9636bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
9637  getTargetStreamer().emitCurrentConstantPool();
9638  return false;
9639}
9640
9641bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
9642  const MCSection *Section = getStreamer().getCurrentSection().first;
9643
9644  if (getLexer().isNot(AsmToken::EndOfStatement)) {
9645    TokError("unexpected token in directive");
9646    return false;
9647  }
9648
9649  if (!Section) {
9650    getStreamer().InitSections(false);
9651    Section = getStreamer().getCurrentSection().first;
9652  }
9653
9654  assert(Section && "must have section to emit alignment");
9655  if (Section->UseCodeAlign())
9656    getStreamer().EmitCodeAlignment(2);
9657  else
9658    getStreamer().EmitValueToAlignment(2);
9659
9660  return false;
9661}
9662
9663/// parseDirectivePersonalityIndex
9664///   ::= .personalityindex index
9665bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
9666  MCAsmParser &Parser = getParser();
9667  bool HasExistingPersonality = UC.hasPersonality();
9668
9669  UC.recordPersonalityIndex(L);
9670
9671  if (!UC.hasFnStart()) {
9672    Parser.eatToEndOfStatement();
9673    Error(L, ".fnstart must precede .personalityindex directive");
9674    return false;
9675  }
9676  if (UC.cantUnwind()) {
9677    Parser.eatToEndOfStatement();
9678    Error(L, ".personalityindex cannot be used with .cantunwind");
9679    UC.emitCantUnwindLocNotes();
9680    return false;
9681  }
9682  if (UC.hasHandlerData()) {
9683    Parser.eatToEndOfStatement();
9684    Error(L, ".personalityindex must precede .handlerdata directive");
9685    UC.emitHandlerDataLocNotes();
9686    return false;
9687  }
9688  if (HasExistingPersonality) {
9689    Parser.eatToEndOfStatement();
9690    Error(L, "multiple personality directives");
9691    UC.emitPersonalityLocNotes();
9692    return false;
9693  }
9694
9695  const MCExpr *IndexExpression;
9696  SMLoc IndexLoc = Parser.getTok().getLoc();
9697  if (Parser.parseExpression(IndexExpression)) {
9698    Parser.eatToEndOfStatement();
9699    return false;
9700  }
9701
9702  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
9703  if (!CE) {
9704    Parser.eatToEndOfStatement();
9705    Error(IndexLoc, "index must be a constant number");
9706    return false;
9707  }
9708  if (CE->getValue() < 0 ||
9709      CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
9710    Parser.eatToEndOfStatement();
9711    Error(IndexLoc, "personality routine index should be in range [0-3]");
9712    return false;
9713  }
9714
9715  getTargetStreamer().emitPersonalityIndex(CE->getValue());
9716  return false;
9717}
9718
9719/// parseDirectiveUnwindRaw
9720///   ::= .unwind_raw offset, opcode [, opcode...]
9721bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
9722  MCAsmParser &Parser = getParser();
9723  if (!UC.hasFnStart()) {
9724    Parser.eatToEndOfStatement();
9725    Error(L, ".fnstart must precede .unwind_raw directives");
9726    return false;
9727  }
9728
9729  int64_t StackOffset;
9730
9731  const MCExpr *OffsetExpr;
9732  SMLoc OffsetLoc = getLexer().getLoc();
9733  if (getLexer().is(AsmToken::EndOfStatement) ||
9734      getParser().parseExpression(OffsetExpr)) {
9735    Error(OffsetLoc, "expected expression");
9736    Parser.eatToEndOfStatement();
9737    return false;
9738  }
9739
9740  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9741  if (!CE) {
9742    Error(OffsetLoc, "offset must be a constant");
9743    Parser.eatToEndOfStatement();
9744    return false;
9745  }
9746
9747  StackOffset = CE->getValue();
9748
9749  if (getLexer().isNot(AsmToken::Comma)) {
9750    Error(getLexer().getLoc(), "expected comma");
9751    Parser.eatToEndOfStatement();
9752    return false;
9753  }
9754  Parser.Lex();
9755
9756  SmallVector<uint8_t, 16> Opcodes;
9757  for (;;) {
9758    const MCExpr *OE;
9759
9760    SMLoc OpcodeLoc = getLexer().getLoc();
9761    if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
9762      Error(OpcodeLoc, "expected opcode expression");
9763      Parser.eatToEndOfStatement();
9764      return false;
9765    }
9766
9767    const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
9768    if (!OC) {
9769      Error(OpcodeLoc, "opcode value must be a constant");
9770      Parser.eatToEndOfStatement();
9771      return false;
9772    }
9773
9774    const int64_t Opcode = OC->getValue();
9775    if (Opcode & ~0xff) {
9776      Error(OpcodeLoc, "invalid opcode");
9777      Parser.eatToEndOfStatement();
9778      return false;
9779    }
9780
9781    Opcodes.push_back(uint8_t(Opcode));
9782
9783    if (getLexer().is(AsmToken::EndOfStatement))
9784      break;
9785
9786    if (getLexer().isNot(AsmToken::Comma)) {
9787      Error(getLexer().getLoc(), "unexpected token in directive");
9788      Parser.eatToEndOfStatement();
9789      return false;
9790    }
9791
9792    Parser.Lex();
9793  }
9794
9795  getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
9796
9797  Parser.Lex();
9798  return false;
9799}
9800
9801/// parseDirectiveTLSDescSeq
9802///   ::= .tlsdescseq tls-variable
9803bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
9804  MCAsmParser &Parser = getParser();
9805
9806  if (getLexer().isNot(AsmToken::Identifier)) {
9807    TokError("expected variable after '.tlsdescseq' directive");
9808    Parser.eatToEndOfStatement();
9809    return false;
9810  }
9811
9812  const MCSymbolRefExpr *SRE =
9813    MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(),
9814                            MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
9815  Lex();
9816
9817  if (getLexer().isNot(AsmToken::EndOfStatement)) {
9818    Error(Parser.getTok().getLoc(), "unexpected token");
9819    Parser.eatToEndOfStatement();
9820    return false;
9821  }
9822
9823  getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
9824  return false;
9825}
9826
9827/// parseDirectiveMovSP
9828///  ::= .movsp reg [, #offset]
9829bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
9830  MCAsmParser &Parser = getParser();
9831  if (!UC.hasFnStart()) {
9832    Parser.eatToEndOfStatement();
9833    Error(L, ".fnstart must precede .movsp directives");
9834    return false;
9835  }
9836  if (UC.getFPReg() != ARM::SP) {
9837    Parser.eatToEndOfStatement();
9838    Error(L, "unexpected .movsp directive");
9839    return false;
9840  }
9841
9842  SMLoc SPRegLoc = Parser.getTok().getLoc();
9843  int SPReg = tryParseRegister();
9844  if (SPReg == -1) {
9845    Parser.eatToEndOfStatement();
9846    Error(SPRegLoc, "register expected");
9847    return false;
9848  }
9849
9850  if (SPReg == ARM::SP || SPReg == ARM::PC) {
9851    Parser.eatToEndOfStatement();
9852    Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
9853    return false;
9854  }
9855
9856  int64_t Offset = 0;
9857  if (Parser.getTok().is(AsmToken::Comma)) {
9858    Parser.Lex();
9859
9860    if (Parser.getTok().isNot(AsmToken::Hash)) {
9861      Error(Parser.getTok().getLoc(), "expected #constant");
9862      Parser.eatToEndOfStatement();
9863      return false;
9864    }
9865    Parser.Lex();
9866
9867    const MCExpr *OffsetExpr;
9868    SMLoc OffsetLoc = Parser.getTok().getLoc();
9869    if (Parser.parseExpression(OffsetExpr)) {
9870      Parser.eatToEndOfStatement();
9871      Error(OffsetLoc, "malformed offset expression");
9872      return false;
9873    }
9874
9875    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9876    if (!CE) {
9877      Parser.eatToEndOfStatement();
9878      Error(OffsetLoc, "offset must be an immediate constant");
9879      return false;
9880    }
9881
9882    Offset = CE->getValue();
9883  }
9884
9885  getTargetStreamer().emitMovSP(SPReg, Offset);
9886  UC.saveFPReg(SPReg);
9887
9888  return false;
9889}
9890
9891/// parseDirectiveObjectArch
9892///   ::= .object_arch name
9893bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9894  MCAsmParser &Parser = getParser();
9895  if (getLexer().isNot(AsmToken::Identifier)) {
9896    Error(getLexer().getLoc(), "unexpected token");
9897    Parser.eatToEndOfStatement();
9898    return false;
9899  }
9900
9901  StringRef Arch = Parser.getTok().getString();
9902  SMLoc ArchLoc = Parser.getTok().getLoc();
9903  getLexer().Lex();
9904
9905  unsigned ID = StringSwitch<unsigned>(Arch)
9906#define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
9907    .Case(NAME, ARM::ID)
9908#define ARM_ARCH_ALIAS(NAME, ID) \
9909    .Case(NAME, ARM::ID)
9910#include "MCTargetDesc/ARMArchName.def"
9911#undef ARM_ARCH_NAME
9912#undef ARM_ARCH_ALIAS
9913    .Default(ARM::INVALID_ARCH);
9914
9915  if (ID == ARM::INVALID_ARCH) {
9916    Error(ArchLoc, "unknown architecture '" + Arch + "'");
9917    Parser.eatToEndOfStatement();
9918    return false;
9919  }
9920
9921  getTargetStreamer().emitObjectArch(ID);
9922
9923  if (getLexer().isNot(AsmToken::EndOfStatement)) {
9924    Error(getLexer().getLoc(), "unexpected token");
9925    Parser.eatToEndOfStatement();
9926  }
9927
9928  return false;
9929}
9930
9931/// parseDirectiveAlign
9932///   ::= .align
9933bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
9934  // NOTE: if this is not the end of the statement, fall back to the target
9935  // agnostic handling for this directive which will correctly handle this.
9936  if (getLexer().isNot(AsmToken::EndOfStatement))
9937    return true;
9938
9939  // '.align' is target specifically handled to mean 2**2 byte alignment.
9940  if (getStreamer().getCurrentSection().first->UseCodeAlign())
9941    getStreamer().EmitCodeAlignment(4, 0);
9942  else
9943    getStreamer().EmitValueToAlignment(4, 0, 1, 0);
9944
9945  return false;
9946}
9947
9948/// parseDirectiveThumbSet
9949///  ::= .thumb_set name, value
9950bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
9951  MCAsmParser &Parser = getParser();
9952
9953  StringRef Name;
9954  if (Parser.parseIdentifier(Name)) {
9955    TokError("expected identifier after '.thumb_set'");
9956    Parser.eatToEndOfStatement();
9957    return false;
9958  }
9959
9960  if (getLexer().isNot(AsmToken::Comma)) {
9961    TokError("expected comma after name '" + Name + "'");
9962    Parser.eatToEndOfStatement();
9963    return false;
9964  }
9965  Lex();
9966
9967  const MCExpr *Value;
9968  if (Parser.parseExpression(Value)) {
9969    TokError("missing expression");
9970    Parser.eatToEndOfStatement();
9971    return false;
9972  }
9973
9974  if (getLexer().isNot(AsmToken::EndOfStatement)) {
9975    TokError("unexpected token");
9976    Parser.eatToEndOfStatement();
9977    return false;
9978  }
9979  Lex();
9980
9981  MCSymbol *Alias = getContext().GetOrCreateSymbol(Name);
9982  getTargetStreamer().emitThumbSet(Alias, Value);
9983  return false;
9984}
9985
9986/// Force static initialization.
9987extern "C" void LLVMInitializeARMAsmParser() {
9988  RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget);
9989  RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget);
9990  RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget);
9991  RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget);
9992}
9993
9994#define GET_REGISTER_MATCHER
9995#define GET_SUBTARGET_FEATURE_NAME
9996#define GET_MATCHER_IMPLEMENTATION
9997#include "ARMGenAsmMatcher.inc"
9998
9999static const struct {
10000  const char *Name;
10001  const unsigned ArchCheck;
10002  const uint64_t Features;
10003} Extensions[] = {
10004  { "crc", Feature_HasV8, ARM::FeatureCRC },
10005  { "crypto",  Feature_HasV8,
10006    ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
10007  { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
10008  { "idiv", Feature_HasV7 | Feature_IsNotMClass,
10009    ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
10010  // FIXME: iWMMXT not supported
10011  { "iwmmxt", Feature_None, 0 },
10012  // FIXME: iWMMXT2 not supported
10013  { "iwmmxt2", Feature_None, 0 },
10014  // FIXME: Maverick not supported
10015  { "maverick", Feature_None, 0 },
10016  { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
10017  // FIXME: ARMv6-m OS Extensions feature not checked
10018  { "os", Feature_None, 0 },
10019  // FIXME: Also available in ARMv6-K
10020  { "sec", Feature_HasV7, ARM::FeatureTrustZone },
10021  { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
10022  // FIXME: Only available in A-class, isel not predicated
10023  { "virt", Feature_HasV7, ARM::FeatureVirtualization },
10024  // FIXME: xscale not supported
10025  { "xscale", Feature_None, 0 },
10026};
10027
10028/// parseDirectiveArchExtension
10029///   ::= .arch_extension [no]feature
10030bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
10031  MCAsmParser &Parser = getParser();
10032
10033  if (getLexer().isNot(AsmToken::Identifier)) {
10034    Error(getLexer().getLoc(), "unexpected token");
10035    Parser.eatToEndOfStatement();
10036    return false;
10037  }
10038
10039  StringRef Name = Parser.getTok().getString();
10040  SMLoc ExtLoc = Parser.getTok().getLoc();
10041  getLexer().Lex();
10042
10043  bool EnableFeature = true;
10044  if (Name.startswith_lower("no")) {
10045    EnableFeature = false;
10046    Name = Name.substr(2);
10047  }
10048
10049  for (const auto &Extension : Extensions) {
10050    if (Extension.Name != Name)
10051      continue;
10052
10053    if (!Extension.Features)
10054      report_fatal_error("unsupported architectural extension: " + Name);
10055
10056    if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) {
10057      Error(ExtLoc, "architectural extension '" + Name + "' is not "
10058            "allowed for the current base architecture");
10059      return false;
10060    }
10061
10062    uint64_t ToggleFeatures = EnableFeature
10063                                  ? (~STI.getFeatureBits() & Extension.Features)
10064                                  : ( STI.getFeatureBits() & Extension.Features);
10065    uint64_t Features =
10066        ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
10067    setAvailableFeatures(Features);
10068    return false;
10069  }
10070
10071  Error(ExtLoc, "unknown architectural extension: " + Name);
10072  Parser.eatToEndOfStatement();
10073  return false;
10074}
10075
10076// Define this matcher function after the auto-generated include so we
10077// have the match class enum definitions.
10078unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
10079                                                  unsigned Kind) {
10080  ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
10081  // If the kind is a token for a literal immediate, check if our asm
10082  // operand matches. This is for InstAliases which have a fixed-value
10083  // immediate in the syntax.
10084  switch (Kind) {
10085  default: break;
10086  case MCK__35_0:
10087    if (Op.isImm())
10088      if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
10089        if (CE->getValue() == 0)
10090          return Match_Success;
10091    break;
10092  case MCK_ModImm:
10093    if (Op.isImm()) {
10094      const MCExpr *SOExpr = Op.getImm();
10095      int64_t Value;
10096      if (!SOExpr->EvaluateAsAbsolute(Value))
10097        return Match_Success;
10098      assert((Value >= INT32_MIN && Value <= UINT32_MAX) &&
10099             "expression value must be representable in 32 bits");
10100    }
10101    break;
10102  case MCK_GPRPair:
10103    if (Op.isReg() &&
10104        MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
10105      return Match_Success;
10106    break;
10107  }
10108  return Match_InvalidOperand;
10109}
10110