ARMAsmParser.cpp revision 218893 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "ARM.h"
11#include "ARMAddressingModes.h"
12#include "ARMMCExpr.h"
13#include "ARMBaseRegisterInfo.h"
14#include "ARMSubtarget.h"
15#include "llvm/MC/MCParser/MCAsmLexer.h"
16#include "llvm/MC/MCParser/MCAsmParser.h"
17#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
18#include "llvm/MC/MCContext.h"
19#include "llvm/MC/MCStreamer.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCInst.h"
22#include "llvm/Target/TargetRegistry.h"
23#include "llvm/Target/TargetAsmParser.h"
24#include "llvm/Support/SourceMgr.h"
25#include "llvm/Support/raw_ostream.h"
26#include "llvm/ADT/SmallVector.h"
27#include "llvm/ADT/StringExtras.h"
28#include "llvm/ADT/StringSwitch.h"
29#include "llvm/ADT/Twine.h"
30using namespace llvm;
31
32/// Shift types used for register controlled shifts in ARM memory addressing.
33enum ShiftType {
34  Lsl,
35  Lsr,
36  Asr,
37  Ror,
38  Rrx
39};
40
41namespace {
42
43class ARMOperand;
44
45class ARMAsmParser : public TargetAsmParser {
46  MCAsmParser &Parser;
47  TargetMachine &TM;
48
49  MCAsmParser &getParser() const { return Parser; }
50  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
51
52  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
53  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
54
55  int TryParseRegister();
56  virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
57  bool TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
58  bool ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
59  bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
60  bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
61  bool ParsePrefix(ARMMCExpr::VariantKind &RefKind);
62  const MCExpr *ApplyPrefixToExpr(const MCExpr *E,
63                                  MCSymbolRefExpr::VariantKind Variant);
64
65
66  bool ParseMemoryOffsetReg(bool &Negative,
67                            bool &OffsetRegShifted,
68                            enum ShiftType &ShiftType,
69                            const MCExpr *&ShiftAmount,
70                            const MCExpr *&Offset,
71                            bool &OffsetIsReg,
72                            int &OffsetRegNum,
73                            SMLoc &E);
74  bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
75  bool ParseDirectiveWord(unsigned Size, SMLoc L);
76  bool ParseDirectiveThumb(SMLoc L);
77  bool ParseDirectiveThumbFunc(SMLoc L);
78  bool ParseDirectiveCode(SMLoc L);
79  bool ParseDirectiveSyntax(SMLoc L);
80
81  bool MatchAndEmitInstruction(SMLoc IDLoc,
82                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
83                               MCStreamer &Out);
84  void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
85                             bool &CanAcceptPredicationCode);
86
87  /// @name Auto-generated Match Functions
88  /// {
89
90#define GET_ASSEMBLER_HEADER
91#include "ARMGenAsmMatcher.inc"
92
93  /// }
94
95  OperandMatchResultTy tryParseCoprocNumOperand(
96    SmallVectorImpl<MCParsedAsmOperand*>&);
97  OperandMatchResultTy tryParseCoprocRegOperand(
98    SmallVectorImpl<MCParsedAsmOperand*>&);
99  OperandMatchResultTy tryParseMemBarrierOptOperand(
100    SmallVectorImpl<MCParsedAsmOperand*>&);
101  OperandMatchResultTy tryParseProcIFlagsOperand(
102    SmallVectorImpl<MCParsedAsmOperand*>&);
103  OperandMatchResultTy tryParseMSRMaskOperand(
104    SmallVectorImpl<MCParsedAsmOperand*>&);
105
106public:
107  ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
108    : TargetAsmParser(T), Parser(_Parser), TM(_TM) {
109      // Initialize the set of available features.
110      setAvailableFeatures(ComputeAvailableFeatures(
111          &TM.getSubtarget<ARMSubtarget>()));
112    }
113
114  virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
115                                SmallVectorImpl<MCParsedAsmOperand*> &Operands);
116  virtual bool ParseDirective(AsmToken DirectiveID);
117};
118} // end anonymous namespace
119
120namespace {
121
122/// ARMOperand - Instances of this class represent a parsed ARM machine
123/// instruction.
124class ARMOperand : public MCParsedAsmOperand {
125  enum KindTy {
126    CondCode,
127    CCOut,
128    CoprocNum,
129    CoprocReg,
130    Immediate,
131    MemBarrierOpt,
132    Memory,
133    MSRMask,
134    ProcIFlags,
135    Register,
136    RegisterList,
137    DPRRegisterList,
138    SPRRegisterList,
139    Token
140  } Kind;
141
142  SMLoc StartLoc, EndLoc;
143  SmallVector<unsigned, 8> Registers;
144
145  union {
146    struct {
147      ARMCC::CondCodes Val;
148    } CC;
149
150    struct {
151      ARM_MB::MemBOpt Val;
152    } MBOpt;
153
154    struct {
155      unsigned Val;
156    } Cop;
157
158    struct {
159      ARM_PROC::IFlags Val;
160    } IFlags;
161
162    struct {
163      unsigned Val;
164    } MMask;
165
166    struct {
167      const char *Data;
168      unsigned Length;
169    } Tok;
170
171    struct {
172      unsigned RegNum;
173    } Reg;
174
175    struct {
176      const MCExpr *Val;
177    } Imm;
178
179    /// Combined record for all forms of ARM address expressions.
180    struct {
181      unsigned BaseRegNum;
182      union {
183        unsigned RegNum;     ///< Offset register num, when OffsetIsReg.
184        const MCExpr *Value; ///< Offset value, when !OffsetIsReg.
185      } Offset;
186      const MCExpr *ShiftAmount;     // used when OffsetRegShifted is true
187      enum ShiftType ShiftType;      // used when OffsetRegShifted is true
188      unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true
189      unsigned Preindexed       : 1;
190      unsigned Postindexed      : 1;
191      unsigned OffsetIsReg      : 1;
192      unsigned Negative         : 1; // only used when OffsetIsReg is true
193      unsigned Writeback        : 1;
194    } Mem;
195  };
196
197  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
198public:
199  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
200    Kind = o.Kind;
201    StartLoc = o.StartLoc;
202    EndLoc = o.EndLoc;
203    switch (Kind) {
204    case CondCode:
205      CC = o.CC;
206      break;
207    case Token:
208      Tok = o.Tok;
209      break;
210    case CCOut:
211    case Register:
212      Reg = o.Reg;
213      break;
214    case RegisterList:
215    case DPRRegisterList:
216    case SPRRegisterList:
217      Registers = o.Registers;
218      break;
219    case CoprocNum:
220    case CoprocReg:
221      Cop = o.Cop;
222      break;
223    case Immediate:
224      Imm = o.Imm;
225      break;
226    case MemBarrierOpt:
227      MBOpt = o.MBOpt;
228      break;
229    case Memory:
230      Mem = o.Mem;
231      break;
232    case MSRMask:
233      MMask = o.MMask;
234      break;
235    case ProcIFlags:
236      IFlags = o.IFlags;
237    }
238  }
239
240  /// getStartLoc - Get the location of the first token of this operand.
241  SMLoc getStartLoc() const { return StartLoc; }
242  /// getEndLoc - Get the location of the last token of this operand.
243  SMLoc getEndLoc() const { return EndLoc; }
244
245  ARMCC::CondCodes getCondCode() const {
246    assert(Kind == CondCode && "Invalid access!");
247    return CC.Val;
248  }
249
250  unsigned getCoproc() const {
251    assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
252    return Cop.Val;
253  }
254
255  StringRef getToken() const {
256    assert(Kind == Token && "Invalid access!");
257    return StringRef(Tok.Data, Tok.Length);
258  }
259
260  unsigned getReg() const {
261    assert((Kind == Register || Kind == CCOut) && "Invalid access!");
262    return Reg.RegNum;
263  }
264
265  const SmallVectorImpl<unsigned> &getRegList() const {
266    assert((Kind == RegisterList || Kind == DPRRegisterList ||
267            Kind == SPRRegisterList) && "Invalid access!");
268    return Registers;
269  }
270
271  const MCExpr *getImm() const {
272    assert(Kind == Immediate && "Invalid access!");
273    return Imm.Val;
274  }
275
276  ARM_MB::MemBOpt getMemBarrierOpt() const {
277    assert(Kind == MemBarrierOpt && "Invalid access!");
278    return MBOpt.Val;
279  }
280
281  ARM_PROC::IFlags getProcIFlags() const {
282    assert(Kind == ProcIFlags && "Invalid access!");
283    return IFlags.Val;
284  }
285
286  unsigned getMSRMask() const {
287    assert(Kind == MSRMask && "Invalid access!");
288    return MMask.Val;
289  }
290
291  /// @name Memory Operand Accessors
292  /// @{
293
294  unsigned getMemBaseRegNum() const {
295    return Mem.BaseRegNum;
296  }
297  unsigned getMemOffsetRegNum() const {
298    assert(Mem.OffsetIsReg && "Invalid access!");
299    return Mem.Offset.RegNum;
300  }
301  const MCExpr *getMemOffset() const {
302    assert(!Mem.OffsetIsReg && "Invalid access!");
303    return Mem.Offset.Value;
304  }
305  unsigned getMemOffsetRegShifted() const {
306    assert(Mem.OffsetIsReg && "Invalid access!");
307    return Mem.OffsetRegShifted;
308  }
309  const MCExpr *getMemShiftAmount() const {
310    assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!");
311    return Mem.ShiftAmount;
312  }
313  enum ShiftType getMemShiftType() const {
314    assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!");
315    return Mem.ShiftType;
316  }
317  bool getMemPreindexed() const { return Mem.Preindexed; }
318  bool getMemPostindexed() const { return Mem.Postindexed; }
319  bool getMemOffsetIsReg() const { return Mem.OffsetIsReg; }
320  bool getMemNegative() const { return Mem.Negative; }
321  bool getMemWriteback() const { return Mem.Writeback; }
322
323  /// @}
324
325  bool isCoprocNum() const { return Kind == CoprocNum; }
326  bool isCoprocReg() const { return Kind == CoprocReg; }
327  bool isCondCode() const { return Kind == CondCode; }
328  bool isCCOut() const { return Kind == CCOut; }
329  bool isImm() const { return Kind == Immediate; }
330  bool isReg() const { return Kind == Register; }
331  bool isRegList() const { return Kind == RegisterList; }
332  bool isDPRRegList() const { return Kind == DPRRegisterList; }
333  bool isSPRRegList() const { return Kind == SPRRegisterList; }
334  bool isToken() const { return Kind == Token; }
335  bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
336  bool isMemory() const { return Kind == Memory; }
337  bool isMemMode5() const {
338    if (!isMemory() || getMemOffsetIsReg() || getMemWriteback() ||
339        getMemNegative())
340      return false;
341
342    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
343    if (!CE) return false;
344
345    // The offset must be a multiple of 4 in the range 0-1020.
346    int64_t Value = CE->getValue();
347    return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
348  }
349  bool isMemModeRegThumb() const {
350    if (!isMemory() || !getMemOffsetIsReg() || getMemWriteback())
351      return false;
352    return true;
353  }
354  bool isMemModeImmThumb() const {
355    if (!isMemory() || getMemOffsetIsReg() || getMemWriteback())
356      return false;
357
358    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
359    if (!CE) return false;
360
361    // The offset must be a multiple of 4 in the range 0-124.
362    uint64_t Value = CE->getValue();
363    return ((Value & 0x3) == 0 && Value <= 124);
364  }
365  bool isMSRMask() const { return Kind == MSRMask; }
366  bool isProcIFlags() const { return Kind == ProcIFlags; }
367
368  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
369    // Add as immediates when possible.  Null MCExpr = 0.
370    if (Expr == 0)
371      Inst.addOperand(MCOperand::CreateImm(0));
372    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
373      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
374    else
375      Inst.addOperand(MCOperand::CreateExpr(Expr));
376  }
377
378  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
379    assert(N == 2 && "Invalid number of operands!");
380    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
381    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
382    Inst.addOperand(MCOperand::CreateReg(RegNum));
383  }
384
385  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
386    assert(N == 1 && "Invalid number of operands!");
387    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
388  }
389
390  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
391    assert(N == 1 && "Invalid number of operands!");
392    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
393  }
394
395  void addCCOutOperands(MCInst &Inst, unsigned N) const {
396    assert(N == 1 && "Invalid number of operands!");
397    Inst.addOperand(MCOperand::CreateReg(getReg()));
398  }
399
400  void addRegOperands(MCInst &Inst, unsigned N) const {
401    assert(N == 1 && "Invalid number of operands!");
402    Inst.addOperand(MCOperand::CreateReg(getReg()));
403  }
404
405  void addRegListOperands(MCInst &Inst, unsigned N) const {
406    assert(N == 1 && "Invalid number of operands!");
407    const SmallVectorImpl<unsigned> &RegList = getRegList();
408    for (SmallVectorImpl<unsigned>::const_iterator
409           I = RegList.begin(), E = RegList.end(); I != E; ++I)
410      Inst.addOperand(MCOperand::CreateReg(*I));
411  }
412
413  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
414    addRegListOperands(Inst, N);
415  }
416
417  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
418    addRegListOperands(Inst, N);
419  }
420
421  void addImmOperands(MCInst &Inst, unsigned N) const {
422    assert(N == 1 && "Invalid number of operands!");
423    addExpr(Inst, getImm());
424  }
425
426  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
427    assert(N == 1 && "Invalid number of operands!");
428    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
429  }
430
431  void addMemMode5Operands(MCInst &Inst, unsigned N) const {
432    assert(N == 2 && isMemMode5() && "Invalid number of operands!");
433
434    Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
435    assert(!getMemOffsetIsReg() && "Invalid mode 5 operand");
436
437    // FIXME: #-0 is encoded differently than #0. Does the parser preserve
438    // the difference?
439    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
440    assert(CE && "Non-constant mode 5 offset operand!");
441
442    // The MCInst offset operand doesn't include the low two bits (like
443    // the instruction encoding).
444    int64_t Offset = CE->getValue() / 4;
445    if (Offset >= 0)
446      Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
447                                                             Offset)));
448    else
449      Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
450                                                             -Offset)));
451  }
452
453  void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const {
454    assert(N == 2 && isMemModeRegThumb() && "Invalid number of operands!");
455    Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
456    Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
457  }
458
459  void addMemModeImmThumbOperands(MCInst &Inst, unsigned N) const {
460    assert(N == 2 && isMemModeImmThumb() && "Invalid number of operands!");
461    Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
462    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
463    assert(CE && "Non-constant mode offset operand!");
464    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
465  }
466
467  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
468    assert(N == 1 && "Invalid number of operands!");
469    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
470  }
471
472  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
473    assert(N == 1 && "Invalid number of operands!");
474    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
475  }
476
477  virtual void dump(raw_ostream &OS) const;
478
479  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
480    ARMOperand *Op = new ARMOperand(CondCode);
481    Op->CC.Val = CC;
482    Op->StartLoc = S;
483    Op->EndLoc = S;
484    return Op;
485  }
486
487  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
488    ARMOperand *Op = new ARMOperand(CoprocNum);
489    Op->Cop.Val = CopVal;
490    Op->StartLoc = S;
491    Op->EndLoc = S;
492    return Op;
493  }
494
495  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
496    ARMOperand *Op = new ARMOperand(CoprocReg);
497    Op->Cop.Val = CopVal;
498    Op->StartLoc = S;
499    Op->EndLoc = S;
500    return Op;
501  }
502
503  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
504    ARMOperand *Op = new ARMOperand(CCOut);
505    Op->Reg.RegNum = RegNum;
506    Op->StartLoc = S;
507    Op->EndLoc = S;
508    return Op;
509  }
510
511  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
512    ARMOperand *Op = new ARMOperand(Token);
513    Op->Tok.Data = Str.data();
514    Op->Tok.Length = Str.size();
515    Op->StartLoc = S;
516    Op->EndLoc = S;
517    return Op;
518  }
519
520  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
521    ARMOperand *Op = new ARMOperand(Register);
522    Op->Reg.RegNum = RegNum;
523    Op->StartLoc = S;
524    Op->EndLoc = E;
525    return Op;
526  }
527
528  static ARMOperand *
529  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
530                SMLoc StartLoc, SMLoc EndLoc) {
531    KindTy Kind = RegisterList;
532
533    if (ARM::DPRRegClass.contains(Regs.front().first))
534      Kind = DPRRegisterList;
535    else if (ARM::SPRRegClass.contains(Regs.front().first))
536      Kind = SPRRegisterList;
537
538    ARMOperand *Op = new ARMOperand(Kind);
539    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
540           I = Regs.begin(), E = Regs.end(); I != E; ++I)
541      Op->Registers.push_back(I->first);
542    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
543    Op->StartLoc = StartLoc;
544    Op->EndLoc = EndLoc;
545    return Op;
546  }
547
548  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
549    ARMOperand *Op = new ARMOperand(Immediate);
550    Op->Imm.Val = Val;
551    Op->StartLoc = S;
552    Op->EndLoc = E;
553    return Op;
554  }
555
556  static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
557                               const MCExpr *Offset, int OffsetRegNum,
558                               bool OffsetRegShifted, enum ShiftType ShiftType,
559                               const MCExpr *ShiftAmount, bool Preindexed,
560                               bool Postindexed, bool Negative, bool Writeback,
561                               SMLoc S, SMLoc E) {
562    assert((OffsetRegNum == -1 || OffsetIsReg) &&
563           "OffsetRegNum must imply OffsetIsReg!");
564    assert((!OffsetRegShifted || OffsetIsReg) &&
565           "OffsetRegShifted must imply OffsetIsReg!");
566    assert((Offset || OffsetIsReg) &&
567           "Offset must exists unless register offset is used!");
568    assert((!ShiftAmount || (OffsetIsReg && OffsetRegShifted)) &&
569           "Cannot have shift amount without shifted register offset!");
570    assert((!Offset || !OffsetIsReg) &&
571           "Cannot have expression offset and register offset!");
572
573    ARMOperand *Op = new ARMOperand(Memory);
574    Op->Mem.BaseRegNum = BaseRegNum;
575    Op->Mem.OffsetIsReg = OffsetIsReg;
576    if (OffsetIsReg)
577      Op->Mem.Offset.RegNum = OffsetRegNum;
578    else
579      Op->Mem.Offset.Value = Offset;
580    Op->Mem.OffsetRegShifted = OffsetRegShifted;
581    Op->Mem.ShiftType = ShiftType;
582    Op->Mem.ShiftAmount = ShiftAmount;
583    Op->Mem.Preindexed = Preindexed;
584    Op->Mem.Postindexed = Postindexed;
585    Op->Mem.Negative = Negative;
586    Op->Mem.Writeback = Writeback;
587
588    Op->StartLoc = S;
589    Op->EndLoc = E;
590    return Op;
591  }
592
593  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
594    ARMOperand *Op = new ARMOperand(MemBarrierOpt);
595    Op->MBOpt.Val = Opt;
596    Op->StartLoc = S;
597    Op->EndLoc = S;
598    return Op;
599  }
600
601  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
602    ARMOperand *Op = new ARMOperand(ProcIFlags);
603    Op->IFlags.Val = IFlags;
604    Op->StartLoc = S;
605    Op->EndLoc = S;
606    return Op;
607  }
608
609  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
610    ARMOperand *Op = new ARMOperand(MSRMask);
611    Op->MMask.Val = MMask;
612    Op->StartLoc = S;
613    Op->EndLoc = S;
614    return Op;
615  }
616};
617
618} // end anonymous namespace.
619
620void ARMOperand::dump(raw_ostream &OS) const {
621  switch (Kind) {
622  case CondCode:
623    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
624    break;
625  case CCOut:
626    OS << "<ccout " << getReg() << ">";
627    break;
628  case CoprocNum:
629    OS << "<coprocessor number: " << getCoproc() << ">";
630    break;
631  case CoprocReg:
632    OS << "<coprocessor register: " << getCoproc() << ">";
633    break;
634  case MSRMask:
635    OS << "<mask: " << getMSRMask() << ">";
636    break;
637  case Immediate:
638    getImm()->print(OS);
639    break;
640  case MemBarrierOpt:
641    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
642    break;
643  case Memory:
644    OS << "<memory "
645       << "base:" << getMemBaseRegNum();
646    if (getMemOffsetIsReg()) {
647      OS << " offset:<register " << getMemOffsetRegNum();
648      if (getMemOffsetRegShifted()) {
649        OS << " offset-shift-type:" << getMemShiftType();
650        OS << " offset-shift-amount:" << *getMemShiftAmount();
651      }
652    } else {
653      OS << " offset:" << *getMemOffset();
654    }
655    if (getMemOffsetIsReg())
656      OS << " (offset-is-reg)";
657    if (getMemPreindexed())
658      OS << " (pre-indexed)";
659    if (getMemPostindexed())
660      OS << " (post-indexed)";
661    if (getMemNegative())
662      OS << " (negative)";
663    if (getMemWriteback())
664      OS << " (writeback)";
665    OS << ">";
666    break;
667  case ProcIFlags: {
668    OS << "<ARM_PROC::";
669    unsigned IFlags = getProcIFlags();
670    for (int i=2; i >= 0; --i)
671      if (IFlags & (1 << i))
672        OS << ARM_PROC::IFlagsToString(1 << i);
673    OS << ">";
674    break;
675  }
676  case Register:
677    OS << "<register " << getReg() << ">";
678    break;
679  case RegisterList:
680  case DPRRegisterList:
681  case SPRRegisterList: {
682    OS << "<register_list ";
683
684    const SmallVectorImpl<unsigned> &RegList = getRegList();
685    for (SmallVectorImpl<unsigned>::const_iterator
686           I = RegList.begin(), E = RegList.end(); I != E; ) {
687      OS << *I;
688      if (++I < E) OS << ", ";
689    }
690
691    OS << ">";
692    break;
693  }
694  case Token:
695    OS << "'" << getToken() << "'";
696    break;
697  }
698}
699
700/// @name Auto-generated Match Functions
701/// {
702
703static unsigned MatchRegisterName(StringRef Name);
704
705/// }
706
707bool ARMAsmParser::ParseRegister(unsigned &RegNo,
708                                 SMLoc &StartLoc, SMLoc &EndLoc) {
709  RegNo = TryParseRegister();
710
711  return (RegNo == (unsigned)-1);
712}
713
714/// Try to parse a register name.  The token must be an Identifier when called,
715/// and if it is a register name the token is eaten and the register number is
716/// returned.  Otherwise return -1.
717///
718int ARMAsmParser::TryParseRegister() {
719  const AsmToken &Tok = Parser.getTok();
720  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
721
722  // FIXME: Validate register for the current architecture; we have to do
723  // validation later, so maybe there is no need for this here.
724  std::string upperCase = Tok.getString().str();
725  std::string lowerCase = LowercaseString(upperCase);
726  unsigned RegNum = MatchRegisterName(lowerCase);
727  if (!RegNum) {
728    RegNum = StringSwitch<unsigned>(lowerCase)
729      .Case("r13", ARM::SP)
730      .Case("r14", ARM::LR)
731      .Case("r15", ARM::PC)
732      .Case("ip", ARM::R12)
733      .Default(0);
734  }
735  if (!RegNum) return -1;
736
737  Parser.Lex(); // Eat identifier token.
738  return RegNum;
739}
740
741/// Try to parse a register name.  The token must be an Identifier when called.
742/// If it's a register, an AsmOperand is created. Another AsmOperand is created
743/// if there is a "writeback". 'true' if it's not a register.
744///
745/// TODO this is likely to change to allow different register types and or to
746/// parse for a specific register type.
747bool ARMAsmParser::
748TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
749  SMLoc S = Parser.getTok().getLoc();
750  int RegNo = TryParseRegister();
751  if (RegNo == -1)
752    return true;
753
754  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
755
756  const AsmToken &ExclaimTok = Parser.getTok();
757  if (ExclaimTok.is(AsmToken::Exclaim)) {
758    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
759                                               ExclaimTok.getLoc()));
760    Parser.Lex(); // Eat exclaim token
761  }
762
763  return false;
764}
765
766/// MatchCoprocessorOperandName - Try to parse an coprocessor related
767/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
768/// "c5", ...
769static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
770  // Use the same layout as the tablegen'erated register name matcher. Ugly,
771  // but efficient.
772  switch (Name.size()) {
773  default: break;
774  case 2:
775    if (Name[0] != CoprocOp)
776      return -1;
777    switch (Name[1]) {
778    default:  return -1;
779    case '0': return 0;
780    case '1': return 1;
781    case '2': return 2;
782    case '3': return 3;
783    case '4': return 4;
784    case '5': return 5;
785    case '6': return 6;
786    case '7': return 7;
787    case '8': return 8;
788    case '9': return 9;
789    }
790    break;
791  case 3:
792    if (Name[0] != CoprocOp || Name[1] != '1')
793      return -1;
794    switch (Name[2]) {
795    default:  return -1;
796    case '0': return 10;
797    case '1': return 11;
798    case '2': return 12;
799    case '3': return 13;
800    case '4': return 14;
801    case '5': return 15;
802    }
803    break;
804  }
805
806  return -1;
807}
808
809/// tryParseCoprocNumOperand - Try to parse an coprocessor number operand. The
810/// token must be an Identifier when called, and if it is a coprocessor
811/// number, the token is eaten and the operand is added to the operand list.
812ARMAsmParser::OperandMatchResultTy ARMAsmParser::
813tryParseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
814  SMLoc S = Parser.getTok().getLoc();
815  const AsmToken &Tok = Parser.getTok();
816  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
817
818  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
819  if (Num == -1)
820    return MatchOperand_NoMatch;
821
822  Parser.Lex(); // Eat identifier token.
823  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
824  return MatchOperand_Success;
825}
826
827/// tryParseCoprocRegOperand - Try to parse an coprocessor register operand. The
828/// token must be an Identifier when called, and if it is a coprocessor
829/// number, the token is eaten and the operand is added to the operand list.
830ARMAsmParser::OperandMatchResultTy ARMAsmParser::
831tryParseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
832  SMLoc S = Parser.getTok().getLoc();
833  const AsmToken &Tok = Parser.getTok();
834  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
835
836  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
837  if (Reg == -1)
838    return MatchOperand_NoMatch;
839
840  Parser.Lex(); // Eat identifier token.
841  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
842  return MatchOperand_Success;
843}
844
845/// Parse a register list, return it if successful else return null.  The first
846/// token must be a '{' when called.
847bool ARMAsmParser::
848ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
849  assert(Parser.getTok().is(AsmToken::LCurly) &&
850         "Token is not a Left Curly Brace");
851  SMLoc S = Parser.getTok().getLoc();
852
853  // Read the rest of the registers in the list.
854  unsigned PrevRegNum = 0;
855  SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
856
857  do {
858    bool IsRange = Parser.getTok().is(AsmToken::Minus);
859    Parser.Lex(); // Eat non-identifier token.
860
861    const AsmToken &RegTok = Parser.getTok();
862    SMLoc RegLoc = RegTok.getLoc();
863    if (RegTok.isNot(AsmToken::Identifier)) {
864      Error(RegLoc, "register expected");
865      return true;
866    }
867
868    int RegNum = TryParseRegister();
869    if (RegNum == -1) {
870      Error(RegLoc, "register expected");
871      return true;
872    }
873
874    if (IsRange) {
875      int Reg = PrevRegNum;
876      do {
877        ++Reg;
878        Registers.push_back(std::make_pair(Reg, RegLoc));
879      } while (Reg != RegNum);
880    } else {
881      Registers.push_back(std::make_pair(RegNum, RegLoc));
882    }
883
884    PrevRegNum = RegNum;
885  } while (Parser.getTok().is(AsmToken::Comma) ||
886           Parser.getTok().is(AsmToken::Minus));
887
888  // Process the right curly brace of the list.
889  const AsmToken &RCurlyTok = Parser.getTok();
890  if (RCurlyTok.isNot(AsmToken::RCurly)) {
891    Error(RCurlyTok.getLoc(), "'}' expected");
892    return true;
893  }
894
895  SMLoc E = RCurlyTok.getLoc();
896  Parser.Lex(); // Eat right curly brace token.
897
898  // Verify the register list.
899  SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
900    RI = Registers.begin(), RE = Registers.end();
901
902  unsigned HighRegNum = getARMRegisterNumbering(RI->first);
903  bool EmittedWarning = false;
904
905  DenseMap<unsigned, bool> RegMap;
906  RegMap[HighRegNum] = true;
907
908  for (++RI; RI != RE; ++RI) {
909    const std::pair<unsigned, SMLoc> &RegInfo = *RI;
910    unsigned Reg = getARMRegisterNumbering(RegInfo.first);
911
912    if (RegMap[Reg]) {
913      Error(RegInfo.second, "register duplicated in register list");
914      return true;
915    }
916
917    if (!EmittedWarning && Reg < HighRegNum)
918      Warning(RegInfo.second,
919              "register not in ascending order in register list");
920
921    RegMap[Reg] = true;
922    HighRegNum = std::max(Reg, HighRegNum);
923  }
924
925  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
926  return false;
927}
928
929/// tryParseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
930ARMAsmParser::OperandMatchResultTy ARMAsmParser::
931tryParseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
932  SMLoc S = Parser.getTok().getLoc();
933  const AsmToken &Tok = Parser.getTok();
934  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
935  StringRef OptStr = Tok.getString();
936
937  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
938    .Case("sy",    ARM_MB::SY)
939    .Case("st",    ARM_MB::ST)
940    .Case("ish",   ARM_MB::ISH)
941    .Case("ishst", ARM_MB::ISHST)
942    .Case("nsh",   ARM_MB::NSH)
943    .Case("nshst", ARM_MB::NSHST)
944    .Case("osh",   ARM_MB::OSH)
945    .Case("oshst", ARM_MB::OSHST)
946    .Default(~0U);
947
948  if (Opt == ~0U)
949    return MatchOperand_NoMatch;
950
951  Parser.Lex(); // Eat identifier token.
952  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
953  return MatchOperand_Success;
954}
955
956/// tryParseProcIFlagsOperand - Try to parse iflags from CPS instruction.
957ARMAsmParser::OperandMatchResultTy ARMAsmParser::
958tryParseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
959  SMLoc S = Parser.getTok().getLoc();
960  const AsmToken &Tok = Parser.getTok();
961  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
962  StringRef IFlagsStr = Tok.getString();
963
964  unsigned IFlags = 0;
965  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
966    unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
967    .Case("a", ARM_PROC::A)
968    .Case("i", ARM_PROC::I)
969    .Case("f", ARM_PROC::F)
970    .Default(~0U);
971
972    // If some specific iflag is already set, it means that some letter is
973    // present more than once, this is not acceptable.
974    if (Flag == ~0U || (IFlags & Flag))
975      return MatchOperand_NoMatch;
976
977    IFlags |= Flag;
978  }
979
980  Parser.Lex(); // Eat identifier token.
981  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
982  return MatchOperand_Success;
983}
984
985/// tryParseMSRMaskOperand - Try to parse mask flags from MSR instruction.
986ARMAsmParser::OperandMatchResultTy ARMAsmParser::
987tryParseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
988  SMLoc S = Parser.getTok().getLoc();
989  const AsmToken &Tok = Parser.getTok();
990  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
991  StringRef Mask = Tok.getString();
992
993  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
994  size_t Start = 0, Next = Mask.find('_');
995  StringRef Flags = "";
996  StringRef SpecReg = Mask.slice(Start, Next);
997  if (Next != StringRef::npos)
998    Flags = Mask.slice(Next+1, Mask.size());
999
1000  // FlagsVal contains the complete mask:
1001  // 3-0: Mask
1002  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1003  unsigned FlagsVal = 0;
1004
1005  if (SpecReg == "apsr") {
1006    FlagsVal = StringSwitch<unsigned>(Flags)
1007    .Case("nzcvq",  0x8) // same as CPSR_c
1008    .Case("g",      0x4) // same as CPSR_s
1009    .Case("nzcvqg", 0xc) // same as CPSR_fs
1010    .Default(~0U);
1011
1012    if (FlagsVal == ~0U) {
1013      if (!Flags.empty())
1014        return MatchOperand_NoMatch;
1015      else
1016        FlagsVal = 0; // No flag
1017    }
1018  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1019    for (int i = 0, e = Flags.size(); i != e; ++i) {
1020      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1021      .Case("c", 1)
1022      .Case("x", 2)
1023      .Case("s", 4)
1024      .Case("f", 8)
1025      .Default(~0U);
1026
1027      // If some specific flag is already set, it means that some letter is
1028      // present more than once, this is not acceptable.
1029      if (FlagsVal == ~0U || (FlagsVal & Flag))
1030        return MatchOperand_NoMatch;
1031      FlagsVal |= Flag;
1032    }
1033  } else // No match for special register.
1034    return MatchOperand_NoMatch;
1035
1036  // Special register without flags are equivalent to "fc" flags.
1037  if (!FlagsVal)
1038    FlagsVal = 0x9;
1039
1040  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1041  if (SpecReg == "spsr")
1042    FlagsVal |= 16;
1043
1044  Parser.Lex(); // Eat identifier token.
1045  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1046  return MatchOperand_Success;
1047}
1048
1049/// Parse an ARM memory expression, return false if successful else return true
1050/// or an error.  The first token must be a '[' when called.
1051///
1052/// TODO Only preindexing and postindexing addressing are started, unindexed
1053/// with option, etc are still to do.
1054bool ARMAsmParser::
1055ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1056  SMLoc S, E;
1057  assert(Parser.getTok().is(AsmToken::LBrac) &&
1058         "Token is not a Left Bracket");
1059  S = Parser.getTok().getLoc();
1060  Parser.Lex(); // Eat left bracket token.
1061
1062  const AsmToken &BaseRegTok = Parser.getTok();
1063  if (BaseRegTok.isNot(AsmToken::Identifier)) {
1064    Error(BaseRegTok.getLoc(), "register expected");
1065    return true;
1066  }
1067  int BaseRegNum = TryParseRegister();
1068  if (BaseRegNum == -1) {
1069    Error(BaseRegTok.getLoc(), "register expected");
1070    return true;
1071  }
1072
1073  // The next token must either be a comma or a closing bracket.
1074  const AsmToken &Tok = Parser.getTok();
1075  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
1076    return true;
1077
1078  bool Preindexed = false;
1079  bool Postindexed = false;
1080  bool OffsetIsReg = false;
1081  bool Negative = false;
1082  bool Writeback = false;
1083  ARMOperand *WBOp = 0;
1084  int OffsetRegNum = -1;
1085  bool OffsetRegShifted = false;
1086  enum ShiftType ShiftType = Lsl;
1087  const MCExpr *ShiftAmount = 0;
1088  const MCExpr *Offset = 0;
1089
1090  // First look for preindexed address forms, that is after the "[Rn" we now
1091  // have to see if the next token is a comma.
1092  if (Tok.is(AsmToken::Comma)) {
1093    Preindexed = true;
1094    Parser.Lex(); // Eat comma token.
1095
1096    if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
1097                             Offset, OffsetIsReg, OffsetRegNum, E))
1098      return true;
1099    const AsmToken &RBracTok = Parser.getTok();
1100    if (RBracTok.isNot(AsmToken::RBrac)) {
1101      Error(RBracTok.getLoc(), "']' expected");
1102      return true;
1103    }
1104    E = RBracTok.getLoc();
1105    Parser.Lex(); // Eat right bracket token.
1106
1107    const AsmToken &ExclaimTok = Parser.getTok();
1108    if (ExclaimTok.is(AsmToken::Exclaim)) {
1109      WBOp = ARMOperand::CreateToken(ExclaimTok.getString(),
1110                                     ExclaimTok.getLoc());
1111      Writeback = true;
1112      Parser.Lex(); // Eat exclaim token
1113    }
1114  } else {
1115    // The "[Rn" we have so far was not followed by a comma.
1116
1117    // If there's anything other than the right brace, this is a post indexing
1118    // addressing form.
1119    E = Tok.getLoc();
1120    Parser.Lex(); // Eat right bracket token.
1121
1122    const AsmToken &NextTok = Parser.getTok();
1123
1124    if (NextTok.isNot(AsmToken::EndOfStatement)) {
1125      Postindexed = true;
1126      Writeback = true;
1127
1128      if (NextTok.isNot(AsmToken::Comma)) {
1129        Error(NextTok.getLoc(), "',' expected");
1130        return true;
1131      }
1132
1133      Parser.Lex(); // Eat comma token.
1134
1135      if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
1136                               ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
1137                               E))
1138        return true;
1139    }
1140  }
1141
1142  // Force Offset to exist if used.
1143  if (!OffsetIsReg) {
1144    if (!Offset)
1145      Offset = MCConstantExpr::Create(0, getContext());
1146  }
1147
1148  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset,
1149                                           OffsetRegNum, OffsetRegShifted,
1150                                           ShiftType, ShiftAmount, Preindexed,
1151                                           Postindexed, Negative, Writeback,
1152                                           S, E));
1153  if (WBOp)
1154    Operands.push_back(WBOp);
1155
1156  return false;
1157}
1158
1159/// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
1160/// we will parse the following (were +/- means that a plus or minus is
1161/// optional):
1162///   +/-Rm
1163///   +/-Rm, shift
1164///   #offset
1165/// we return false on success or an error otherwise.
1166bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
1167                                        bool &OffsetRegShifted,
1168                                        enum ShiftType &ShiftType,
1169                                        const MCExpr *&ShiftAmount,
1170                                        const MCExpr *&Offset,
1171                                        bool &OffsetIsReg,
1172                                        int &OffsetRegNum,
1173                                        SMLoc &E) {
1174  Negative = false;
1175  OffsetRegShifted = false;
1176  OffsetIsReg = false;
1177  OffsetRegNum = -1;
1178  const AsmToken &NextTok = Parser.getTok();
1179  E = NextTok.getLoc();
1180  if (NextTok.is(AsmToken::Plus))
1181    Parser.Lex(); // Eat plus token.
1182  else if (NextTok.is(AsmToken::Minus)) {
1183    Negative = true;
1184    Parser.Lex(); // Eat minus token
1185  }
1186  // See if there is a register following the "[Rn," or "[Rn]," we have so far.
1187  const AsmToken &OffsetRegTok = Parser.getTok();
1188  if (OffsetRegTok.is(AsmToken::Identifier)) {
1189    SMLoc CurLoc = OffsetRegTok.getLoc();
1190    OffsetRegNum = TryParseRegister();
1191    if (OffsetRegNum != -1) {
1192      OffsetIsReg = true;
1193      E = CurLoc;
1194    }
1195  }
1196
1197  // If we parsed a register as the offset then there can be a shift after that.
1198  if (OffsetRegNum != -1) {
1199    // Look for a comma then a shift
1200    const AsmToken &Tok = Parser.getTok();
1201    if (Tok.is(AsmToken::Comma)) {
1202      Parser.Lex(); // Eat comma token.
1203
1204      const AsmToken &Tok = Parser.getTok();
1205      if (ParseShift(ShiftType, ShiftAmount, E))
1206        return Error(Tok.getLoc(), "shift expected");
1207      OffsetRegShifted = true;
1208    }
1209  }
1210  else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
1211    // Look for #offset following the "[Rn," or "[Rn],"
1212    const AsmToken &HashTok = Parser.getTok();
1213    if (HashTok.isNot(AsmToken::Hash))
1214      return Error(HashTok.getLoc(), "'#' expected");
1215
1216    Parser.Lex(); // Eat hash token.
1217
1218    if (getParser().ParseExpression(Offset))
1219     return true;
1220    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1221  }
1222  return false;
1223}
1224
1225/// ParseShift as one of these two:
1226///   ( lsl | lsr | asr | ror ) , # shift_amount
1227///   rrx
1228/// and returns true if it parses a shift otherwise it returns false.
1229bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
1230                              SMLoc &E) {
1231  const AsmToken &Tok = Parser.getTok();
1232  if (Tok.isNot(AsmToken::Identifier))
1233    return true;
1234  StringRef ShiftName = Tok.getString();
1235  if (ShiftName == "lsl" || ShiftName == "LSL")
1236    St = Lsl;
1237  else if (ShiftName == "lsr" || ShiftName == "LSR")
1238    St = Lsr;
1239  else if (ShiftName == "asr" || ShiftName == "ASR")
1240    St = Asr;
1241  else if (ShiftName == "ror" || ShiftName == "ROR")
1242    St = Ror;
1243  else if (ShiftName == "rrx" || ShiftName == "RRX")
1244    St = Rrx;
1245  else
1246    return true;
1247  Parser.Lex(); // Eat shift type token.
1248
1249  // Rrx stands alone.
1250  if (St == Rrx)
1251    return false;
1252
1253  // Otherwise, there must be a '#' and a shift amount.
1254  const AsmToken &HashTok = Parser.getTok();
1255  if (HashTok.isNot(AsmToken::Hash))
1256    return Error(HashTok.getLoc(), "'#' expected");
1257  Parser.Lex(); // Eat hash token.
1258
1259  if (getParser().ParseExpression(ShiftAmount))
1260    return true;
1261
1262  return false;
1263}
1264
1265/// Parse a arm instruction operand.  For now this parses the operand regardless
1266/// of the mnemonic.
1267bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1268                                StringRef Mnemonic) {
1269  SMLoc S, E;
1270
1271  // Check if the current operand has a custom associated parser, if so, try to
1272  // custom parse the operand, or fallback to the general approach.
1273  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1274  if (ResTy == MatchOperand_Success)
1275    return false;
1276  // If there wasn't a custom match, try the generic matcher below. Otherwise,
1277  // there was a match, but an error occurred, in which case, just return that
1278  // the operand parsing failed.
1279  if (ResTy == MatchOperand_ParseFail)
1280    return true;
1281
1282  switch (getLexer().getKind()) {
1283  default:
1284    Error(Parser.getTok().getLoc(), "unexpected token in operand");
1285    return true;
1286  case AsmToken::Identifier:
1287    if (!TryParseRegisterWithWriteBack(Operands))
1288      return false;
1289
1290    // Fall though for the Identifier case that is not a register or a
1291    // special name.
1292  case AsmToken::Integer: // things like 1f and 2b as a branch targets
1293  case AsmToken::Dot: {   // . as a branch target
1294    // This was not a register so parse other operands that start with an
1295    // identifier (like labels) as expressions and create them as immediates.
1296    const MCExpr *IdVal;
1297    S = Parser.getTok().getLoc();
1298    if (getParser().ParseExpression(IdVal))
1299      return true;
1300    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1301    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
1302    return false;
1303  }
1304  case AsmToken::LBrac:
1305    return ParseMemory(Operands);
1306  case AsmToken::LCurly:
1307    return ParseRegisterList(Operands);
1308  case AsmToken::Hash:
1309    // #42 -> immediate.
1310    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
1311    S = Parser.getTok().getLoc();
1312    Parser.Lex();
1313    const MCExpr *ImmVal;
1314    if (getParser().ParseExpression(ImmVal))
1315      return true;
1316    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1317    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
1318    return false;
1319  case AsmToken::Colon: {
1320    // ":lower16:" and ":upper16:" expression prefixes
1321    // FIXME: Check it's an expression prefix,
1322    // e.g. (FOO - :lower16:BAR) isn't legal.
1323    ARMMCExpr::VariantKind RefKind;
1324    if (ParsePrefix(RefKind))
1325      return true;
1326
1327    const MCExpr *SubExprVal;
1328    if (getParser().ParseExpression(SubExprVal))
1329      return true;
1330
1331    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
1332                                                   getContext());
1333    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1334    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
1335    return false;
1336  }
1337  }
1338}
1339
1340// ParsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
1341//  :lower16: and :upper16:.
1342bool ARMAsmParser::ParsePrefix(ARMMCExpr::VariantKind &RefKind) {
1343  RefKind = ARMMCExpr::VK_ARM_None;
1344
1345  // :lower16: and :upper16: modifiers
1346  assert(getLexer().is(AsmToken::Colon) && "expected a :");
1347  Parser.Lex(); // Eat ':'
1348
1349  if (getLexer().isNot(AsmToken::Identifier)) {
1350    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
1351    return true;
1352  }
1353
1354  StringRef IDVal = Parser.getTok().getIdentifier();
1355  if (IDVal == "lower16") {
1356    RefKind = ARMMCExpr::VK_ARM_LO16;
1357  } else if (IDVal == "upper16") {
1358    RefKind = ARMMCExpr::VK_ARM_HI16;
1359  } else {
1360    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
1361    return true;
1362  }
1363  Parser.Lex();
1364
1365  if (getLexer().isNot(AsmToken::Colon)) {
1366    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
1367    return true;
1368  }
1369  Parser.Lex(); // Eat the last ':'
1370  return false;
1371}
1372
1373const MCExpr *
1374ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E,
1375                                MCSymbolRefExpr::VariantKind Variant) {
1376  // Recurse over the given expression, rebuilding it to apply the given variant
1377  // to the leftmost symbol.
1378  if (Variant == MCSymbolRefExpr::VK_None)
1379    return E;
1380
1381  switch (E->getKind()) {
1382  case MCExpr::Target:
1383    llvm_unreachable("Can't handle target expr yet");
1384  case MCExpr::Constant:
1385    llvm_unreachable("Can't handle lower16/upper16 of constant yet");
1386
1387  case MCExpr::SymbolRef: {
1388    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1389
1390    if (SRE->getKind() != MCSymbolRefExpr::VK_None)
1391      return 0;
1392
1393    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
1394  }
1395
1396  case MCExpr::Unary:
1397    llvm_unreachable("Can't handle unary expressions yet");
1398
1399  case MCExpr::Binary: {
1400    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1401    const MCExpr *LHS = ApplyPrefixToExpr(BE->getLHS(), Variant);
1402    const MCExpr *RHS = BE->getRHS();
1403    if (!LHS)
1404      return 0;
1405
1406    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
1407  }
1408  }
1409
1410  assert(0 && "Invalid expression kind!");
1411  return 0;
1412}
1413
1414/// \brief Given a mnemonic, split out possible predication code and carry
1415/// setting letters to form a canonical mnemonic and flags.
1416//
1417// FIXME: Would be nice to autogen this.
1418static StringRef SplitMnemonic(StringRef Mnemonic,
1419                               unsigned &PredicationCode,
1420                               bool &CarrySetting,
1421                               unsigned &ProcessorIMod) {
1422  PredicationCode = ARMCC::AL;
1423  CarrySetting = false;
1424  ProcessorIMod = 0;
1425
1426  // Ignore some mnemonics we know aren't predicated forms.
1427  //
1428  // FIXME: Would be nice to autogen this.
1429  if (Mnemonic == "teq" || Mnemonic == "vceq" ||
1430      Mnemonic == "movs" ||
1431      Mnemonic == "svc" ||
1432      (Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
1433       Mnemonic == "vmls" || Mnemonic == "vnmls") ||
1434      Mnemonic == "vacge" || Mnemonic == "vcge" ||
1435      Mnemonic == "vclt" ||
1436      Mnemonic == "vacgt" || Mnemonic == "vcgt" ||
1437      Mnemonic == "vcle" ||
1438      (Mnemonic == "smlal" || Mnemonic == "umaal" || Mnemonic == "umlal" ||
1439       Mnemonic == "vabal" || Mnemonic == "vmlal" || Mnemonic == "vpadal" ||
1440       Mnemonic == "vqdmlal"))
1441    return Mnemonic;
1442
1443  // First, split out any predication code.
1444  unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
1445    .Case("eq", ARMCC::EQ)
1446    .Case("ne", ARMCC::NE)
1447    .Case("hs", ARMCC::HS)
1448    .Case("lo", ARMCC::LO)
1449    .Case("mi", ARMCC::MI)
1450    .Case("pl", ARMCC::PL)
1451    .Case("vs", ARMCC::VS)
1452    .Case("vc", ARMCC::VC)
1453    .Case("hi", ARMCC::HI)
1454    .Case("ls", ARMCC::LS)
1455    .Case("ge", ARMCC::GE)
1456    .Case("lt", ARMCC::LT)
1457    .Case("gt", ARMCC::GT)
1458    .Case("le", ARMCC::LE)
1459    .Case("al", ARMCC::AL)
1460    .Default(~0U);
1461  if (CC != ~0U) {
1462    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
1463    PredicationCode = CC;
1464  }
1465
1466  // Next, determine if we have a carry setting bit. We explicitly ignore all
1467  // the instructions we know end in 's'.
1468  if (Mnemonic.endswith("s") &&
1469      !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" ||
1470        Mnemonic == "movs" || Mnemonic == "mrs" || Mnemonic == "smmls" ||
1471        Mnemonic == "vabs" || Mnemonic == "vcls" || Mnemonic == "vmls" ||
1472        Mnemonic == "vmrs" || Mnemonic == "vnmls" || Mnemonic == "vqabs" ||
1473        Mnemonic == "vrecps" || Mnemonic == "vrsqrts")) {
1474    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
1475    CarrySetting = true;
1476  }
1477
1478  // The "cps" instruction can have a interrupt mode operand which is glued into
1479  // the mnemonic. Check if this is the case, split it and parse the imod op
1480  if (Mnemonic.startswith("cps")) {
1481    // Split out any imod code.
1482    unsigned IMod =
1483      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
1484      .Case("ie", ARM_PROC::IE)
1485      .Case("id", ARM_PROC::ID)
1486      .Default(~0U);
1487    if (IMod != ~0U) {
1488      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
1489      ProcessorIMod = IMod;
1490    }
1491  }
1492
1493  return Mnemonic;
1494}
1495
1496/// \brief Given a canonical mnemonic, determine if the instruction ever allows
1497/// inclusion of carry set or predication code operands.
1498//
1499// FIXME: It would be nice to autogen this.
1500void ARMAsmParser::
1501GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
1502                      bool &CanAcceptPredicationCode) {
1503  bool isThumb = TM.getSubtarget<ARMSubtarget>().isThumb();
1504
1505  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
1506      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
1507      Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
1508      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
1509      Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mov" ||
1510      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
1511      Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
1512      Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "mvn") {
1513    CanAcceptCarrySet = true;
1514  } else {
1515    CanAcceptCarrySet = false;
1516  }
1517
1518  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
1519      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
1520      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
1521      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
1522      Mnemonic == "dsb" || Mnemonic == "movs" || Mnemonic == "isb" ||
1523      Mnemonic == "clrex" || Mnemonic.startswith("cps")) {
1524    CanAcceptPredicationCode = false;
1525  } else {
1526    CanAcceptPredicationCode = true;
1527  }
1528
1529  if (isThumb)
1530    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
1531        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
1532      CanAcceptPredicationCode = false;
1533}
1534
1535/// Parse an arm instruction mnemonic followed by its operands.
1536bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
1537                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1538  // Create the leading tokens for the mnemonic, split by '.' characters.
1539  size_t Start = 0, Next = Name.find('.');
1540  StringRef Head = Name.slice(Start, Next);
1541
1542  // Split out the predication code and carry setting flag from the mnemonic.
1543  unsigned PredicationCode;
1544  unsigned ProcessorIMod;
1545  bool CarrySetting;
1546  Head = SplitMnemonic(Head, PredicationCode, CarrySetting,
1547                       ProcessorIMod);
1548
1549  Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
1550
1551  // Next, add the CCOut and ConditionCode operands, if needed.
1552  //
1553  // For mnemonics which can ever incorporate a carry setting bit or predication
1554  // code, our matching model involves us always generating CCOut and
1555  // ConditionCode operands to match the mnemonic "as written" and then we let
1556  // the matcher deal with finding the right instruction or generating an
1557  // appropriate error.
1558  bool CanAcceptCarrySet, CanAcceptPredicationCode;
1559  GetMnemonicAcceptInfo(Head, CanAcceptCarrySet, CanAcceptPredicationCode);
1560
1561  // Add the carry setting operand, if necessary.
1562  //
1563  // FIXME: It would be awesome if we could somehow invent a location such that
1564  // match errors on this operand would print a nice diagnostic about how the
1565  // 's' character in the mnemonic resulted in a CCOut operand.
1566  if (CanAcceptCarrySet) {
1567    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
1568                                               NameLoc));
1569  } else {
1570    // This mnemonic can't ever accept a carry set, but the user wrote one (or
1571    // misspelled another mnemonic).
1572
1573    // FIXME: Issue a nice error.
1574  }
1575
1576  // Add the predication code operand, if necessary.
1577  if (CanAcceptPredicationCode) {
1578    Operands.push_back(ARMOperand::CreateCondCode(
1579                         ARMCC::CondCodes(PredicationCode), NameLoc));
1580  } else {
1581    // This mnemonic can't ever accept a predication code, but the user wrote
1582    // one (or misspelled another mnemonic).
1583
1584    // FIXME: Issue a nice error.
1585  }
1586
1587  // Add the processor imod operand, if necessary.
1588  if (ProcessorIMod) {
1589    Operands.push_back(ARMOperand::CreateImm(
1590          MCConstantExpr::Create(ProcessorIMod, getContext()),
1591                                 NameLoc, NameLoc));
1592  } else {
1593    // This mnemonic can't ever accept a imod, but the user wrote
1594    // one (or misspelled another mnemonic).
1595
1596    // FIXME: Issue a nice error.
1597  }
1598
1599  // Add the remaining tokens in the mnemonic.
1600  while (Next != StringRef::npos) {
1601    Start = Next;
1602    Next = Name.find('.', Start + 1);
1603    StringRef ExtraToken = Name.slice(Start, Next);
1604
1605    Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
1606  }
1607
1608  // Read the remaining operands.
1609  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1610    // Read the first operand.
1611    if (ParseOperand(Operands, Head)) {
1612      Parser.EatToEndOfStatement();
1613      return true;
1614    }
1615
1616    while (getLexer().is(AsmToken::Comma)) {
1617      Parser.Lex();  // Eat the comma.
1618
1619      // Parse and remember the operand.
1620      if (ParseOperand(Operands, Head)) {
1621        Parser.EatToEndOfStatement();
1622        return true;
1623      }
1624    }
1625  }
1626
1627  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1628    Parser.EatToEndOfStatement();
1629    return TokError("unexpected token in argument list");
1630  }
1631
1632  Parser.Lex(); // Consume the EndOfStatement
1633  return false;
1634}
1635
1636bool ARMAsmParser::
1637MatchAndEmitInstruction(SMLoc IDLoc,
1638                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1639                        MCStreamer &Out) {
1640  MCInst Inst;
1641  unsigned ErrorInfo;
1642  MatchResultTy MatchResult, MatchResult2;
1643  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
1644  if (MatchResult != Match_Success) {
1645    // If we get a Match_InvalidOperand it might be some arithmetic instruction
1646    // that does not update the condition codes.  So try adding a CCOut operand
1647    // with a value of reg0.
1648    if (MatchResult == Match_InvalidOperand) {
1649      Operands.insert(Operands.begin() + 1,
1650                      ARMOperand::CreateCCOut(0,
1651                                  ((ARMOperand*)Operands[0])->getStartLoc()));
1652      MatchResult2 = MatchInstructionImpl(Operands, Inst, ErrorInfo);
1653      if (MatchResult2 == Match_Success)
1654        MatchResult = Match_Success;
1655      else {
1656        ARMOperand *CCOut = ((ARMOperand*)Operands[1]);
1657        Operands.erase(Operands.begin() + 1);
1658        delete CCOut;
1659      }
1660    }
1661    // If we get a Match_MnemonicFail it might be some arithmetic instruction
1662    // that updates the condition codes if it ends in 's'.  So see if the
1663    // mnemonic ends in 's' and if so try removing the 's' and adding a CCOut
1664    // operand with a value of CPSR.
1665    else if(MatchResult == Match_MnemonicFail) {
1666      // Get the instruction mnemonic, which is the first token.
1667      StringRef Mnemonic = ((ARMOperand*)Operands[0])->getToken();
1668      if (Mnemonic.substr(Mnemonic.size()-1) == "s") {
1669        // removed the 's' from the mnemonic for matching.
1670        StringRef MnemonicNoS = Mnemonic.slice(0, Mnemonic.size() - 1);
1671        SMLoc NameLoc = ((ARMOperand*)Operands[0])->getStartLoc();
1672        ARMOperand *OldMnemonic = ((ARMOperand*)Operands[0]);
1673        Operands.erase(Operands.begin());
1674        delete OldMnemonic;
1675        Operands.insert(Operands.begin(),
1676                        ARMOperand::CreateToken(MnemonicNoS, NameLoc));
1677        Operands.insert(Operands.begin() + 1,
1678                        ARMOperand::CreateCCOut(ARM::CPSR, NameLoc));
1679        MatchResult2 = MatchInstructionImpl(Operands, Inst, ErrorInfo);
1680        if (MatchResult2 == Match_Success)
1681          MatchResult = Match_Success;
1682        else {
1683          ARMOperand *OldMnemonic = ((ARMOperand*)Operands[0]);
1684          Operands.erase(Operands.begin());
1685          delete OldMnemonic;
1686          Operands.insert(Operands.begin(),
1687                          ARMOperand::CreateToken(Mnemonic, NameLoc));
1688          ARMOperand *CCOut = ((ARMOperand*)Operands[1]);
1689          Operands.erase(Operands.begin() + 1);
1690          delete CCOut;
1691        }
1692      }
1693    }
1694  }
1695  switch (MatchResult) {
1696  case Match_Success:
1697    Out.EmitInstruction(Inst);
1698    return false;
1699  case Match_MissingFeature:
1700    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1701    return true;
1702  case Match_InvalidOperand: {
1703    SMLoc ErrorLoc = IDLoc;
1704    if (ErrorInfo != ~0U) {
1705      if (ErrorInfo >= Operands.size())
1706        return Error(IDLoc, "too few operands for instruction");
1707
1708      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
1709      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1710    }
1711
1712    return Error(ErrorLoc, "invalid operand for instruction");
1713  }
1714  case Match_MnemonicFail:
1715    return Error(IDLoc, "unrecognized instruction mnemonic");
1716  case Match_ConversionFail:
1717    return Error(IDLoc, "unable to convert operands to instruction");
1718  }
1719
1720  llvm_unreachable("Implement any new match types added!");
1721  return true;
1722}
1723
1724/// ParseDirective parses the arm specific directives
1725bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
1726  StringRef IDVal = DirectiveID.getIdentifier();
1727  if (IDVal == ".word")
1728    return ParseDirectiveWord(4, DirectiveID.getLoc());
1729  else if (IDVal == ".thumb")
1730    return ParseDirectiveThumb(DirectiveID.getLoc());
1731  else if (IDVal == ".thumb_func")
1732    return ParseDirectiveThumbFunc(DirectiveID.getLoc());
1733  else if (IDVal == ".code")
1734    return ParseDirectiveCode(DirectiveID.getLoc());
1735  else if (IDVal == ".syntax")
1736    return ParseDirectiveSyntax(DirectiveID.getLoc());
1737  return true;
1738}
1739
1740/// ParseDirectiveWord
1741///  ::= .word [ expression (, expression)* ]
1742bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1743  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1744    for (;;) {
1745      const MCExpr *Value;
1746      if (getParser().ParseExpression(Value))
1747        return true;
1748
1749      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
1750
1751      if (getLexer().is(AsmToken::EndOfStatement))
1752        break;
1753
1754      // FIXME: Improve diagnostic.
1755      if (getLexer().isNot(AsmToken::Comma))
1756        return Error(L, "unexpected token in directive");
1757      Parser.Lex();
1758    }
1759  }
1760
1761  Parser.Lex();
1762  return false;
1763}
1764
1765/// ParseDirectiveThumb
1766///  ::= .thumb
1767bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
1768  if (getLexer().isNot(AsmToken::EndOfStatement))
1769    return Error(L, "unexpected token in directive");
1770  Parser.Lex();
1771
1772  // TODO: set thumb mode
1773  // TODO: tell the MC streamer the mode
1774  // getParser().getStreamer().Emit???();
1775  return false;
1776}
1777
1778/// ParseDirectiveThumbFunc
1779///  ::= .thumbfunc symbol_name
1780bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
1781  const AsmToken &Tok = Parser.getTok();
1782  if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
1783    return Error(L, "unexpected token in .thumb_func directive");
1784  StringRef Name = Tok.getString();
1785  Parser.Lex(); // Consume the identifier token.
1786  if (getLexer().isNot(AsmToken::EndOfStatement))
1787    return Error(L, "unexpected token in directive");
1788  Parser.Lex();
1789
1790  // Mark symbol as a thumb symbol.
1791  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
1792  getParser().getStreamer().EmitThumbFunc(Func);
1793  return false;
1794}
1795
1796/// ParseDirectiveSyntax
1797///  ::= .syntax unified | divided
1798bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
1799  const AsmToken &Tok = Parser.getTok();
1800  if (Tok.isNot(AsmToken::Identifier))
1801    return Error(L, "unexpected token in .syntax directive");
1802  StringRef Mode = Tok.getString();
1803  if (Mode == "unified" || Mode == "UNIFIED")
1804    Parser.Lex();
1805  else if (Mode == "divided" || Mode == "DIVIDED")
1806    return Error(L, "'.syntax divided' arm asssembly not supported");
1807  else
1808    return Error(L, "unrecognized syntax mode in .syntax directive");
1809
1810  if (getLexer().isNot(AsmToken::EndOfStatement))
1811    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
1812  Parser.Lex();
1813
1814  // TODO tell the MC streamer the mode
1815  // getParser().getStreamer().Emit???();
1816  return false;
1817}
1818
1819/// ParseDirectiveCode
1820///  ::= .code 16 | 32
1821bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
1822  const AsmToken &Tok = Parser.getTok();
1823  if (Tok.isNot(AsmToken::Integer))
1824    return Error(L, "unexpected token in .code directive");
1825  int64_t Val = Parser.getTok().getIntVal();
1826  if (Val == 16)
1827    Parser.Lex();
1828  else if (Val == 32)
1829    Parser.Lex();
1830  else
1831    return Error(L, "invalid operand to .code directive");
1832
1833  if (getLexer().isNot(AsmToken::EndOfStatement))
1834    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
1835  Parser.Lex();
1836
1837  // FIXME: We need to be able switch subtargets at this point so that
1838  // MatchInstructionImpl() will work when it gets the AvailableFeatures which
1839  // includes Feature_IsThumb or not to match the right instructions.  This is
1840  // blocked on the FIXME in llvm-mc.cpp when creating the TargetMachine.
1841  if (Val == 16){
1842    assert(TM.getSubtarget<ARMSubtarget>().isThumb() &&
1843	   "switching between arm/thumb not yet suppported via .code 16)");
1844    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
1845  }
1846  else{
1847    assert(!TM.getSubtarget<ARMSubtarget>().isThumb() &&
1848           "switching between thumb/arm not yet suppported via .code 32)");
1849    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
1850   }
1851
1852  return false;
1853}
1854
1855extern "C" void LLVMInitializeARMAsmLexer();
1856
1857/// Force static initialization.
1858extern "C" void LLVMInitializeARMAsmParser() {
1859  RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
1860  RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
1861  LLVMInitializeARMAsmLexer();
1862}
1863
1864#define GET_REGISTER_MATCHER
1865#define GET_MATCHER_IMPLEMENTATION
1866#include "ARMGenAsmMatcher.inc"
1867