ARMRegisterInfo.cpp revision 193323
110154Sache//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===// 210154Sache// 37767Sache// The LLVM Compiler Infrastructure 4941Snate// 510154Sache// This file is distributed under the University of Illinois Open Source 610154Sache// License. See LICENSE.TXT for details. 710154Sache// 810154Sache//===----------------------------------------------------------------------===// 910154Sache// 1010154Sache// This file contains the ARM implementation of the TargetRegisterInfo class. 1110154Sache// 1210154Sache//===----------------------------------------------------------------------===// 13941Snate 1410154Sache#include "ARM.h" 1510154Sache#include "ARMAddressingModes.h" 1610154Sache#include "ARMInstrInfo.h" 1710154Sache#include "ARMMachineFunctionInfo.h" 1810154Sache#include "ARMRegisterInfo.h" 1910154Sache#include "ARMSubtarget.h" 2010154Sache#include "llvm/Constants.h" 2110154Sache#include "llvm/DerivedTypes.h" 2210154Sache#include "llvm/CodeGen/MachineConstantPool.h" 2310154Sache#include "llvm/CodeGen/MachineFrameInfo.h" 2454158Scharnier#include "llvm/CodeGen/MachineFunction.h" 2554158Scharnier#include "llvm/CodeGen/MachineInstrBuilder.h" 26941Snate#include "llvm/CodeGen/MachineLocation.h" 27941Snate#include "llvm/CodeGen/MachineRegisterInfo.h" 28941Snate#include "llvm/CodeGen/RegisterScavenging.h" 29941Snate#include "llvm/Target/TargetFrameInfo.h" 30941Snate#include "llvm/Target/TargetMachine.h" 31941Snate#include "llvm/Target/TargetOptions.h" 32941Snate#include "llvm/ADT/BitVector.h" 337767Sache#include "llvm/ADT/SmallVector.h" 3482973Sru#include "llvm/ADT/STLExtras.h" 3582973Sru#include "llvm/Support/CommandLine.h" 3654158Scharnier#include <algorithm> 37941Snateusing namespace llvm; 387767Sache 39941Snatestatic cl::opt<bool> ThumbRegScavenging("enable-thumb-reg-scavenging", 40941Snate cl::Hidden, 41941Snate cl::desc("Enable register scavenging on Thumb")); 427767Sache 43941Snateunsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 44941Snate using namespace ARM; 45941Snate switch (RegEnum) { 46941Snate case R0: case S0: case D0: return 0; 47941Snate case R1: case S1: case D1: return 1; 487767Sache case R2: case S2: case D2: return 2; 49941Snate case R3: case S3: case D3: return 3; 50941Snate case R4: case S4: case D4: return 4; 51941Snate case R5: case S5: case D5: return 5; 52941Snate case R6: case S6: case D6: return 6; 53941Snate case R7: case S7: case D7: return 7; 54941Snate case R8: case S8: case D8: return 8; 55941Snate case R9: case S9: case D9: return 9; 56941Snate case R10: case S10: case D10: return 10; 57941Snate case R11: case S11: case D11: return 11; 5854158Scharnier case R12: case S12: case D12: return 12; 59941Snate case SP: case S13: case D13: return 13; 60941Snate case LR: case S14: case D14: return 14; 61941Snate case PC: case S15: case D15: return 15; 62241737Sed case S16: return 16; 63241737Sed case S17: return 17; 64241737Sed case S18: return 18; 65241737Sed case S19: return 19; 66227269Sed case S20: return 20; 67241737Sed case S21: return 21; 68227269Sed case S22: return 22; 69227269Sed case S23: return 23; 70941Snate case S24: return 24; 7182973Sru case S25: return 25; 7282973Sru case S26: return 26; 7382973Sru case S27: return 27; 7482973Sru case S28: return 28; 75241852Seadler case S29: return 29; 76241852Seadler case S30: return 30; 7782973Sru case S31: return 31; 78941Snate default: 7982973Sru assert(0 && "Unknown ARM register!"); 8082973Sru abort(); 8182973Sru } 8282973Sru} 8382973Sru 84241852Seadlerunsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum, 85241852Seadler bool &isSPVFP) { 8682973Sru isSPVFP = false; 87941Snate 8882973Sru using namespace ARM; 89241852Seadler switch (RegEnum) { 90241852Seadler default: 9182973Sru assert(0 && "Unknown ARM register!"); 92941Snate abort(); 9382973Sru case R0: case D0: return 0; 94241852Seadler case R1: case D1: return 1; 95241852Seadler case R2: case D2: return 2; 9682973Sru case R3: case D3: return 3; 97941Snate case R4: case D4: return 4; 9882973Sru case R5: case D5: return 5; 9982973Sru case R6: case D6: return 6; 10082973Sru case R7: case D7: return 7; 10182973Sru case R8: case D8: return 8; 102249404Sgahr case R9: case D9: return 9; 103241852Seadler case R10: case D10: return 10; 10482973Sru case R11: case D11: return 11; 10582973Sru case R12: case D12: return 12; 106941Snate case SP: case D13: return 13; 107 case LR: case D14: return 14; 108 case PC: case D15: return 15; 109 110 case S0: case S1: case S2: case S3: 111 case S4: case S5: case S6: case S7: 112 case S8: case S9: case S10: case S11: 113 case S12: case S13: case S14: case S15: 114 case S16: case S17: case S18: case S19: 115 case S20: case S21: case S22: case S23: 116 case S24: case S25: case S26: case S27: 117 case S28: case S29: case S30: case S31: { 118 isSPVFP = true; 119 switch (RegEnum) { 120 default: return 0; // Avoid compile time warning. 121 case S0: return 0; 122 case S1: return 1; 123 case S2: return 2; 124 case S3: return 3; 125 case S4: return 4; 126 case S5: return 5; 127 case S6: return 6; 128 case S7: return 7; 129 case S8: return 8; 130 case S9: return 9; 131 case S10: return 10; 132 case S11: return 11; 133 case S12: return 12; 134 case S13: return 13; 135 case S14: return 14; 136 case S15: return 15; 137 case S16: return 16; 138 case S17: return 17; 139 case S18: return 18; 140 case S19: return 19; 141 case S20: return 20; 142 case S21: return 21; 143 case S22: return 22; 144 case S23: return 23; 145 case S24: return 24; 146 case S25: return 25; 147 case S26: return 26; 148 case S27: return 27; 149 case S28: return 28; 150 case S29: return 29; 151 case S30: return 30; 152 case S31: return 31; 153 } 154 } 155 } 156} 157 158ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii, 159 const ARMSubtarget &sti) 160 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 161 TII(tii), STI(sti), 162 FramePtr((STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11) { 163} 164 165static inline 166const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { 167 return MIB.addImm((int64_t)ARMCC::AL).addReg(0); 168} 169 170static inline 171const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { 172 return MIB.addReg(0); 173} 174 175/// emitLoadConstPool - Emits a load from constpool to materialize the 176/// specified immediate. 177void ARMRegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB, 178 MachineBasicBlock::iterator &MBBI, 179 unsigned DestReg, int Val, 180 unsigned Pred, unsigned PredReg, 181 const TargetInstrInfo *TII, 182 bool isThumb, 183 DebugLoc dl) const { 184 MachineFunction &MF = *MBB.getParent(); 185 MachineConstantPool *ConstantPool = MF.getConstantPool(); 186 Constant *C = ConstantInt::get(Type::Int32Ty, Val); 187 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 188 if (isThumb) 189 BuildMI(MBB, MBBI, dl, 190 TII->get(ARM::tLDRcp),DestReg).addConstantPoolIndex(Idx); 191 else 192 BuildMI(MBB, MBBI, dl, TII->get(ARM::LDRcp), DestReg) 193 .addConstantPoolIndex(Idx) 194 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 195} 196 197const TargetRegisterClass *ARMRegisterInfo::getPointerRegClass() const { 198 return &ARM::GPRRegClass; 199} 200 201/// isLowRegister - Returns true if the register is low register r0-r7. 202/// 203bool ARMRegisterInfo::isLowRegister(unsigned Reg) const { 204 using namespace ARM; 205 switch (Reg) { 206 case R0: case R1: case R2: case R3: 207 case R4: case R5: case R6: case R7: 208 return true; 209 default: 210 return false; 211 } 212} 213 214const TargetRegisterClass* 215ARMRegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, MVT VT) const { 216 if (STI.isThumb()) { 217 if (isLowRegister(Reg)) 218 return ARM::tGPRRegisterClass; 219 switch (Reg) { 220 default: 221 break; 222 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 223 case ARM::R12: case ARM::SP: case ARM::LR: case ARM::PC: 224 return ARM::GPRRegisterClass; 225 } 226 } 227 return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT); 228} 229 230const unsigned* 231ARMRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 232 static const unsigned CalleeSavedRegs[] = { 233 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 234 ARM::R7, ARM::R6, ARM::R5, ARM::R4, 235 236 ARM::D15, ARM::D14, ARM::D13, ARM::D12, 237 ARM::D11, ARM::D10, ARM::D9, ARM::D8, 238 0 239 }; 240 241 static const unsigned DarwinCalleeSavedRegs[] = { 242 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 243 ARM::R11, ARM::R10, ARM::R9, ARM::R8, 244 245 ARM::D15, ARM::D14, ARM::D13, ARM::D12, 246 ARM::D11, ARM::D10, ARM::D9, ARM::D8, 247 0 248 }; 249 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 250} 251 252const TargetRegisterClass* const * 253ARMRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 254 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 255 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 256 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 257 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 258 259 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 260 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 261 0 262 }; 263 static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = { 264 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 265 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass, 266 &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass, 267 268 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 269 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 270 0 271 }; 272 return STI.isThumb() ? ThumbCalleeSavedRegClasses : CalleeSavedRegClasses; 273} 274 275BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 276 // FIXME: avoid re-calculating this everytime. 277 BitVector Reserved(getNumRegs()); 278 Reserved.set(ARM::SP); 279 Reserved.set(ARM::PC); 280 if (STI.isTargetDarwin() || hasFP(MF)) 281 Reserved.set(FramePtr); 282 // Some targets reserve R9. 283 if (STI.isR9Reserved()) 284 Reserved.set(ARM::R9); 285 return Reserved; 286} 287 288bool 289ARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const { 290 switch (Reg) { 291 default: break; 292 case ARM::SP: 293 case ARM::PC: 294 return true; 295 case ARM::R7: 296 case ARM::R11: 297 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF))) 298 return true; 299 break; 300 case ARM::R9: 301 return STI.isR9Reserved(); 302 } 303 304 return false; 305} 306 307bool 308ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { 309 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 310 return ThumbRegScavenging || !AFI->isThumbFunction(); 311} 312 313/// hasFP - Return true if the specified function should have a dedicated frame 314/// pointer register. This is true if the function has variable sized allocas 315/// or if frame pointer elimination is disabled. 316/// 317bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const { 318 const MachineFrameInfo *MFI = MF.getFrameInfo(); 319 return NoFramePointerElim || MFI->hasVarSizedObjects(); 320} 321 322// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 323// not required, we reserve argument space for call sites in the function 324// immediately on entry to the current function. This eliminates the need for 325// add/sub sp brackets around call sites. Returns true if the call frame is 326// included as part of the stack frame. 327bool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const { 328 const MachineFrameInfo *FFI = MF.getFrameInfo(); 329 unsigned CFSize = FFI->getMaxCallFrameSize(); 330 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 331 // It's not always a good idea to include the call frame as part of the 332 // stack frame. ARM (especially Thumb) has small immediate offset to 333 // address the stack frame. So a large call frame can cause poor codegen 334 // and may even makes it impossible to scavenge a register. 335 if (AFI->isThumbFunction()) { 336 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4 337 return false; 338 } else { 339 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 340 return false; 341 } 342 return !MF.getFrameInfo()->hasVarSizedObjects(); 343} 344 345/// emitARMRegPlusImmediate - Emits a series of instructions to materialize 346/// a destreg = basereg + immediate in ARM code. 347static 348void emitARMRegPlusImmediate(MachineBasicBlock &MBB, 349 MachineBasicBlock::iterator &MBBI, 350 unsigned DestReg, unsigned BaseReg, int NumBytes, 351 ARMCC::CondCodes Pred, unsigned PredReg, 352 const TargetInstrInfo &TII, 353 DebugLoc dl) { 354 bool isSub = NumBytes < 0; 355 if (isSub) NumBytes = -NumBytes; 356 357 while (NumBytes) { 358 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 359 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 360 assert(ThisVal && "Didn't extract field correctly"); 361 362 // We will handle these bits from offset, clear them. 363 NumBytes &= ~ThisVal; 364 365 // Get the properly encoded SOImmVal field. 366 int SOImmVal = ARM_AM::getSOImmVal(ThisVal); 367 assert(SOImmVal != -1 && "Bit extraction didn't work?"); 368 369 // Build the new ADD / SUB. 370 BuildMI(MBB, MBBI, dl, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) 371 .addReg(BaseReg, RegState::Kill).addImm(SOImmVal) 372 .addImm((unsigned)Pred).addReg(PredReg).addReg(0); 373 BaseReg = DestReg; 374 } 375} 376 377/// calcNumMI - Returns the number of instructions required to materialize 378/// the specific add / sub r, c instruction. 379static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, 380 unsigned NumBits, unsigned Scale) { 381 unsigned NumMIs = 0; 382 unsigned Chunk = ((1 << NumBits) - 1) * Scale; 383 384 if (Opc == ARM::tADDrSPi) { 385 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 386 Bytes -= ThisVal; 387 NumMIs++; 388 NumBits = 8; 389 Scale = 1; // Followed by a number of tADDi8. 390 Chunk = ((1 << NumBits) - 1) * Scale; 391 } 392 393 NumMIs += Bytes / Chunk; 394 if ((Bytes % Chunk) != 0) 395 NumMIs++; 396 if (ExtraOpc) 397 NumMIs++; 398 return NumMIs; 399} 400 401/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize 402/// a destreg = basereg + immediate in Thumb code. Materialize the immediate 403/// in a register using mov / mvn sequences or load the immediate from a 404/// constpool entry. 405static 406void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, 407 MachineBasicBlock::iterator &MBBI, 408 unsigned DestReg, unsigned BaseReg, 409 int NumBytes, bool CanChangeCC, 410 const TargetInstrInfo &TII, 411 const ARMRegisterInfo& MRI, 412 DebugLoc dl) { 413 bool isHigh = !MRI.isLowRegister(DestReg) || 414 (BaseReg != 0 && !MRI.isLowRegister(BaseReg)); 415 bool isSub = false; 416 // Subtract doesn't have high register version. Load the negative value 417 // if either base or dest register is a high register. Also, if do not 418 // issue sub as part of the sequence if condition register is to be 419 // preserved. 420 if (NumBytes < 0 && !isHigh && CanChangeCC) { 421 isSub = true; 422 NumBytes = -NumBytes; 423 } 424 unsigned LdReg = DestReg; 425 if (DestReg == ARM::SP) { 426 assert(BaseReg == ARM::SP && "Unexpected!"); 427 LdReg = ARM::R3; 428 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::R12) 429 .addReg(ARM::R3, RegState::Kill); 430 } 431 432 if (NumBytes <= 255 && NumBytes >= 0) 433 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); 434 else if (NumBytes < 0 && NumBytes >= -255) { 435 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); 436 BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg) 437 .addReg(LdReg, RegState::Kill); 438 } else 439 MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, &TII, 440 true, dl); 441 442 // Emit add / sub. 443 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); 444 const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, 445 TII.get(Opc), DestReg); 446 if (DestReg == ARM::SP || isSub) 447 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); 448 else 449 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); 450 if (DestReg == ARM::SP) 451 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVhir2lor), ARM::R3) 452 .addReg(ARM::R12, RegState::Kill); 453} 454 455/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize 456/// a destreg = basereg + immediate in Thumb code. 457static 458void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 459 MachineBasicBlock::iterator &MBBI, 460 unsigned DestReg, unsigned BaseReg, 461 int NumBytes, const TargetInstrInfo &TII, 462 const ARMRegisterInfo& MRI, 463 DebugLoc dl) { 464 bool isSub = NumBytes < 0; 465 unsigned Bytes = (unsigned)NumBytes; 466 if (isSub) Bytes = -NumBytes; 467 bool isMul4 = (Bytes & 3) == 0; 468 bool isTwoAddr = false; 469 bool DstNotEqBase = false; 470 unsigned NumBits = 1; 471 unsigned Scale = 1; 472 int Opc = 0; 473 int ExtraOpc = 0; 474 475 if (DestReg == BaseReg && BaseReg == ARM::SP) { 476 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!"); 477 NumBits = 7; 478 Scale = 4; 479 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 480 isTwoAddr = true; 481 } else if (!isSub && BaseReg == ARM::SP) { 482 // r1 = add sp, 403 483 // => 484 // r1 = add sp, 100 * 4 485 // r1 = add r1, 3 486 if (!isMul4) { 487 Bytes &= ~3; 488 ExtraOpc = ARM::tADDi3; 489 } 490 NumBits = 8; 491 Scale = 4; 492 Opc = ARM::tADDrSPi; 493 } else { 494 // sp = sub sp, c 495 // r1 = sub sp, c 496 // r8 = sub sp, c 497 if (DestReg != BaseReg) 498 DstNotEqBase = true; 499 NumBits = 8; 500 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 501 isTwoAddr = true; 502 } 503 504 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale); 505 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2; 506 if (NumMIs > Threshold) { 507 // This will expand into too many instructions. Load the immediate from a 508 // constpool entry. 509 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII, 510 MRI, dl); 511 return; 512 } 513 514 if (DstNotEqBase) { 515 if (MRI.isLowRegister(DestReg) && MRI.isLowRegister(BaseReg)) { 516 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) 517 unsigned Chunk = (1 << 3) - 1; 518 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 519 Bytes -= ThisVal; 520 BuildMI(MBB, MBBI, dl,TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) 521 .addReg(BaseReg, RegState::Kill).addImm(ThisVal); 522 } else { 523 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) 524 .addReg(BaseReg, RegState::Kill); 525 } 526 BaseReg = DestReg; 527 } 528 529 unsigned Chunk = ((1 << NumBits) - 1) * Scale; 530 while (Bytes) { 531 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; 532 Bytes -= ThisVal; 533 ThisVal /= Scale; 534 // Build the new tADD / tSUB. 535 if (isTwoAddr) 536 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 537 .addReg(DestReg).addImm(ThisVal); 538 else { 539 bool isKill = BaseReg != ARM::SP; 540 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 541 .addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal); 542 BaseReg = DestReg; 543 544 if (Opc == ARM::tADDrSPi) { 545 // r4 = add sp, imm 546 // r4 = add r4, imm 547 // ... 548 NumBits = 8; 549 Scale = 1; 550 Chunk = ((1 << NumBits) - 1) * Scale; 551 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; 552 isTwoAddr = true; 553 } 554 } 555 } 556 557 if (ExtraOpc) 558 BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg) 559 .addReg(DestReg, RegState::Kill) 560 .addImm(((unsigned)NumBytes) & 3); 561} 562 563static 564void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 565 int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, 566 bool isThumb, const TargetInstrInfo &TII, 567 const ARMRegisterInfo& MRI, 568 DebugLoc dl) { 569 if (isThumb) 570 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII, 571 MRI, dl); 572 else 573 emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, 574 Pred, PredReg, TII, dl); 575} 576 577void ARMRegisterInfo:: 578eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 579 MachineBasicBlock::iterator I) const { 580 if (!hasReservedCallFrame(MF)) { 581 // If we have alloca, convert as follows: 582 // ADJCALLSTACKDOWN -> sub, sp, sp, amount 583 // ADJCALLSTACKUP -> add, sp, sp, amount 584 MachineInstr *Old = I; 585 DebugLoc dl = Old->getDebugLoc(); 586 unsigned Amount = Old->getOperand(0).getImm(); 587 if (Amount != 0) { 588 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 589 // We need to keep the stack aligned properly. To do this, we round the 590 // amount of space needed for the outgoing arguments up to the next 591 // alignment boundary. 592 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 593 Amount = (Amount+Align-1)/Align*Align; 594 595 // Replace the pseudo instruction with a new instruction... 596 unsigned Opc = Old->getOpcode(); 597 bool isThumb = AFI->isThumbFunction(); 598 ARMCC::CondCodes Pred = isThumb 599 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImm(); 600 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 601 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 602 unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg(); 603 emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII, *this, dl); 604 } else { 605 // Note: PredReg is operand 3 for ADJCALLSTACKUP. 606 unsigned PredReg = isThumb ? 0 : Old->getOperand(3).getReg(); 607 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 608 emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII, *this, dl); 609 } 610 } 611 } 612 MBB.erase(I); 613} 614 615/// emitThumbConstant - Emit a series of instructions to materialize a 616/// constant. 617static void emitThumbConstant(MachineBasicBlock &MBB, 618 MachineBasicBlock::iterator &MBBI, 619 unsigned DestReg, int Imm, 620 const TargetInstrInfo &TII, 621 const ARMRegisterInfo& MRI, 622 DebugLoc dl) { 623 bool isSub = Imm < 0; 624 if (isSub) Imm = -Imm; 625 626 int Chunk = (1 << 8) - 1; 627 int ThisVal = (Imm > Chunk) ? Chunk : Imm; 628 Imm -= ThisVal; 629 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal); 630 if (Imm > 0) 631 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl); 632 if (isSub) 633 BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), DestReg) 634 .addReg(DestReg, RegState::Kill); 635} 636 637/// findScratchRegister - Find a 'free' ARM register. If register scavenger 638/// is not being used, R12 is available. Otherwise, try for a call-clobbered 639/// register first and then a spilled callee-saved register if that fails. 640static 641unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC, 642 ARMFunctionInfo *AFI) { 643 unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12; 644 assert (!AFI->isThumbFunction()); 645 if (Reg == 0) 646 // Try a already spilled CS register. 647 Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters()); 648 649 return Reg; 650} 651 652void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 653 int SPAdj, RegScavenger *RS) const{ 654 unsigned i = 0; 655 MachineInstr &MI = *II; 656 MachineBasicBlock &MBB = *MI.getParent(); 657 MachineFunction &MF = *MBB.getParent(); 658 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 659 bool isThumb = AFI->isThumbFunction(); 660 DebugLoc dl = MI.getDebugLoc(); 661 662 while (!MI.getOperand(i).isFI()) { 663 ++i; 664 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 665 } 666 667 unsigned FrameReg = ARM::SP; 668 int FrameIndex = MI.getOperand(i).getIndex(); 669 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 670 MF.getFrameInfo()->getStackSize() + SPAdj; 671 672 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 673 Offset -= AFI->getGPRCalleeSavedArea1Offset(); 674 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 675 Offset -= AFI->getGPRCalleeSavedArea2Offset(); 676 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 677 Offset -= AFI->getDPRCalleeSavedAreaOffset(); 678 else if (hasFP(MF)) { 679 assert(SPAdj == 0 && "Unexpected"); 680 // There is alloca()'s in this function, must reference off the frame 681 // pointer instead. 682 FrameReg = getFrameRegister(MF); 683 Offset -= AFI->getFramePtrSpillOffset(); 684 } 685 686 unsigned Opcode = MI.getOpcode(); 687 const TargetInstrDesc &Desc = MI.getDesc(); 688 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 689 bool isSub = false; 690 691 // Memory operands in inline assembly always use AddrMode2. 692 if (Opcode == ARM::INLINEASM) 693 AddrMode = ARMII::AddrMode2; 694 695 if (Opcode == ARM::ADDri) { 696 Offset += MI.getOperand(i+1).getImm(); 697 if (Offset == 0) { 698 // Turn it into a move. 699 MI.setDesc(TII.get(ARM::MOVr)); 700 MI.getOperand(i).ChangeToRegister(FrameReg, false); 701 MI.RemoveOperand(i+1); 702 return; 703 } else if (Offset < 0) { 704 Offset = -Offset; 705 isSub = true; 706 MI.setDesc(TII.get(ARM::SUBri)); 707 } 708 709 // Common case: small offset, fits into instruction. 710 int ImmedOffset = ARM_AM::getSOImmVal(Offset); 711 if (ImmedOffset != -1) { 712 // Replace the FrameIndex with sp / fp 713 MI.getOperand(i).ChangeToRegister(FrameReg, false); 714 MI.getOperand(i+1).ChangeToImmediate(ImmedOffset); 715 return; 716 } 717 718 // Otherwise, we fallback to common code below to form the imm offset with 719 // a sequence of ADDri instructions. First though, pull as much of the imm 720 // into this ADDri as possible. 721 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 722 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 723 724 // We will handle these bits from offset, clear them. 725 Offset &= ~ThisImmVal; 726 727 // Get the properly encoded SOImmVal field. 728 int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal); 729 assert(ThisSOImmVal != -1 && "Bit extraction didn't work?"); 730 MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal); 731 } else if (Opcode == ARM::tADDrSPi) { 732 Offset += MI.getOperand(i+1).getImm(); 733 734 // Can't use tADDrSPi if it's based off the frame pointer. 735 unsigned NumBits = 0; 736 unsigned Scale = 1; 737 if (FrameReg != ARM::SP) { 738 Opcode = ARM::tADDi3; 739 MI.setDesc(TII.get(ARM::tADDi3)); 740 NumBits = 3; 741 } else { 742 NumBits = 8; 743 Scale = 4; 744 assert((Offset & 3) == 0 && 745 "Thumb add/sub sp, #imm immediate must be multiple of 4!"); 746 } 747 748 if (Offset == 0) { 749 // Turn it into a move. 750 MI.setDesc(TII.get(ARM::tMOVhir2lor)); 751 MI.getOperand(i).ChangeToRegister(FrameReg, false); 752 MI.RemoveOperand(i+1); 753 return; 754 } 755 756 // Common case: small offset, fits into instruction. 757 unsigned Mask = (1 << NumBits) - 1; 758 if (((Offset / Scale) & ~Mask) == 0) { 759 // Replace the FrameIndex with sp / fp 760 MI.getOperand(i).ChangeToRegister(FrameReg, false); 761 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale); 762 return; 763 } 764 765 unsigned DestReg = MI.getOperand(0).getReg(); 766 unsigned Bytes = (Offset > 0) ? Offset : -Offset; 767 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale); 768 // MI would expand into a large number of instructions. Don't try to 769 // simplify the immediate. 770 if (NumMIs > 2) { 771 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII, 772 *this, dl); 773 MBB.erase(II); 774 return; 775 } 776 777 if (Offset > 0) { 778 // Translate r0 = add sp, imm to 779 // r0 = add sp, 255*4 780 // r0 = add r0, (imm - 255*4) 781 MI.getOperand(i).ChangeToRegister(FrameReg, false); 782 MI.getOperand(i+1).ChangeToImmediate(Mask); 783 Offset = (Offset - Mask * Scale); 784 MachineBasicBlock::iterator NII = next(II); 785 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII, 786 *this, dl); 787 } else { 788 // Translate r0 = add sp, -imm to 789 // r0 = -imm (this is then translated into a series of instructons) 790 // r0 = add r0, sp 791 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl); 792 MI.setDesc(TII.get(ARM::tADDhirr)); 793 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true); 794 MI.getOperand(i+1).ChangeToRegister(FrameReg, false); 795 } 796 return; 797 } else { 798 unsigned ImmIdx = 0; 799 int InstrOffs = 0; 800 unsigned NumBits = 0; 801 unsigned Scale = 1; 802 switch (AddrMode) { 803 case ARMII::AddrMode2: { 804 ImmIdx = i+2; 805 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 806 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 807 InstrOffs *= -1; 808 NumBits = 12; 809 break; 810 } 811 case ARMII::AddrMode3: { 812 ImmIdx = i+2; 813 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 814 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 815 InstrOffs *= -1; 816 NumBits = 8; 817 break; 818 } 819 case ARMII::AddrMode5: { 820 ImmIdx = i+1; 821 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 822 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 823 InstrOffs *= -1; 824 NumBits = 8; 825 Scale = 4; 826 break; 827 } 828 case ARMII::AddrModeTs: { 829 ImmIdx = i+1; 830 InstrOffs = MI.getOperand(ImmIdx).getImm(); 831 NumBits = (FrameReg == ARM::SP) ? 8 : 5; 832 Scale = 4; 833 break; 834 } 835 default: 836 assert(0 && "Unsupported addressing mode!"); 837 abort(); 838 break; 839 } 840 841 Offset += InstrOffs * Scale; 842 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 843 if (Offset < 0 && !isThumb) { 844 Offset = -Offset; 845 isSub = true; 846 } 847 848 // Common case: small offset, fits into instruction. 849 MachineOperand &ImmOp = MI.getOperand(ImmIdx); 850 int ImmedOffset = Offset / Scale; 851 unsigned Mask = (1 << NumBits) - 1; 852 if ((unsigned)Offset <= Mask * Scale) { 853 // Replace the FrameIndex with sp 854 MI.getOperand(i).ChangeToRegister(FrameReg, false); 855 if (isSub) 856 ImmedOffset |= 1 << NumBits; 857 ImmOp.ChangeToImmediate(ImmedOffset); 858 return; 859 } 860 861 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill; 862 if (AddrMode == ARMII::AddrModeTs) { 863 // Thumb tLDRspi, tSTRspi. These will change to instructions that use 864 // a different base register. 865 NumBits = 5; 866 Mask = (1 << NumBits) - 1; 867 } 868 // If this is a thumb spill / restore, we will be using a constpool load to 869 // materialize the offset. 870 if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore) 871 ImmOp.ChangeToImmediate(0); 872 else { 873 // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 874 ImmedOffset = ImmedOffset & Mask; 875 if (isSub) 876 ImmedOffset |= 1 << NumBits; 877 ImmOp.ChangeToImmediate(ImmedOffset); 878 Offset &= ~(Mask*Scale); 879 } 880 } 881 882 // If we get here, the immediate doesn't fit into the instruction. We folded 883 // as much as possible above, handle the rest, providing a register that is 884 // SP+LargeImm. 885 assert(Offset && "This code isn't needed if offset already handled!"); 886 887 if (isThumb) { 888 if (Desc.mayLoad()) { 889 // Use the destination register to materialize sp + offset. 890 unsigned TmpReg = MI.getOperand(0).getReg(); 891 bool UseRR = false; 892 if (Opcode == ARM::tRestore) { 893 if (FrameReg == ARM::SP) 894 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg, 895 Offset, false, TII, *this, dl); 896 else { 897 emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII, 898 true, dl); 899 UseRR = true; 900 } 901 } else 902 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, 903 *this, dl); 904 MI.setDesc(TII.get(ARM::tLDR)); 905 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 906 if (UseRR) 907 // Use [reg, reg] addrmode. 908 MI.addOperand(MachineOperand::CreateReg(FrameReg, false)); 909 else // tLDR has an extra register operand. 910 MI.addOperand(MachineOperand::CreateReg(0, false)); 911 } else if (Desc.mayStore()) { 912 // FIXME! This is horrific!!! We need register scavenging. 913 // Our temporary workaround has marked r3 unavailable. Of course, r3 is 914 // also a ABI register so it's possible that is is the register that is 915 // being storing here. If that's the case, we do the following: 916 // r12 = r2 917 // Use r2 to materialize sp + offset 918 // str r3, r2 919 // r2 = r12 920 unsigned ValReg = MI.getOperand(0).getReg(); 921 unsigned TmpReg = ARM::R3; 922 bool UseRR = false; 923 if (ValReg == ARM::R3) { 924 BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12) 925 .addReg(ARM::R2, RegState::Kill); 926 TmpReg = ARM::R2; 927 } 928 if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) 929 BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12) 930 .addReg(ARM::R3, RegState::Kill); 931 if (Opcode == ARM::tSpill) { 932 if (FrameReg == ARM::SP) 933 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg, 934 Offset, false, TII, *this, dl); 935 else { 936 emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII, 937 true, dl); 938 UseRR = true; 939 } 940 } else 941 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, 942 *this, dl); 943 MI.setDesc(TII.get(ARM::tSTR)); 944 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); 945 if (UseRR) // Use [reg, reg] addrmode. 946 MI.addOperand(MachineOperand::CreateReg(FrameReg, false)); 947 else // tSTR has an extra register operand. 948 MI.addOperand(MachineOperand::CreateReg(0, false)); 949 950 MachineBasicBlock::iterator NII = next(II); 951 if (ValReg == ARM::R3) 952 BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R2) 953 .addReg(ARM::R12, RegState::Kill); 954 if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) 955 BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R3) 956 .addReg(ARM::R12, RegState::Kill); 957 } else 958 assert(false && "Unexpected opcode!"); 959 } else { 960 // Insert a set of r12 with the full address: r12 = sp + offset 961 // If the offset we have is too large to fit into the instruction, we need 962 // to form it with a series of ADDri's. Do this by taking 8-bit chunks 963 // out of 'Offset'. 964 unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI); 965 if (ScratchReg == 0) 966 // No register is "free". Scavenge a register. 967 ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj); 968 int PIdx = MI.findFirstPredOperandIdx(); 969 ARMCC::CondCodes Pred = (PIdx == -1) 970 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 971 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 972 emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, 973 isSub ? -Offset : Offset, Pred, PredReg, TII, dl); 974 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 975 } 976} 977 978static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) { 979 const MachineFrameInfo *FFI = MF.getFrameInfo(); 980 int Offset = 0; 981 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { 982 int FixedOff = -FFI->getObjectOffset(i); 983 if (FixedOff > Offset) Offset = FixedOff; 984 } 985 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { 986 if (FFI->isDeadObjectIndex(i)) 987 continue; 988 Offset += FFI->getObjectSize(i); 989 unsigned Align = FFI->getObjectAlignment(i); 990 // Adjust to alignment boundary 991 Offset = (Offset+Align-1)/Align*Align; 992 } 993 return (unsigned)Offset; 994} 995 996void 997ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 998 RegScavenger *RS) const { 999 // This tells PEI to spill the FP as if it is any other callee-save register 1000 // to take advantage the eliminateFrameIndex machinery. This also ensures it 1001 // is spilled in the order specified by getCalleeSavedRegs() to make it easier 1002 // to combine multiple loads / stores. 1003 bool CanEliminateFrame = true; 1004 bool CS1Spilled = false; 1005 bool LRSpilled = false; 1006 unsigned NumGPRSpills = 0; 1007 SmallVector<unsigned, 4> UnspilledCS1GPRs; 1008 SmallVector<unsigned, 4> UnspilledCS2GPRs; 1009 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1010 1011 // Don't spill FP if the frame can be eliminated. This is determined 1012 // by scanning the callee-save registers to see if any is used. 1013 const unsigned *CSRegs = getCalleeSavedRegs(); 1014 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 1015 for (unsigned i = 0; CSRegs[i]; ++i) { 1016 unsigned Reg = CSRegs[i]; 1017 bool Spilled = false; 1018 if (MF.getRegInfo().isPhysRegUsed(Reg)) { 1019 AFI->setCSRegisterIsSpilled(Reg); 1020 Spilled = true; 1021 CanEliminateFrame = false; 1022 } else { 1023 // Check alias registers too. 1024 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 1025 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { 1026 Spilled = true; 1027 CanEliminateFrame = false; 1028 } 1029 } 1030 } 1031 1032 if (CSRegClasses[i] == &ARM::GPRRegClass) { 1033 if (Spilled) { 1034 NumGPRSpills++; 1035 1036 if (!STI.isTargetDarwin()) { 1037 if (Reg == ARM::LR) 1038 LRSpilled = true; 1039 CS1Spilled = true; 1040 continue; 1041 } 1042 1043 // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 1044 switch (Reg) { 1045 case ARM::LR: 1046 LRSpilled = true; 1047 // Fallthrough 1048 case ARM::R4: 1049 case ARM::R5: 1050 case ARM::R6: 1051 case ARM::R7: 1052 CS1Spilled = true; 1053 break; 1054 default: 1055 break; 1056 } 1057 } else { 1058 if (!STI.isTargetDarwin()) { 1059 UnspilledCS1GPRs.push_back(Reg); 1060 continue; 1061 } 1062 1063 switch (Reg) { 1064 case ARM::R4: 1065 case ARM::R5: 1066 case ARM::R6: 1067 case ARM::R7: 1068 case ARM::LR: 1069 UnspilledCS1GPRs.push_back(Reg); 1070 break; 1071 default: 1072 UnspilledCS2GPRs.push_back(Reg); 1073 break; 1074 } 1075 } 1076 } 1077 } 1078 1079 bool ForceLRSpill = false; 1080 if (!LRSpilled && AFI->isThumbFunction()) { 1081 unsigned FnSize = TII.GetFunctionSizeInBytes(MF); 1082 // Force LR to be spilled if the Thumb function size is > 2048. This enables 1083 // use of BL to implement far jump. If it turns out that it's not needed 1084 // then the branch fix up path will undo it. 1085 if (FnSize >= (1 << 11)) { 1086 CanEliminateFrame = false; 1087 ForceLRSpill = true; 1088 } 1089 } 1090 1091 bool ExtraCSSpill = false; 1092 if (!CanEliminateFrame || hasFP(MF)) { 1093 AFI->setHasStackFrame(true); 1094 1095 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 1096 // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 1097 if (!LRSpilled && CS1Spilled) { 1098 MF.getRegInfo().setPhysRegUsed(ARM::LR); 1099 AFI->setCSRegisterIsSpilled(ARM::LR); 1100 NumGPRSpills++; 1101 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 1102 UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 1103 ForceLRSpill = false; 1104 ExtraCSSpill = true; 1105 } 1106 1107 // Darwin ABI requires FP to point to the stack slot that contains the 1108 // previous FP. 1109 if (STI.isTargetDarwin() || hasFP(MF)) { 1110 MF.getRegInfo().setPhysRegUsed(FramePtr); 1111 NumGPRSpills++; 1112 } 1113 1114 // If stack and double are 8-byte aligned and we are spilling an odd number 1115 // of GPRs. Spill one extra callee save GPR so we won't have to pad between 1116 // the integer and double callee save areas. 1117 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1118 if (TargetAlign == 8 && (NumGPRSpills & 1)) { 1119 if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 1120 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 1121 unsigned Reg = UnspilledCS1GPRs[i]; 1122 // Don't spiil high register if the function is thumb 1123 if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) { 1124 MF.getRegInfo().setPhysRegUsed(Reg); 1125 AFI->setCSRegisterIsSpilled(Reg); 1126 if (!isReservedReg(MF, Reg)) 1127 ExtraCSSpill = true; 1128 break; 1129 } 1130 } 1131 } else if (!UnspilledCS2GPRs.empty() && 1132 !AFI->isThumbFunction()) { 1133 unsigned Reg = UnspilledCS2GPRs.front(); 1134 MF.getRegInfo().setPhysRegUsed(Reg); 1135 AFI->setCSRegisterIsSpilled(Reg); 1136 if (!isReservedReg(MF, Reg)) 1137 ExtraCSSpill = true; 1138 } 1139 } 1140 1141 // Estimate if we might need to scavenge a register at some point in order 1142 // to materialize a stack offset. If so, either spill one additiona 1143 // callee-saved register or reserve a special spill slot to facilitate 1144 // register scavenging. 1145 if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) { 1146 MachineFrameInfo *MFI = MF.getFrameInfo(); 1147 unsigned Size = estimateStackSize(MF, MFI); 1148 unsigned Limit = (1 << 12) - 1; 1149 for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB) 1150 for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) { 1151 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) 1152 if (I->getOperand(i).isFI()) { 1153 unsigned Opcode = I->getOpcode(); 1154 const TargetInstrDesc &Desc = TII.get(Opcode); 1155 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 1156 if (AddrMode == ARMII::AddrMode3) { 1157 Limit = (1 << 8) - 1; 1158 goto DoneEstimating; 1159 } else if (AddrMode == ARMII::AddrMode5) { 1160 unsigned ThisLimit = ((1 << 8) - 1) * 4; 1161 if (ThisLimit < Limit) 1162 Limit = ThisLimit; 1163 } 1164 } 1165 } 1166 DoneEstimating: 1167 if (Size >= Limit) { 1168 // If any non-reserved CS register isn't spilled, just spill one or two 1169 // extra. That should take care of it! 1170 unsigned NumExtras = TargetAlign / 4; 1171 SmallVector<unsigned, 2> Extras; 1172 while (NumExtras && !UnspilledCS1GPRs.empty()) { 1173 unsigned Reg = UnspilledCS1GPRs.back(); 1174 UnspilledCS1GPRs.pop_back(); 1175 if (!isReservedReg(MF, Reg)) { 1176 Extras.push_back(Reg); 1177 NumExtras--; 1178 } 1179 } 1180 while (NumExtras && !UnspilledCS2GPRs.empty()) { 1181 unsigned Reg = UnspilledCS2GPRs.back(); 1182 UnspilledCS2GPRs.pop_back(); 1183 if (!isReservedReg(MF, Reg)) { 1184 Extras.push_back(Reg); 1185 NumExtras--; 1186 } 1187 } 1188 if (Extras.size() && NumExtras == 0) { 1189 for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 1190 MF.getRegInfo().setPhysRegUsed(Extras[i]); 1191 AFI->setCSRegisterIsSpilled(Extras[i]); 1192 } 1193 } else { 1194 // Reserve a slot closest to SP or frame pointer. 1195 const TargetRegisterClass *RC = &ARM::GPRRegClass; 1196 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1197 RC->getAlignment())); 1198 } 1199 } 1200 } 1201 } 1202 1203 if (ForceLRSpill) { 1204 MF.getRegInfo().setPhysRegUsed(ARM::LR); 1205 AFI->setCSRegisterIsSpilled(ARM::LR); 1206 AFI->setLRIsSpilledForFarJump(true); 1207 } 1208} 1209 1210/// Move iterator pass the next bunch of callee save load / store ops for 1211/// the particular spill area (1: integer area 1, 2: integer area 2, 1212/// 3: fp area, 0: don't care). 1213static void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1214 MachineBasicBlock::iterator &MBBI, 1215 int Opc, unsigned Area, 1216 const ARMSubtarget &STI) { 1217 while (MBBI != MBB.end() && 1218 MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) { 1219 if (Area != 0) { 1220 bool Done = false; 1221 unsigned Category = 0; 1222 switch (MBBI->getOperand(0).getReg()) { 1223 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1224 case ARM::LR: 1225 Category = 1; 1226 break; 1227 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1228 Category = STI.isTargetDarwin() ? 2 : 1; 1229 break; 1230 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 1231 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1232 Category = 3; 1233 break; 1234 default: 1235 Done = true; 1236 break; 1237 } 1238 if (Done || Category != Area) 1239 break; 1240 } 1241 1242 ++MBBI; 1243 } 1244} 1245 1246void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { 1247 MachineBasicBlock &MBB = MF.front(); 1248 MachineBasicBlock::iterator MBBI = MBB.begin(); 1249 MachineFrameInfo *MFI = MF.getFrameInfo(); 1250 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1251 bool isThumb = AFI->isThumbFunction(); 1252 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1253 unsigned NumBytes = MFI->getStackSize(); 1254 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1255 DebugLoc dl = (MBBI != MBB.end() ? 1256 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc()); 1257 1258 if (isThumb) { 1259 // Check if R3 is live in. It might have to be used as a scratch register. 1260 for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(), 1261 E = MF.getRegInfo().livein_end(); I != E; ++I) { 1262 if (I->first == ARM::R3) { 1263 AFI->setR3IsLiveIn(true); 1264 break; 1265 } 1266 } 1267 1268 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 1269 NumBytes = (NumBytes + 3) & ~3; 1270 MFI->setStackSize(NumBytes); 1271 } 1272 1273 // Determine the sizes of each callee-save spill areas and record which frame 1274 // belongs to which callee-save spill areas. 1275 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1276 int FramePtrSpillFI = 0; 1277 1278 if (VARegSaveSize) 1279 emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII, 1280 *this, dl); 1281 1282 if (!AFI->hasStackFrame()) { 1283 if (NumBytes != 0) 1284 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl); 1285 return; 1286 } 1287 1288 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1289 unsigned Reg = CSI[i].getReg(); 1290 int FI = CSI[i].getFrameIdx(); 1291 switch (Reg) { 1292 case ARM::R4: 1293 case ARM::R5: 1294 case ARM::R6: 1295 case ARM::R7: 1296 case ARM::LR: 1297 if (Reg == FramePtr) 1298 FramePtrSpillFI = FI; 1299 AFI->addGPRCalleeSavedArea1Frame(FI); 1300 GPRCS1Size += 4; 1301 break; 1302 case ARM::R8: 1303 case ARM::R9: 1304 case ARM::R10: 1305 case ARM::R11: 1306 if (Reg == FramePtr) 1307 FramePtrSpillFI = FI; 1308 if (STI.isTargetDarwin()) { 1309 AFI->addGPRCalleeSavedArea2Frame(FI); 1310 GPRCS2Size += 4; 1311 } else { 1312 AFI->addGPRCalleeSavedArea1Frame(FI); 1313 GPRCS1Size += 4; 1314 } 1315 break; 1316 default: 1317 AFI->addDPRCalleeSavedAreaFrame(FI); 1318 DPRCSSize += 8; 1319 } 1320 } 1321 1322 if (!isThumb) { 1323 // Build the new SUBri to adjust SP for integer callee-save spill area 1. 1324 emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII, *this, dl); 1325 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI); 1326 } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) { 1327 ++MBBI; 1328 if (MBBI != MBB.end()) 1329 dl = MBBI->getDebugLoc(); 1330 } 1331 1332 // Darwin ABI requires FP to point to the stack slot that contains the 1333 // previous FP. 1334 if (STI.isTargetDarwin() || hasFP(MF)) { 1335 MachineInstrBuilder MIB = 1336 BuildMI(MBB, MBBI, dl, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), 1337 FramePtr) 1338 .addFrameIndex(FramePtrSpillFI).addImm(0); 1339 if (!isThumb) AddDefaultCC(AddDefaultPred(MIB)); 1340 } 1341 1342 if (!isThumb) { 1343 // Build the new SUBri to adjust SP for integer callee-save spill area 2. 1344 emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII, *this, dl); 1345 1346 // Build the new SUBri to adjust SP for FP callee-save spill area. 1347 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI); 1348 emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII, *this, dl); 1349 } 1350 1351 // Determine starting offsets of spill areas. 1352 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1353 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1354 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1355 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1356 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1357 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1358 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1359 1360 NumBytes = DPRCSOffset; 1361 if (NumBytes) { 1362 // Insert it after all the callee-save spills. 1363 if (!isThumb) 1364 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI); 1365 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl); 1366 } 1367 1368 if(STI.isTargetELF() && hasFP(MF)) { 1369 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 1370 AFI->getFramePtrSpillOffset()); 1371 } 1372 1373 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1374 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1375 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1376} 1377 1378static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1379 for (unsigned i = 0; CSRegs[i]; ++i) 1380 if (Reg == CSRegs[i]) 1381 return true; 1382 return false; 1383} 1384 1385static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { 1386 return ((MI->getOpcode() == ARM::FLDD || 1387 MI->getOpcode() == ARM::LDR || 1388 MI->getOpcode() == ARM::tRestore) && 1389 MI->getOperand(1).isFI() && 1390 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 1391} 1392 1393void ARMRegisterInfo::emitEpilogue(MachineFunction &MF, 1394 MachineBasicBlock &MBB) const { 1395 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1396 assert((MBBI->getOpcode() == ARM::BX_RET || 1397 MBBI->getOpcode() == ARM::tBX_RET || 1398 MBBI->getOpcode() == ARM::tPOP_RET) && 1399 "Can only insert epilog into returning blocks"); 1400 DebugLoc dl = MBBI->getDebugLoc(); 1401 MachineFrameInfo *MFI = MF.getFrameInfo(); 1402 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1403 bool isThumb = AFI->isThumbFunction(); 1404 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1405 int NumBytes = (int)MFI->getStackSize(); 1406 1407 if (!AFI->hasStackFrame()) { 1408 if (NumBytes != 0) 1409 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl); 1410 } else { 1411 // Unwind MBBI to point to first LDR / FLDD. 1412 const unsigned *CSRegs = getCalleeSavedRegs(); 1413 if (MBBI != MBB.begin()) { 1414 do 1415 --MBBI; 1416 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 1417 if (!isCSRestore(MBBI, CSRegs)) 1418 ++MBBI; 1419 } 1420 1421 // Move SP to start of FP callee save spill area. 1422 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1423 AFI->getGPRCalleeSavedArea2Size() + 1424 AFI->getDPRCalleeSavedAreaSize()); 1425 if (isThumb) { 1426 if (hasFP(MF)) { 1427 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1428 // Reset SP based on frame pointer only if the stack frame extends beyond 1429 // frame pointer stack slot or target is ELF and the function has FP. 1430 if (NumBytes) 1431 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, 1432 TII, *this, dl); 1433 else 1434 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::SP) 1435 .addReg(FramePtr); 1436 } else { 1437 if (MBBI->getOpcode() == ARM::tBX_RET && 1438 &MBB.front() != MBBI && 1439 prior(MBBI)->getOpcode() == ARM::tPOP) { 1440 MachineBasicBlock::iterator PMBBI = prior(MBBI); 1441 emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, 1442 *this, dl); 1443 } else 1444 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, 1445 *this, dl); 1446 } 1447 } else { 1448 // Darwin ABI requires FP to point to the stack slot that contains the 1449 // previous FP. 1450 if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) { 1451 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1452 // Reset SP based on frame pointer only if the stack frame extends beyond 1453 // frame pointer stack slot or target is ELF and the function has FP. 1454 if (AFI->getGPRCalleeSavedArea2Size() || 1455 AFI->getDPRCalleeSavedAreaSize() || 1456 AFI->getDPRCalleeSavedAreaOffset()|| 1457 hasFP(MF)) { 1458 if (NumBytes) 1459 BuildMI(MBB, MBBI, dl, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) 1460 .addImm(NumBytes) 1461 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1462 else 1463 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr) 1464 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1465 } 1466 } else if (NumBytes) { 1467 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII, *this, dl); 1468 } 1469 1470 // Move SP to start of integer callee save spill area 2. 1471 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); 1472 emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0, 1473 false, TII, *this, dl); 1474 1475 // Move SP to start of integer callee save spill area 1. 1476 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI); 1477 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0, 1478 false, TII, *this, dl); 1479 1480 // Move SP to SP upon entry to the function. 1481 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI); 1482 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0, 1483 false, TII, *this, dl); 1484 } 1485 } 1486 1487 if (VARegSaveSize) { 1488 if (isThumb) 1489 // Epilogue for vararg functions: pop LR to R3 and branch off it. 1490 // FIXME: Verify this is still ok when R3 is no longer being reserved. 1491 BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)).addReg(ARM::R3); 1492 1493 emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII, 1494 *this, dl); 1495 1496 if (isThumb) { 1497 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); 1498 MBB.erase(MBBI); 1499 } 1500 } 1501} 1502 1503unsigned ARMRegisterInfo::getRARegister() const { 1504 return ARM::LR; 1505} 1506 1507unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1508 if (STI.isTargetDarwin() || hasFP(MF)) 1509 return (STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11; 1510 else 1511 return ARM::SP; 1512} 1513 1514unsigned ARMRegisterInfo::getEHExceptionRegister() const { 1515 assert(0 && "What is the exception register"); 1516 return 0; 1517} 1518 1519unsigned ARMRegisterInfo::getEHHandlerRegister() const { 1520 assert(0 && "What is the exception handler register"); 1521 return 0; 1522} 1523 1524int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 1525 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 1526} 1527 1528#include "ARMGenRegisterInfo.inc" 1529