ARMInstrFormats.td revision 280031
1//===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// ARM Instruction Format Definitions. 13// 14 15// Format specifies the encoding used by the instruction. This is part of the 16// ad-hoc solution used to emit machine instruction encodings by our machine 17// code emitter. 18class Format<bits<6> val> { 19 bits<6> Value = val; 20} 21 22def Pseudo : Format<0>; 23def MulFrm : Format<1>; 24def BrFrm : Format<2>; 25def BrMiscFrm : Format<3>; 26 27def DPFrm : Format<4>; 28def DPSoRegRegFrm : Format<5>; 29 30def LdFrm : Format<6>; 31def StFrm : Format<7>; 32def LdMiscFrm : Format<8>; 33def StMiscFrm : Format<9>; 34def LdStMulFrm : Format<10>; 35 36def LdStExFrm : Format<11>; 37 38def ArithMiscFrm : Format<12>; 39def SatFrm : Format<13>; 40def ExtFrm : Format<14>; 41 42def VFPUnaryFrm : Format<15>; 43def VFPBinaryFrm : Format<16>; 44def VFPConv1Frm : Format<17>; 45def VFPConv2Frm : Format<18>; 46def VFPConv3Frm : Format<19>; 47def VFPConv4Frm : Format<20>; 48def VFPConv5Frm : Format<21>; 49def VFPLdStFrm : Format<22>; 50def VFPLdStMulFrm : Format<23>; 51def VFPMiscFrm : Format<24>; 52 53def ThumbFrm : Format<25>; 54def MiscFrm : Format<26>; 55 56def NGetLnFrm : Format<27>; 57def NSetLnFrm : Format<28>; 58def NDupFrm : Format<29>; 59def NLdStFrm : Format<30>; 60def N1RegModImmFrm: Format<31>; 61def N2RegFrm : Format<32>; 62def NVCVTFrm : Format<33>; 63def NVDupLnFrm : Format<34>; 64def N2RegVShLFrm : Format<35>; 65def N2RegVShRFrm : Format<36>; 66def N3RegFrm : Format<37>; 67def N3RegVShFrm : Format<38>; 68def NVExtFrm : Format<39>; 69def NVMulSLFrm : Format<40>; 70def NVTBLFrm : Format<41>; 71def DPSoRegImmFrm : Format<42>; 72 73// Misc flags. 74 75// The instruction has an Rn register operand. 76// UnaryDP - Indicates this is a unary data processing instruction, i.e. 77// it doesn't have a Rn operand. 78class UnaryDP { bit isUnaryDataProc = 1; } 79 80// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 81// a 16-bit Thumb instruction if certain conditions are met. 82class Xform16Bit { bit canXformTo16Bit = 1; } 83 84//===----------------------------------------------------------------------===// 85// ARM Instruction flags. These need to match ARMBaseInstrInfo.h. 86// 87 88// FIXME: Once the JIT is MC-ized, these can go away. 89// Addressing mode. 90class AddrMode<bits<5> val> { 91 bits<5> Value = val; 92} 93def AddrModeNone : AddrMode<0>; 94def AddrMode1 : AddrMode<1>; 95def AddrMode2 : AddrMode<2>; 96def AddrMode3 : AddrMode<3>; 97def AddrMode4 : AddrMode<4>; 98def AddrMode5 : AddrMode<5>; 99def AddrMode6 : AddrMode<6>; 100def AddrModeT1_1 : AddrMode<7>; 101def AddrModeT1_2 : AddrMode<8>; 102def AddrModeT1_4 : AddrMode<9>; 103def AddrModeT1_s : AddrMode<10>; 104def AddrModeT2_i12 : AddrMode<11>; 105def AddrModeT2_i8 : AddrMode<12>; 106def AddrModeT2_so : AddrMode<13>; 107def AddrModeT2_pc : AddrMode<14>; 108def AddrModeT2_i8s4 : AddrMode<15>; 109def AddrMode_i12 : AddrMode<16>; 110 111// Load / store index mode. 112class IndexMode<bits<2> val> { 113 bits<2> Value = val; 114} 115def IndexModeNone : IndexMode<0>; 116def IndexModePre : IndexMode<1>; 117def IndexModePost : IndexMode<2>; 118def IndexModeUpd : IndexMode<3>; 119 120// Instruction execution domain. 121class Domain<bits<3> val> { 122 bits<3> Value = val; 123} 124def GenericDomain : Domain<0>; 125def VFPDomain : Domain<1>; // Instructions in VFP domain only 126def NeonDomain : Domain<2>; // Instructions in Neon domain only 127def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains 128def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8 129 130//===----------------------------------------------------------------------===// 131// ARM special operands. 132// 133 134// ARM imod and iflag operands, used only by the CPS instruction. 135def imod_op : Operand<i32> { 136 let PrintMethod = "printCPSIMod"; 137} 138 139def ProcIFlagsOperand : AsmOperandClass { 140 let Name = "ProcIFlags"; 141 let ParserMethod = "parseProcIFlagsOperand"; 142} 143def iflags_op : Operand<i32> { 144 let PrintMethod = "printCPSIFlag"; 145 let ParserMatchClass = ProcIFlagsOperand; 146} 147 148// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 149// register whose default is 0 (no register). 150def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; } 151def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), 152 (ops (i32 14), (i32 zero_reg))> { 153 let PrintMethod = "printPredicateOperand"; 154 let ParserMatchClass = CondCodeOperand; 155 let DecoderMethod = "DecodePredicateOperand"; 156} 157 158// Selectable predicate operand for CMOV instructions. We can't use a normal 159// predicate because the default values interfere with instruction selection. In 160// all other respects it is identical though: pseudo-instruction expansion 161// relies on the MachineOperands being compatible. 162def cmovpred : Operand<i32>, PredicateOp, 163 ComplexPattern<i32, 2, "SelectCMOVPred"> { 164 let MIOperandInfo = (ops i32imm, i32imm); 165 let PrintMethod = "printPredicateOperand"; 166} 167 168// Conditional code result for instructions whose 's' bit is set, e.g. subs. 169def CCOutOperand : AsmOperandClass { let Name = "CCOut"; } 170def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 171 let EncoderMethod = "getCCOutOpValue"; 172 let PrintMethod = "printSBitModifierOperand"; 173 let ParserMatchClass = CCOutOperand; 174 let DecoderMethod = "DecodeCCOutOperand"; 175} 176 177// Same as cc_out except it defaults to setting CPSR. 178def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 179 let EncoderMethod = "getCCOutOpValue"; 180 let PrintMethod = "printSBitModifierOperand"; 181 let ParserMatchClass = CCOutOperand; 182 let DecoderMethod = "DecodeCCOutOperand"; 183} 184 185// ARM special operands for disassembly only. 186// 187def SetEndAsmOperand : ImmAsmOperand { 188 let Name = "SetEndImm"; 189 let ParserMethod = "parseSetEndImm"; 190} 191def setend_op : Operand<i32> { 192 let PrintMethod = "printSetendOperand"; 193 let ParserMatchClass = SetEndAsmOperand; 194} 195 196def MSRMaskOperand : AsmOperandClass { 197 let Name = "MSRMask"; 198 let ParserMethod = "parseMSRMaskOperand"; 199} 200def msr_mask : Operand<i32> { 201 let PrintMethod = "printMSRMaskOperand"; 202 let DecoderMethod = "DecodeMSRMask"; 203 let ParserMatchClass = MSRMaskOperand; 204} 205 206def BankedRegOperand : AsmOperandClass { 207 let Name = "BankedReg"; 208 let ParserMethod = "parseBankedRegOperand"; 209} 210def banked_reg : Operand<i32> { 211 let PrintMethod = "printBankedRegOperand"; 212 let DecoderMethod = "DecodeBankedReg"; 213 let ParserMatchClass = BankedRegOperand; 214} 215 216// Shift Right Immediate - A shift right immediate is encoded differently from 217// other shift immediates. The imm6 field is encoded like so: 218// 219// Offset Encoding 220// 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0> 221// 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0> 222// 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0> 223// 64 64 - <imm> is encoded in imm6<5:0> 224def shr_imm8_asm_operand : ImmAsmOperand { let Name = "ShrImm8"; } 225def shr_imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 8; }]> { 226 let EncoderMethod = "getShiftRight8Imm"; 227 let DecoderMethod = "DecodeShiftRight8Imm"; 228 let ParserMatchClass = shr_imm8_asm_operand; 229} 230def shr_imm16_asm_operand : ImmAsmOperand { let Name = "ShrImm16"; } 231def shr_imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 16; }]> { 232 let EncoderMethod = "getShiftRight16Imm"; 233 let DecoderMethod = "DecodeShiftRight16Imm"; 234 let ParserMatchClass = shr_imm16_asm_operand; 235} 236def shr_imm32_asm_operand : ImmAsmOperand { let Name = "ShrImm32"; } 237def shr_imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]> { 238 let EncoderMethod = "getShiftRight32Imm"; 239 let DecoderMethod = "DecodeShiftRight32Imm"; 240 let ParserMatchClass = shr_imm32_asm_operand; 241} 242def shr_imm64_asm_operand : ImmAsmOperand { let Name = "ShrImm64"; } 243def shr_imm64 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 64; }]> { 244 let EncoderMethod = "getShiftRight64Imm"; 245 let DecoderMethod = "DecodeShiftRight64Imm"; 246 let ParserMatchClass = shr_imm64_asm_operand; 247} 248 249//===----------------------------------------------------------------------===// 250// ARM Assembler alias templates. 251// 252class ARMInstAlias<string Asm, dag Result, bit Emit = 0b1> 253 : InstAlias<Asm, Result, Emit>, Requires<[IsARM]>; 254class tInstAlias<string Asm, dag Result, bit Emit = 0b1> 255 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb]>; 256class t2InstAlias<string Asm, dag Result, bit Emit = 0b1> 257 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb2]>; 258class VFP2InstAlias<string Asm, dag Result, bit Emit = 0b1> 259 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP2]>; 260class VFP2DPInstAlias<string Asm, dag Result, bit Emit = 0b1> 261 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP2,HasDPVFP]>; 262class VFP3InstAlias<string Asm, dag Result, bit Emit = 0b1> 263 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP3]>; 264class NEONInstAlias<string Asm, dag Result, bit Emit = 0b1> 265 : InstAlias<Asm, Result, Emit>, Requires<[HasNEON]>; 266 267 268class VFP2MnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>, 269 Requires<[HasVFP2]>; 270class NEONMnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>, 271 Requires<[HasNEON]>; 272 273//===----------------------------------------------------------------------===// 274// ARM Instruction templates. 275// 276 277 278class InstTemplate<AddrMode am, int sz, IndexMode im, 279 Format f, Domain d, string cstr, InstrItinClass itin> 280 : Instruction { 281 let Namespace = "ARM"; 282 283 AddrMode AM = am; 284 int Size = sz; 285 IndexMode IM = im; 286 bits<2> IndexModeBits = IM.Value; 287 Format F = f; 288 bits<6> Form = F.Value; 289 Domain D = d; 290 bit isUnaryDataProc = 0; 291 bit canXformTo16Bit = 0; 292 // The instruction is a 16-bit flag setting Thumb instruction. Used 293 // by the parser to determine whether to require the 'S' suffix on the 294 // mnemonic (when not in an IT block) or preclude it (when in an IT block). 295 bit thumbArithFlagSetting = 0; 296 297 // If this is a pseudo instruction, mark it isCodeGenOnly. 298 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo"); 299 300 // The layout of TSFlags should be kept in sync with ARMBaseInfo.h. 301 let TSFlags{4-0} = AM.Value; 302 let TSFlags{6-5} = IndexModeBits; 303 let TSFlags{12-7} = Form; 304 let TSFlags{13} = isUnaryDataProc; 305 let TSFlags{14} = canXformTo16Bit; 306 let TSFlags{17-15} = D.Value; 307 let TSFlags{18} = thumbArithFlagSetting; 308 309 let Constraints = cstr; 310 let Itinerary = itin; 311} 312 313class Encoding { 314 field bits<32> Inst; 315 // Mask of bits that cause an encoding to be UNPREDICTABLE. 316 // If a bit is set, then if the corresponding bit in the 317 // target encoding differs from its value in the "Inst" field, 318 // the instruction is UNPREDICTABLE (SoftFail in abstract parlance). 319 field bits<32> Unpredictable = 0; 320 // SoftFail is the generic name for this field, but we alias it so 321 // as to make it more obvious what it means in ARM-land. 322 field bits<32> SoftFail = Unpredictable; 323} 324 325class InstARM<AddrMode am, int sz, IndexMode im, 326 Format f, Domain d, string cstr, InstrItinClass itin> 327 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding { 328 let DecoderNamespace = "ARM"; 329} 330 331// This Encoding-less class is used by Thumb1 to specify the encoding bits later 332// on by adding flavors to specific instructions. 333class InstThumb<AddrMode am, int sz, IndexMode im, 334 Format f, Domain d, string cstr, InstrItinClass itin> 335 : InstTemplate<am, sz, im, f, d, cstr, itin> { 336 let DecoderNamespace = "Thumb"; 337} 338 339// Pseudo-instructions for alternate assembly syntax (never used by codegen). 340// These are aliases that require C++ handling to convert to the target 341// instruction, while InstAliases can be handled directly by tblgen. 342class AsmPseudoInst<string asm, dag iops, dag oops = (outs)> 343 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 344 "", NoItinerary> { 345 let OutOperandList = oops; 346 let InOperandList = iops; 347 let Pattern = []; 348 let isCodeGenOnly = 0; // So we get asm matcher for it. 349 let AsmString = asm; 350 let isPseudo = 1; 351} 352 353class ARMAsmPseudo<string asm, dag iops, dag oops = (outs)> 354 : AsmPseudoInst<asm, iops, oops>, Requires<[IsARM]>; 355class tAsmPseudo<string asm, dag iops, dag oops = (outs)> 356 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb]>; 357class t2AsmPseudo<string asm, dag iops, dag oops = (outs)> 358 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb2]>; 359class VFP2AsmPseudo<string asm, dag iops, dag oops = (outs)> 360 : AsmPseudoInst<asm, iops, oops>, Requires<[HasVFP2]>; 361class NEONAsmPseudo<string asm, dag iops, dag oops = (outs)> 362 : AsmPseudoInst<asm, iops, oops>, Requires<[HasNEON]>; 363 364// Pseudo instructions for the code generator. 365class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern> 366 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, 367 GenericDomain, "", itin> { 368 let OutOperandList = oops; 369 let InOperandList = iops; 370 let Pattern = pattern; 371 let isCodeGenOnly = 1; 372 let isPseudo = 1; 373} 374 375// PseudoInst that's ARM-mode only. 376class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 377 list<dag> pattern> 378 : PseudoInst<oops, iops, itin, pattern> { 379 let Size = sz; 380 list<Predicate> Predicates = [IsARM]; 381} 382 383// PseudoInst that's Thumb-mode only. 384class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 385 list<dag> pattern> 386 : PseudoInst<oops, iops, itin, pattern> { 387 let Size = sz; 388 list<Predicate> Predicates = [IsThumb]; 389} 390 391// PseudoInst that's Thumb2-mode only. 392class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 393 list<dag> pattern> 394 : PseudoInst<oops, iops, itin, pattern> { 395 let Size = sz; 396 list<Predicate> Predicates = [IsThumb2]; 397} 398 399class ARMPseudoExpand<dag oops, dag iops, int sz, 400 InstrItinClass itin, list<dag> pattern, 401 dag Result> 402 : ARMPseudoInst<oops, iops, sz, itin, pattern>, 403 PseudoInstExpansion<Result>; 404 405class tPseudoExpand<dag oops, dag iops, int sz, 406 InstrItinClass itin, list<dag> pattern, 407 dag Result> 408 : tPseudoInst<oops, iops, sz, itin, pattern>, 409 PseudoInstExpansion<Result>; 410 411class t2PseudoExpand<dag oops, dag iops, int sz, 412 InstrItinClass itin, list<dag> pattern, 413 dag Result> 414 : t2PseudoInst<oops, iops, sz, itin, pattern>, 415 PseudoInstExpansion<Result>; 416 417// Almost all ARM instructions are predicable. 418class I<dag oops, dag iops, AddrMode am, int sz, 419 IndexMode im, Format f, InstrItinClass itin, 420 string opc, string asm, string cstr, 421 list<dag> pattern> 422 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 423 bits<4> p; 424 let Inst{31-28} = p; 425 let OutOperandList = oops; 426 let InOperandList = !con(iops, (ins pred:$p)); 427 let AsmString = !strconcat(opc, "${p}", asm); 428 let Pattern = pattern; 429 list<Predicate> Predicates = [IsARM]; 430} 431 432// A few are not predicable 433class InoP<dag oops, dag iops, AddrMode am, int sz, 434 IndexMode im, Format f, InstrItinClass itin, 435 string opc, string asm, string cstr, 436 list<dag> pattern> 437 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 438 let OutOperandList = oops; 439 let InOperandList = iops; 440 let AsmString = !strconcat(opc, asm); 441 let Pattern = pattern; 442 let isPredicable = 0; 443 list<Predicate> Predicates = [IsARM]; 444} 445 446// Same as I except it can optionally modify CPSR. Note it's modeled as an input 447// operand since by default it's a zero register. It will become an implicit def 448// once it's "flipped". 449class sI<dag oops, dag iops, AddrMode am, int sz, 450 IndexMode im, Format f, InstrItinClass itin, 451 string opc, string asm, string cstr, 452 list<dag> pattern> 453 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 454 bits<4> p; // Predicate operand 455 bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 456 let Inst{31-28} = p; 457 let Inst{20} = s; 458 459 let OutOperandList = oops; 460 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 461 let AsmString = !strconcat(opc, "${s}${p}", asm); 462 let Pattern = pattern; 463 list<Predicate> Predicates = [IsARM]; 464} 465 466// Special cases 467class XI<dag oops, dag iops, AddrMode am, int sz, 468 IndexMode im, Format f, InstrItinClass itin, 469 string asm, string cstr, list<dag> pattern> 470 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 471 let OutOperandList = oops; 472 let InOperandList = iops; 473 let AsmString = asm; 474 let Pattern = pattern; 475 list<Predicate> Predicates = [IsARM]; 476} 477 478class AI<dag oops, dag iops, Format f, InstrItinClass itin, 479 string opc, string asm, list<dag> pattern> 480 : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 481 opc, asm, "", pattern>; 482class AsI<dag oops, dag iops, Format f, InstrItinClass itin, 483 string opc, string asm, list<dag> pattern> 484 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 485 opc, asm, "", pattern>; 486class AXI<dag oops, dag iops, Format f, InstrItinClass itin, 487 string asm, list<dag> pattern> 488 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 489 asm, "", pattern>; 490class AXIM<dag oops, dag iops, AddrMode am, Format f, InstrItinClass itin, 491 string asm, list<dag> pattern> 492 : XI<oops, iops, am, 4, IndexModeNone, f, itin, 493 asm, "", pattern>; 494class AInoP<dag oops, dag iops, Format f, InstrItinClass itin, 495 string opc, string asm, list<dag> pattern> 496 : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 497 opc, asm, "", pattern>; 498 499// Ctrl flow instructions 500class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 501 string opc, string asm, list<dag> pattern> 502 : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin, 503 opc, asm, "", pattern> { 504 let Inst{27-24} = opcod; 505} 506class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 507 string asm, list<dag> pattern> 508 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin, 509 asm, "", pattern> { 510 let Inst{27-24} = opcod; 511} 512 513// BR_JT instructions 514class JTI<dag oops, dag iops, InstrItinClass itin, 515 string asm, list<dag> pattern> 516 : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin, 517 asm, "", pattern>; 518 519class AIldr_ex_or_acq<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin, 520 string opc, string asm, list<dag> pattern> 521 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin, 522 opc, asm, "", pattern> { 523 bits<4> Rt; 524 bits<4> addr; 525 let Inst{27-23} = 0b00011; 526 let Inst{22-21} = opcod; 527 let Inst{20} = 1; 528 let Inst{19-16} = addr; 529 let Inst{15-12} = Rt; 530 let Inst{11-10} = 0b11; 531 let Inst{9-8} = opcod2; 532 let Inst{7-0} = 0b10011111; 533} 534class AIstr_ex_or_rel<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin, 535 string opc, string asm, list<dag> pattern> 536 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin, 537 opc, asm, "", pattern> { 538 bits<4> Rt; 539 bits<4> addr; 540 let Inst{27-23} = 0b00011; 541 let Inst{22-21} = opcod; 542 let Inst{20} = 0; 543 let Inst{19-16} = addr; 544 let Inst{11-10} = 0b11; 545 let Inst{9-8} = opcod2; 546 let Inst{7-4} = 0b1001; 547 let Inst{3-0} = Rt; 548} 549// Atomic load/store instructions 550class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 551 string opc, string asm, list<dag> pattern> 552 : AIldr_ex_or_acq<opcod, 0b11, oops, iops, itin, opc, asm, pattern>; 553 554class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 555 string opc, string asm, list<dag> pattern> 556 : AIstr_ex_or_rel<opcod, 0b11, oops, iops, itin, opc, asm, pattern> { 557 bits<4> Rd; 558 let Inst{15-12} = Rd; 559} 560 561// Exclusive load/store instructions 562 563class AIldaex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 564 string opc, string asm, list<dag> pattern> 565 : AIldr_ex_or_acq<opcod, 0b10, oops, iops, itin, opc, asm, pattern>, 566 Requires<[IsARM, HasV8]>; 567 568class AIstlex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 569 string opc, string asm, list<dag> pattern> 570 : AIstr_ex_or_rel<opcod, 0b10, oops, iops, itin, opc, asm, pattern>, 571 Requires<[IsARM, HasV8]> { 572 bits<4> Rd; 573 let Inst{15-12} = Rd; 574} 575 576class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern> 577 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> { 578 bits<4> Rt; 579 bits<4> Rt2; 580 bits<4> addr; 581 let Inst{27-23} = 0b00010; 582 let Inst{22} = b; 583 let Inst{21-20} = 0b00; 584 let Inst{19-16} = addr; 585 let Inst{15-12} = Rt; 586 let Inst{11-4} = 0b00001001; 587 let Inst{3-0} = Rt2; 588 589 let Unpredictable{11-8} = 0b1111; 590 let DecoderMethod = "DecodeSwap"; 591} 592// Acquire/Release load/store instructions 593class AIldracq<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 594 string opc, string asm, list<dag> pattern> 595 : AIldr_ex_or_acq<opcod, 0b00, oops, iops, itin, opc, asm, pattern>, 596 Requires<[IsARM, HasV8]>; 597 598class AIstrrel<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 599 string opc, string asm, list<dag> pattern> 600 : AIstr_ex_or_rel<opcod, 0b00, oops, iops, itin, opc, asm, pattern>, 601 Requires<[IsARM, HasV8]> { 602 let Inst{15-12} = 0b1111; 603} 604 605// addrmode1 instructions 606class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 607 string opc, string asm, list<dag> pattern> 608 : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 609 opc, asm, "", pattern> { 610 let Inst{24-21} = opcod; 611 let Inst{27-26} = 0b00; 612} 613class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 614 string opc, string asm, list<dag> pattern> 615 : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 616 opc, asm, "", pattern> { 617 let Inst{24-21} = opcod; 618 let Inst{27-26} = 0b00; 619} 620class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 621 string asm, list<dag> pattern> 622 : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 623 asm, "", pattern> { 624 let Inst{24-21} = opcod; 625 let Inst{27-26} = 0b00; 626} 627 628// loads 629 630// LDR/LDRB/STR/STRB/... 631class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am, 632 Format f, InstrItinClass itin, string opc, string asm, 633 list<dag> pattern> 634 : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm, 635 "", pattern> { 636 let Inst{27-25} = op; 637 let Inst{24} = 1; // 24 == P 638 // 23 == U 639 let Inst{22} = isByte; 640 let Inst{21} = 0; // 21 == W 641 let Inst{20} = isLd; 642} 643// Indexed load/stores 644class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops, 645 IndexMode im, Format f, InstrItinClass itin, string opc, 646 string asm, string cstr, list<dag> pattern> 647 : I<oops, iops, AddrMode2, 4, im, f, itin, 648 opc, asm, cstr, pattern> { 649 bits<4> Rt; 650 let Inst{27-26} = 0b01; 651 let Inst{24} = isPre; // P bit 652 let Inst{22} = isByte; // B bit 653 let Inst{21} = isPre; // W bit 654 let Inst{20} = isLd; // L bit 655 let Inst{15-12} = Rt; 656} 657class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops, 658 IndexMode im, Format f, InstrItinClass itin, string opc, 659 string asm, string cstr, list<dag> pattern> 660 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 661 pattern> { 662 // AM2 store w/ two operands: (GPR, am2offset) 663 // {12} isAdd 664 // {11-0} imm12/Rm 665 bits<14> offset; 666 bits<4> Rn; 667 let Inst{25} = 1; 668 let Inst{23} = offset{12}; 669 let Inst{19-16} = Rn; 670 let Inst{11-5} = offset{11-5}; 671 let Inst{4} = 0; 672 let Inst{3-0} = offset{3-0}; 673} 674 675class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops, 676 IndexMode im, Format f, InstrItinClass itin, string opc, 677 string asm, string cstr, list<dag> pattern> 678 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 679 pattern> { 680 // AM2 store w/ two operands: (GPR, am2offset) 681 // {12} isAdd 682 // {11-0} imm12/Rm 683 bits<14> offset; 684 bits<4> Rn; 685 let Inst{25} = 0; 686 let Inst{23} = offset{12}; 687 let Inst{19-16} = Rn; 688 let Inst{11-0} = offset{11-0}; 689} 690 691 692// FIXME: Merge with the above class when addrmode2 gets used for STR, STRB 693// but for now use this class for STRT and STRBT. 694class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops, 695 IndexMode im, Format f, InstrItinClass itin, string opc, 696 string asm, string cstr, list<dag> pattern> 697 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 698 pattern> { 699 // AM2 store w/ two operands: (GPR, am2offset) 700 // {17-14} Rn 701 // {13} 1 == Rm, 0 == imm12 702 // {12} isAdd 703 // {11-0} imm12/Rm 704 bits<18> addr; 705 let Inst{25} = addr{13}; 706 let Inst{23} = addr{12}; 707 let Inst{19-16} = addr{17-14}; 708 let Inst{11-0} = addr{11-0}; 709} 710 711// addrmode3 instructions 712class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f, 713 InstrItinClass itin, string opc, string asm, list<dag> pattern> 714 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin, 715 opc, asm, "", pattern> { 716 bits<14> addr; 717 bits<4> Rt; 718 let Inst{27-25} = 0b000; 719 let Inst{24} = 1; // P bit 720 let Inst{23} = addr{8}; // U bit 721 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 722 let Inst{21} = 0; // W bit 723 let Inst{20} = op20; // L bit 724 let Inst{19-16} = addr{12-9}; // Rn 725 let Inst{15-12} = Rt; // Rt 726 let Inst{11-8} = addr{7-4}; // imm7_4/zero 727 let Inst{7-4} = op; 728 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 729 730 let DecoderMethod = "DecodeAddrMode3Instruction"; 731} 732 733class AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops, 734 IndexMode im, Format f, InstrItinClass itin, string opc, 735 string asm, string cstr, list<dag> pattern> 736 : I<oops, iops, AddrMode3, 4, im, f, itin, 737 opc, asm, cstr, pattern> { 738 bits<4> Rt; 739 let Inst{27-25} = 0b000; 740 let Inst{24} = isPre; // P bit 741 let Inst{21} = isPre; // W bit 742 let Inst{20} = op20; // L bit 743 let Inst{15-12} = Rt; // Rt 744 let Inst{7-4} = op; 745} 746 747// FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB 748// but for now use this class for LDRSBT, LDRHT, LDSHT. 749class AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops, 750 IndexMode im, Format f, InstrItinClass itin, string opc, 751 string asm, string cstr, list<dag> pattern> 752 : I<oops, iops, AddrMode3, 4, im, f, itin, opc, asm, cstr, pattern> { 753 // {13} 1 == imm8, 0 == Rm 754 // {12-9} Rn 755 // {8} isAdd 756 // {7-4} imm7_4/zero 757 // {3-0} imm3_0/Rm 758 bits<4> addr; 759 bits<4> Rt; 760 let Inst{27-25} = 0b000; 761 let Inst{24} = 0; // P bit 762 let Inst{21} = 1; 763 let Inst{20} = isLoad; // L bit 764 let Inst{19-16} = addr; // Rn 765 let Inst{15-12} = Rt; // Rt 766 let Inst{7-4} = op; 767} 768 769// stores 770class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin, 771 string opc, string asm, list<dag> pattern> 772 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin, 773 opc, asm, "", pattern> { 774 bits<14> addr; 775 bits<4> Rt; 776 let Inst{27-25} = 0b000; 777 let Inst{24} = 1; // P bit 778 let Inst{23} = addr{8}; // U bit 779 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 780 let Inst{21} = 0; // W bit 781 let Inst{20} = 0; // L bit 782 let Inst{19-16} = addr{12-9}; // Rn 783 let Inst{15-12} = Rt; // Rt 784 let Inst{11-8} = addr{7-4}; // imm7_4/zero 785 let Inst{7-4} = op; 786 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 787 let DecoderMethod = "DecodeAddrMode3Instruction"; 788} 789 790// addrmode4 instructions 791class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, 792 string asm, string cstr, list<dag> pattern> 793 : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> { 794 bits<4> p; 795 bits<16> regs; 796 bits<4> Rn; 797 let Inst{31-28} = p; 798 let Inst{27-25} = 0b100; 799 let Inst{22} = 0; // S bit 800 let Inst{19-16} = Rn; 801 let Inst{15-0} = regs; 802} 803 804// Unsigned multiply, multiply-accumulate instructions. 805class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 806 string opc, string asm, list<dag> pattern> 807 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 808 opc, asm, "", pattern> { 809 let Inst{7-4} = 0b1001; 810 let Inst{20} = 0; // S bit 811 let Inst{27-21} = opcod; 812} 813class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 814 string opc, string asm, list<dag> pattern> 815 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 816 opc, asm, "", pattern> { 817 let Inst{7-4} = 0b1001; 818 let Inst{27-21} = opcod; 819} 820 821// Most significant word multiply 822class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 823 InstrItinClass itin, string opc, string asm, list<dag> pattern> 824 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 825 opc, asm, "", pattern> { 826 bits<4> Rd; 827 bits<4> Rn; 828 bits<4> Rm; 829 let Inst{7-4} = opc7_4; 830 let Inst{20} = 1; 831 let Inst{27-21} = opcod; 832 let Inst{19-16} = Rd; 833 let Inst{11-8} = Rm; 834 let Inst{3-0} = Rn; 835} 836// MSW multiple w/ Ra operand 837class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 838 InstrItinClass itin, string opc, string asm, list<dag> pattern> 839 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> { 840 bits<4> Ra; 841 let Inst{15-12} = Ra; 842} 843 844// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 845class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 846 InstrItinClass itin, string opc, string asm, list<dag> pattern> 847 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 848 opc, asm, "", pattern> { 849 bits<4> Rn; 850 bits<4> Rm; 851 let Inst{4} = 0; 852 let Inst{7} = 1; 853 let Inst{20} = 0; 854 let Inst{27-21} = opcod; 855 let Inst{6-5} = bit6_5; 856 let Inst{11-8} = Rm; 857 let Inst{3-0} = Rn; 858} 859class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 860 InstrItinClass itin, string opc, string asm, list<dag> pattern> 861 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 862 bits<4> Rd; 863 let Inst{19-16} = Rd; 864} 865 866// AMulxyI with Ra operand 867class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 868 InstrItinClass itin, string opc, string asm, list<dag> pattern> 869 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 870 bits<4> Ra; 871 let Inst{15-12} = Ra; 872} 873// SMLAL* 874class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 875 InstrItinClass itin, string opc, string asm, list<dag> pattern> 876 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 877 bits<4> RdLo; 878 bits<4> RdHi; 879 let Inst{19-16} = RdHi; 880 let Inst{15-12} = RdLo; 881} 882 883// Extend instructions. 884class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 885 string opc, string asm, list<dag> pattern> 886 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin, 887 opc, asm, "", pattern> { 888 // All AExtI instructions have Rd and Rm register operands. 889 bits<4> Rd; 890 bits<4> Rm; 891 let Inst{15-12} = Rd; 892 let Inst{3-0} = Rm; 893 let Inst{7-4} = 0b0111; 894 let Inst{9-8} = 0b00; 895 let Inst{27-20} = opcod; 896 897 let Unpredictable{9-8} = 0b11; 898} 899 900// Misc Arithmetic instructions. 901class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops, 902 InstrItinClass itin, string opc, string asm, list<dag> pattern> 903 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, 904 opc, asm, "", pattern> { 905 bits<4> Rd; 906 bits<4> Rm; 907 let Inst{27-20} = opcod; 908 let Inst{19-16} = 0b1111; 909 let Inst{15-12} = Rd; 910 let Inst{11-8} = 0b1111; 911 let Inst{7-4} = opc7_4; 912 let Inst{3-0} = Rm; 913} 914 915// Division instructions. 916class ADivA1I<bits<3> opcod, dag oops, dag iops, 917 InstrItinClass itin, string opc, string asm, list<dag> pattern> 918 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, 919 opc, asm, "", pattern> { 920 bits<4> Rd; 921 bits<4> Rn; 922 bits<4> Rm; 923 let Inst{27-23} = 0b01110; 924 let Inst{22-20} = opcod; 925 let Inst{19-16} = Rd; 926 let Inst{15-12} = 0b1111; 927 let Inst{11-8} = Rm; 928 let Inst{7-4} = 0b0001; 929 let Inst{3-0} = Rn; 930} 931 932// PKH instructions 933def PKHLSLAsmOperand : ImmAsmOperand { 934 let Name = "PKHLSLImm"; 935 let ParserMethod = "parsePKHLSLImm"; 936} 937def pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{ 938 let PrintMethod = "printPKHLSLShiftImm"; 939 let ParserMatchClass = PKHLSLAsmOperand; 940} 941def PKHASRAsmOperand : AsmOperandClass { 942 let Name = "PKHASRImm"; 943 let ParserMethod = "parsePKHASRImm"; 944} 945def pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{ 946 let PrintMethod = "printPKHASRShiftImm"; 947 let ParserMatchClass = PKHASRAsmOperand; 948} 949 950class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin, 951 string opc, string asm, list<dag> pattern> 952 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, 953 opc, asm, "", pattern> { 954 bits<4> Rd; 955 bits<4> Rn; 956 bits<4> Rm; 957 bits<5> sh; 958 let Inst{27-20} = opcod; 959 let Inst{19-16} = Rn; 960 let Inst{15-12} = Rd; 961 let Inst{11-7} = sh; 962 let Inst{6} = tb; 963 let Inst{5-4} = 0b01; 964 let Inst{3-0} = Rm; 965} 966 967//===----------------------------------------------------------------------===// 968 969// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 970class ARMPat<dag pattern, dag result> : Pat<pattern, result> { 971 list<Predicate> Predicates = [IsARM]; 972} 973class ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> { 974 list<Predicate> Predicates = [IsARM, HasV5T]; 975} 976class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 977 list<Predicate> Predicates = [IsARM, HasV5TE]; 978} 979// ARMV5MOPat - Same as ARMV5TEPat with UseMulOps. 980class ARMV5MOPat<dag pattern, dag result> : Pat<pattern, result> { 981 list<Predicate> Predicates = [IsARM, HasV5TE, UseMulOps]; 982} 983class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 984 list<Predicate> Predicates = [IsARM, HasV6]; 985} 986 987//===----------------------------------------------------------------------===// 988// Thumb Instruction Format Definitions. 989// 990 991class ThumbI<dag oops, dag iops, AddrMode am, int sz, 992 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 993 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 994 let OutOperandList = oops; 995 let InOperandList = iops; 996 let AsmString = asm; 997 let Pattern = pattern; 998 list<Predicate> Predicates = [IsThumb]; 999} 1000 1001// TI - Thumb instruction. 1002class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 1003 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>; 1004 1005// Two-address instructions 1006class TIt<dag oops, dag iops, InstrItinClass itin, string asm, 1007 list<dag> pattern> 1008 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst", 1009 pattern>; 1010 1011// tBL, tBX 32-bit instructions 1012class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, 1013 dag oops, dag iops, InstrItinClass itin, string asm, 1014 list<dag> pattern> 1015 : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>, 1016 Encoding { 1017 let Inst{31-27} = opcod1; 1018 let Inst{15-14} = opcod2; 1019 let Inst{12} = opcod3; 1020} 1021 1022// BR_JT instructions 1023class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, 1024 list<dag> pattern> 1025 : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>; 1026 1027// Thumb1 only 1028class Thumb1I<dag oops, dag iops, AddrMode am, int sz, 1029 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 1030 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1031 let OutOperandList = oops; 1032 let InOperandList = iops; 1033 let AsmString = asm; 1034 let Pattern = pattern; 1035 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1036} 1037 1038class T1I<dag oops, dag iops, InstrItinClass itin, 1039 string asm, list<dag> pattern> 1040 : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>; 1041class T1Ix2<dag oops, dag iops, InstrItinClass itin, 1042 string asm, list<dag> pattern> 1043 : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>; 1044 1045// Two-address instructions 1046class T1It<dag oops, dag iops, InstrItinClass itin, 1047 string asm, string cstr, list<dag> pattern> 1048 : Thumb1I<oops, iops, AddrModeNone, 2, itin, 1049 asm, cstr, pattern>; 1050 1051// Thumb1 instruction that can either be predicated or set CPSR. 1052class Thumb1sI<dag oops, dag iops, AddrMode am, int sz, 1053 InstrItinClass itin, 1054 string opc, string asm, string cstr, list<dag> pattern> 1055 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1056 let OutOperandList = !con(oops, (outs s_cc_out:$s)); 1057 let InOperandList = !con(iops, (ins pred:$p)); 1058 let AsmString = !strconcat(opc, "${s}${p}", asm); 1059 let Pattern = pattern; 1060 let thumbArithFlagSetting = 1; 1061 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1062 let DecoderNamespace = "ThumbSBit"; 1063} 1064 1065class T1sI<dag oops, dag iops, InstrItinClass itin, 1066 string opc, string asm, list<dag> pattern> 1067 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>; 1068 1069// Two-address instructions 1070class T1sIt<dag oops, dag iops, InstrItinClass itin, 1071 string opc, string asm, list<dag> pattern> 1072 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, 1073 "$Rn = $Rdn", pattern>; 1074 1075// Thumb1 instruction that can be predicated. 1076class Thumb1pI<dag oops, dag iops, AddrMode am, int sz, 1077 InstrItinClass itin, 1078 string opc, string asm, string cstr, list<dag> pattern> 1079 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1080 let OutOperandList = oops; 1081 let InOperandList = !con(iops, (ins pred:$p)); 1082 let AsmString = !strconcat(opc, "${p}", asm); 1083 let Pattern = pattern; 1084 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1085} 1086 1087class T1pI<dag oops, dag iops, InstrItinClass itin, 1088 string opc, string asm, list<dag> pattern> 1089 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>; 1090 1091// Two-address instructions 1092class T1pIt<dag oops, dag iops, InstrItinClass itin, 1093 string opc, string asm, list<dag> pattern> 1094 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, 1095 "$Rn = $Rdn", pattern>; 1096 1097class T1pIs<dag oops, dag iops, 1098 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1099 : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>; 1100 1101class Encoding16 : Encoding { 1102 let Inst{31-16} = 0x0000; 1103} 1104 1105// A6.2 16-bit Thumb instruction encoding 1106class T1Encoding<bits<6> opcode> : Encoding16 { 1107 let Inst{15-10} = opcode; 1108} 1109 1110// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. 1111class T1General<bits<5> opcode> : Encoding16 { 1112 let Inst{15-14} = 0b00; 1113 let Inst{13-9} = opcode; 1114} 1115 1116// A6.2.2 Data-processing encoding. 1117class T1DataProcessing<bits<4> opcode> : Encoding16 { 1118 let Inst{15-10} = 0b010000; 1119 let Inst{9-6} = opcode; 1120} 1121 1122// A6.2.3 Special data instructions and branch and exchange encoding. 1123class T1Special<bits<4> opcode> : Encoding16 { 1124 let Inst{15-10} = 0b010001; 1125 let Inst{9-6} = opcode; 1126} 1127 1128// A6.2.4 Load/store single data item encoding. 1129class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { 1130 let Inst{15-12} = opA; 1131 let Inst{11-9} = opB; 1132} 1133class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative 1134 1135class T1BranchCond<bits<4> opcode> : Encoding16 { 1136 let Inst{15-12} = opcode; 1137} 1138 1139// Helper classes to encode Thumb1 loads and stores. For immediates, the 1140// following bits are used for "opA" (see A6.2.4): 1141// 1142// 0b0110 => Immediate, 4 bytes 1143// 0b1000 => Immediate, 2 bytes 1144// 0b0111 => Immediate, 1 byte 1145class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am, 1146 InstrItinClass itin, string opc, string asm, 1147 list<dag> pattern> 1148 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>, 1149 T1LoadStore<0b0101, opcode> { 1150 bits<3> Rt; 1151 bits<8> addr; 1152 let Inst{8-6} = addr{5-3}; // Rm 1153 let Inst{5-3} = addr{2-0}; // Rn 1154 let Inst{2-0} = Rt; 1155} 1156class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am, 1157 InstrItinClass itin, string opc, string asm, 1158 list<dag> pattern> 1159 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>, 1160 T1LoadStore<opA, {opB,?,?}> { 1161 bits<3> Rt; 1162 bits<8> addr; 1163 let Inst{10-6} = addr{7-3}; // imm5 1164 let Inst{5-3} = addr{2-0}; // Rn 1165 let Inst{2-0} = Rt; 1166} 1167 1168// A6.2.5 Miscellaneous 16-bit instructions encoding. 1169class T1Misc<bits<7> opcode> : Encoding16 { 1170 let Inst{15-12} = 0b1011; 1171 let Inst{11-5} = opcode; 1172} 1173 1174// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 1175class Thumb2I<dag oops, dag iops, AddrMode am, int sz, 1176 InstrItinClass itin, 1177 string opc, string asm, string cstr, list<dag> pattern> 1178 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1179 let OutOperandList = oops; 1180 let InOperandList = !con(iops, (ins pred:$p)); 1181 let AsmString = !strconcat(opc, "${p}", asm); 1182 let Pattern = pattern; 1183 list<Predicate> Predicates = [IsThumb2]; 1184 let DecoderNamespace = "Thumb2"; 1185} 1186 1187// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an 1188// input operand since by default it's a zero register. It will become an 1189// implicit def once it's "flipped". 1190// 1191// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 1192// more consistent. 1193class Thumb2sI<dag oops, dag iops, AddrMode am, int sz, 1194 InstrItinClass itin, 1195 string opc, string asm, string cstr, list<dag> pattern> 1196 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1197 bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 1198 let Inst{20} = s; 1199 1200 let OutOperandList = oops; 1201 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 1202 let AsmString = !strconcat(opc, "${s}${p}", asm); 1203 let Pattern = pattern; 1204 list<Predicate> Predicates = [IsThumb2]; 1205 let DecoderNamespace = "Thumb2"; 1206} 1207 1208// Special cases 1209class Thumb2XI<dag oops, dag iops, AddrMode am, int sz, 1210 InstrItinClass itin, 1211 string asm, string cstr, list<dag> pattern> 1212 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1213 let OutOperandList = oops; 1214 let InOperandList = iops; 1215 let AsmString = asm; 1216 let Pattern = pattern; 1217 list<Predicate> Predicates = [IsThumb2]; 1218 let DecoderNamespace = "Thumb2"; 1219} 1220 1221class ThumbXI<dag oops, dag iops, AddrMode am, int sz, 1222 InstrItinClass itin, 1223 string asm, string cstr, list<dag> pattern> 1224 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1225 let OutOperandList = oops; 1226 let InOperandList = iops; 1227 let AsmString = asm; 1228 let Pattern = pattern; 1229 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1230 let DecoderNamespace = "Thumb"; 1231} 1232 1233class T2I<dag oops, dag iops, InstrItinClass itin, 1234 string opc, string asm, list<dag> pattern> 1235 : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>; 1236class T2Ii12<dag oops, dag iops, InstrItinClass itin, 1237 string opc, string asm, list<dag> pattern> 1238 : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>; 1239class T2Ii8<dag oops, dag iops, InstrItinClass itin, 1240 string opc, string asm, list<dag> pattern> 1241 : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>; 1242class T2Iso<dag oops, dag iops, InstrItinClass itin, 1243 string opc, string asm, list<dag> pattern> 1244 : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>; 1245class T2Ipc<dag oops, dag iops, InstrItinClass itin, 1246 string opc, string asm, list<dag> pattern> 1247 : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>; 1248class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin, 1249 string opc, string asm, string cstr, list<dag> pattern> 1250 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr, 1251 pattern> { 1252 bits<4> Rt; 1253 bits<4> Rt2; 1254 bits<13> addr; 1255 let Inst{31-25} = 0b1110100; 1256 let Inst{24} = P; 1257 let Inst{23} = addr{8}; 1258 let Inst{22} = 1; 1259 let Inst{21} = W; 1260 let Inst{20} = isLoad; 1261 let Inst{19-16} = addr{12-9}; 1262 let Inst{15-12} = Rt{3-0}; 1263 let Inst{11-8} = Rt2{3-0}; 1264 let Inst{7-0} = addr{7-0}; 1265} 1266class T2Ii8s4post<bit P, bit W, bit isLoad, dag oops, dag iops, 1267 InstrItinClass itin, string opc, string asm, string cstr, 1268 list<dag> pattern> 1269 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr, 1270 pattern> { 1271 bits<4> Rt; 1272 bits<4> Rt2; 1273 bits<4> addr; 1274 bits<9> imm; 1275 let Inst{31-25} = 0b1110100; 1276 let Inst{24} = P; 1277 let Inst{23} = imm{8}; 1278 let Inst{22} = 1; 1279 let Inst{21} = W; 1280 let Inst{20} = isLoad; 1281 let Inst{19-16} = addr; 1282 let Inst{15-12} = Rt{3-0}; 1283 let Inst{11-8} = Rt2{3-0}; 1284 let Inst{7-0} = imm{7-0}; 1285} 1286 1287class T2sI<dag oops, dag iops, InstrItinClass itin, 1288 string opc, string asm, list<dag> pattern> 1289 : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>; 1290 1291class T2XI<dag oops, dag iops, InstrItinClass itin, 1292 string asm, list<dag> pattern> 1293 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>; 1294class T2JTI<dag oops, dag iops, InstrItinClass itin, 1295 string asm, list<dag> pattern> 1296 : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>; 1297 1298// Move to/from coprocessor instructions 1299class T2Cop<bits<4> opc, dag oops, dag iops, string opcstr, string asm, 1300 list<dag> pattern> 1301 : T2I <oops, iops, NoItinerary, opcstr, asm, pattern>, Requires<[IsThumb2]> { 1302 let Inst{31-28} = opc; 1303} 1304 1305// Two-address instructions 1306class T2XIt<dag oops, dag iops, InstrItinClass itin, 1307 string asm, string cstr, list<dag> pattern> 1308 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>; 1309 1310// T2Ipreldst - Thumb2 pre-indexed load / store instructions. 1311class T2Ipreldst<bit signed, bits<2> opcod, bit load, bit pre, 1312 dag oops, dag iops, 1313 AddrMode am, IndexMode im, InstrItinClass itin, 1314 string opc, string asm, string cstr, list<dag> pattern> 1315 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> { 1316 let OutOperandList = oops; 1317 let InOperandList = !con(iops, (ins pred:$p)); 1318 let AsmString = !strconcat(opc, "${p}", asm); 1319 let Pattern = pattern; 1320 list<Predicate> Predicates = [IsThumb2]; 1321 let DecoderNamespace = "Thumb2"; 1322 1323 bits<4> Rt; 1324 bits<13> addr; 1325 let Inst{31-27} = 0b11111; 1326 let Inst{26-25} = 0b00; 1327 let Inst{24} = signed; 1328 let Inst{23} = 0; 1329 let Inst{22-21} = opcod; 1330 let Inst{20} = load; 1331 let Inst{19-16} = addr{12-9}; 1332 let Inst{15-12} = Rt{3-0}; 1333 let Inst{11} = 1; 1334 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1335 let Inst{10} = pre; // The P bit. 1336 let Inst{9} = addr{8}; // Sign bit 1337 let Inst{8} = 1; // The W bit. 1338 let Inst{7-0} = addr{7-0}; 1339 1340 let DecoderMethod = "DecodeT2LdStPre"; 1341} 1342 1343// T2Ipostldst - Thumb2 post-indexed load / store instructions. 1344class T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre, 1345 dag oops, dag iops, 1346 AddrMode am, IndexMode im, InstrItinClass itin, 1347 string opc, string asm, string cstr, list<dag> pattern> 1348 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> { 1349 let OutOperandList = oops; 1350 let InOperandList = !con(iops, (ins pred:$p)); 1351 let AsmString = !strconcat(opc, "${p}", asm); 1352 let Pattern = pattern; 1353 list<Predicate> Predicates = [IsThumb2]; 1354 let DecoderNamespace = "Thumb2"; 1355 1356 bits<4> Rt; 1357 bits<4> Rn; 1358 bits<9> offset; 1359 let Inst{31-27} = 0b11111; 1360 let Inst{26-25} = 0b00; 1361 let Inst{24} = signed; 1362 let Inst{23} = 0; 1363 let Inst{22-21} = opcod; 1364 let Inst{20} = load; 1365 let Inst{19-16} = Rn; 1366 let Inst{15-12} = Rt{3-0}; 1367 let Inst{11} = 1; 1368 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1369 let Inst{10} = pre; // The P bit. 1370 let Inst{9} = offset{8}; // Sign bit 1371 let Inst{8} = 1; // The W bit. 1372 let Inst{7-0} = offset{7-0}; 1373 1374 let DecoderMethod = "DecodeT2LdStPre"; 1375} 1376 1377// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 1378class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 1379 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T]; 1380} 1381 1382// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 1383class T1Pat<dag pattern, dag result> : Pat<pattern, result> { 1384 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1385} 1386 1387// T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode. 1388class T2v6Pat<dag pattern, dag result> : Pat<pattern, result> { 1389 list<Predicate> Predicates = [IsThumb2, HasV6T2]; 1390} 1391 1392// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 1393class T2Pat<dag pattern, dag result> : Pat<pattern, result> { 1394 list<Predicate> Predicates = [IsThumb2]; 1395} 1396 1397//===----------------------------------------------------------------------===// 1398 1399//===----------------------------------------------------------------------===// 1400// ARM VFP Instruction templates. 1401// 1402 1403// Almost all VFP instructions are predicable. 1404class VFPI<dag oops, dag iops, AddrMode am, int sz, 1405 IndexMode im, Format f, InstrItinClass itin, 1406 string opc, string asm, string cstr, list<dag> pattern> 1407 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1408 bits<4> p; 1409 let Inst{31-28} = p; 1410 let OutOperandList = oops; 1411 let InOperandList = !con(iops, (ins pred:$p)); 1412 let AsmString = !strconcat(opc, "${p}", asm); 1413 let Pattern = pattern; 1414 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1415 let DecoderNamespace = "VFP"; 1416 list<Predicate> Predicates = [HasVFP2]; 1417} 1418 1419// Special cases 1420class VFPXI<dag oops, dag iops, AddrMode am, int sz, 1421 IndexMode im, Format f, InstrItinClass itin, 1422 string asm, string cstr, list<dag> pattern> 1423 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1424 bits<4> p; 1425 let Inst{31-28} = p; 1426 let OutOperandList = oops; 1427 let InOperandList = iops; 1428 let AsmString = asm; 1429 let Pattern = pattern; 1430 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1431 let DecoderNamespace = "VFP"; 1432 list<Predicate> Predicates = [HasVFP2]; 1433} 1434 1435class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, 1436 string opc, string asm, list<dag> pattern> 1437 : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 1438 opc, asm, "", pattern> { 1439 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1440} 1441 1442// ARM VFP addrmode5 loads and stores 1443class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1444 InstrItinClass itin, 1445 string opc, string asm, list<dag> pattern> 1446 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone, 1447 VFPLdStFrm, itin, opc, asm, "", pattern> { 1448 // Instruction operands. 1449 bits<5> Dd; 1450 bits<13> addr; 1451 1452 // Encode instruction operands. 1453 let Inst{23} = addr{8}; // U (add = (U == '1')) 1454 let Inst{22} = Dd{4}; 1455 let Inst{19-16} = addr{12-9}; // Rn 1456 let Inst{15-12} = Dd{3-0}; 1457 let Inst{7-0} = addr{7-0}; // imm8 1458 1459 let Inst{27-24} = opcod1; 1460 let Inst{21-20} = opcod2; 1461 let Inst{11-9} = 0b101; 1462 let Inst{8} = 1; // Double precision 1463 1464 // Loads & stores operate on both NEON and VFP pipelines. 1465 let D = VFPNeonDomain; 1466} 1467 1468class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1469 InstrItinClass itin, 1470 string opc, string asm, list<dag> pattern> 1471 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone, 1472 VFPLdStFrm, itin, opc, asm, "", pattern> { 1473 // Instruction operands. 1474 bits<5> Sd; 1475 bits<13> addr; 1476 1477 // Encode instruction operands. 1478 let Inst{23} = addr{8}; // U (add = (U == '1')) 1479 let Inst{22} = Sd{0}; 1480 let Inst{19-16} = addr{12-9}; // Rn 1481 let Inst{15-12} = Sd{4-1}; 1482 let Inst{7-0} = addr{7-0}; // imm8 1483 1484 let Inst{27-24} = opcod1; 1485 let Inst{21-20} = opcod2; 1486 let Inst{11-9} = 0b101; 1487 let Inst{8} = 0; // Single precision 1488 1489 // Loads & stores operate on both NEON and VFP pipelines. 1490 let D = VFPNeonDomain; 1491} 1492 1493// VFP Load / store multiple pseudo instructions. 1494class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr, 1495 list<dag> pattern> 1496 : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain, 1497 cstr, itin> { 1498 let OutOperandList = oops; 1499 let InOperandList = !con(iops, (ins pred:$p)); 1500 let Pattern = pattern; 1501 list<Predicate> Predicates = [HasVFP2]; 1502} 1503 1504// Load / store multiple 1505 1506// Unknown precision 1507class AXXI4<dag oops, dag iops, IndexMode im, 1508 string asm, string cstr, list<dag> pattern> 1509 : VFPXI<oops, iops, AddrMode4, 4, im, 1510 VFPLdStFrm, NoItinerary, asm, cstr, pattern> { 1511 // Instruction operands. 1512 bits<4> Rn; 1513 bits<13> regs; 1514 1515 // Encode instruction operands. 1516 let Inst{19-16} = Rn; 1517 let Inst{22} = 0; 1518 let Inst{15-12} = regs{11-8}; 1519 let Inst{7-1} = regs{7-1}; 1520 1521 let Inst{27-25} = 0b110; 1522 let Inst{11-8} = 0b1011; 1523 let Inst{0} = 1; 1524} 1525 1526// Double precision 1527class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1528 string asm, string cstr, list<dag> pattern> 1529 : VFPXI<oops, iops, AddrMode4, 4, im, 1530 VFPLdStMulFrm, itin, asm, cstr, pattern> { 1531 // Instruction operands. 1532 bits<4> Rn; 1533 bits<13> regs; 1534 1535 // Encode instruction operands. 1536 let Inst{19-16} = Rn; 1537 let Inst{22} = regs{12}; 1538 let Inst{15-12} = regs{11-8}; 1539 let Inst{7-1} = regs{7-1}; 1540 1541 let Inst{27-25} = 0b110; 1542 let Inst{11-9} = 0b101; 1543 let Inst{8} = 1; // Double precision 1544 let Inst{0} = 0; 1545} 1546 1547// Single Precision 1548class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1549 string asm, string cstr, list<dag> pattern> 1550 : VFPXI<oops, iops, AddrMode4, 4, im, 1551 VFPLdStMulFrm, itin, asm, cstr, pattern> { 1552 // Instruction operands. 1553 bits<4> Rn; 1554 bits<13> regs; 1555 1556 // Encode instruction operands. 1557 let Inst{19-16} = Rn; 1558 let Inst{22} = regs{8}; 1559 let Inst{15-12} = regs{12-9}; 1560 let Inst{7-0} = regs{7-0}; 1561 1562 let Inst{27-25} = 0b110; 1563 let Inst{11-9} = 0b101; 1564 let Inst{8} = 0; // Single precision 1565} 1566 1567// Double precision, unary 1568class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1569 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1570 string asm, list<dag> pattern> 1571 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1572 // Instruction operands. 1573 bits<5> Dd; 1574 bits<5> Dm; 1575 1576 // Encode instruction operands. 1577 let Inst{3-0} = Dm{3-0}; 1578 let Inst{5} = Dm{4}; 1579 let Inst{15-12} = Dd{3-0}; 1580 let Inst{22} = Dd{4}; 1581 1582 let Inst{27-23} = opcod1; 1583 let Inst{21-20} = opcod2; 1584 let Inst{19-16} = opcod3; 1585 let Inst{11-9} = 0b101; 1586 let Inst{8} = 1; // Double precision 1587 let Inst{7-6} = opcod4; 1588 let Inst{4} = opcod5; 1589 1590 let Predicates = [HasVFP2, HasDPVFP]; 1591} 1592 1593// Double precision, unary, not-predicated 1594class ADuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1595 bit opcod5, dag oops, dag iops, InstrItinClass itin, 1596 string asm, list<dag> pattern> 1597 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, VFPUnaryFrm, itin, asm, "", pattern> { 1598 // Instruction operands. 1599 bits<5> Dd; 1600 bits<5> Dm; 1601 1602 let Inst{31-28} = 0b1111; 1603 1604 // Encode instruction operands. 1605 let Inst{3-0} = Dm{3-0}; 1606 let Inst{5} = Dm{4}; 1607 let Inst{15-12} = Dd{3-0}; 1608 let Inst{22} = Dd{4}; 1609 1610 let Inst{27-23} = opcod1; 1611 let Inst{21-20} = opcod2; 1612 let Inst{19-16} = opcod3; 1613 let Inst{11-9} = 0b101; 1614 let Inst{8} = 1; // Double precision 1615 let Inst{7-6} = opcod4; 1616 let Inst{4} = opcod5; 1617} 1618 1619// Double precision, binary 1620class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1621 dag iops, InstrItinClass itin, string opc, string asm, 1622 list<dag> pattern> 1623 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1624 // Instruction operands. 1625 bits<5> Dd; 1626 bits<5> Dn; 1627 bits<5> Dm; 1628 1629 // Encode instruction operands. 1630 let Inst{3-0} = Dm{3-0}; 1631 let Inst{5} = Dm{4}; 1632 let Inst{19-16} = Dn{3-0}; 1633 let Inst{7} = Dn{4}; 1634 let Inst{15-12} = Dd{3-0}; 1635 let Inst{22} = Dd{4}; 1636 1637 let Inst{27-23} = opcod1; 1638 let Inst{21-20} = opcod2; 1639 let Inst{11-9} = 0b101; 1640 let Inst{8} = 1; // Double precision 1641 let Inst{6} = op6; 1642 let Inst{4} = op4; 1643 1644 let Predicates = [HasVFP2, HasDPVFP]; 1645} 1646 1647// FP, binary, not predicated 1648class ADbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops, 1649 InstrItinClass itin, string asm, list<dag> pattern> 1650 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, VFPBinaryFrm, itin, 1651 asm, "", pattern> 1652{ 1653 // Instruction operands. 1654 bits<5> Dd; 1655 bits<5> Dn; 1656 bits<5> Dm; 1657 1658 let Inst{31-28} = 0b1111; 1659 1660 // Encode instruction operands. 1661 let Inst{3-0} = Dm{3-0}; 1662 let Inst{5} = Dm{4}; 1663 let Inst{19-16} = Dn{3-0}; 1664 let Inst{7} = Dn{4}; 1665 let Inst{15-12} = Dd{3-0}; 1666 let Inst{22} = Dd{4}; 1667 1668 let Inst{27-23} = opcod1; 1669 let Inst{21-20} = opcod2; 1670 let Inst{11-9} = 0b101; 1671 let Inst{8} = 1; // double precision 1672 let Inst{6} = opcod3; 1673 let Inst{4} = 0; 1674 1675 let Predicates = [HasVFP2, HasDPVFP]; 1676} 1677 1678// Single precision, unary, predicated 1679class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1680 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1681 string asm, list<dag> pattern> 1682 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1683 // Instruction operands. 1684 bits<5> Sd; 1685 bits<5> Sm; 1686 1687 // Encode instruction operands. 1688 let Inst{3-0} = Sm{4-1}; 1689 let Inst{5} = Sm{0}; 1690 let Inst{15-12} = Sd{4-1}; 1691 let Inst{22} = Sd{0}; 1692 1693 let Inst{27-23} = opcod1; 1694 let Inst{21-20} = opcod2; 1695 let Inst{19-16} = opcod3; 1696 let Inst{11-9} = 0b101; 1697 let Inst{8} = 0; // Single precision 1698 let Inst{7-6} = opcod4; 1699 let Inst{4} = opcod5; 1700} 1701 1702// Single precision, unary, non-predicated 1703class ASuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1704 bit opcod5, dag oops, dag iops, InstrItinClass itin, 1705 string asm, list<dag> pattern> 1706 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, 1707 VFPUnaryFrm, itin, asm, "", pattern> { 1708 // Instruction operands. 1709 bits<5> Sd; 1710 bits<5> Sm; 1711 1712 let Inst{31-28} = 0b1111; 1713 1714 // Encode instruction operands. 1715 let Inst{3-0} = Sm{4-1}; 1716 let Inst{5} = Sm{0}; 1717 let Inst{15-12} = Sd{4-1}; 1718 let Inst{22} = Sd{0}; 1719 1720 let Inst{27-23} = opcod1; 1721 let Inst{21-20} = opcod2; 1722 let Inst{19-16} = opcod3; 1723 let Inst{11-9} = 0b101; 1724 let Inst{8} = 0; // Single precision 1725 let Inst{7-6} = opcod4; 1726 let Inst{4} = opcod5; 1727} 1728 1729// Single precision unary, if no NEON. Same as ASuI except not available if 1730// NEON is enabled. 1731class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1732 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1733 string asm, list<dag> pattern> 1734 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm, 1735 pattern> { 1736 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1737} 1738 1739// Single precision, binary 1740class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1741 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1742 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1743 // Instruction operands. 1744 bits<5> Sd; 1745 bits<5> Sn; 1746 bits<5> Sm; 1747 1748 // Encode instruction operands. 1749 let Inst{3-0} = Sm{4-1}; 1750 let Inst{5} = Sm{0}; 1751 let Inst{19-16} = Sn{4-1}; 1752 let Inst{7} = Sn{0}; 1753 let Inst{15-12} = Sd{4-1}; 1754 let Inst{22} = Sd{0}; 1755 1756 let Inst{27-23} = opcod1; 1757 let Inst{21-20} = opcod2; 1758 let Inst{11-9} = 0b101; 1759 let Inst{8} = 0; // Single precision 1760 let Inst{6} = op6; 1761 let Inst{4} = op4; 1762} 1763 1764// Single precision, binary, not predicated 1765class ASbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops, 1766 InstrItinClass itin, string asm, list<dag> pattern> 1767 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, 1768 VFPBinaryFrm, itin, asm, "", pattern> 1769{ 1770 // Instruction operands. 1771 bits<5> Sd; 1772 bits<5> Sn; 1773 bits<5> Sm; 1774 1775 let Inst{31-28} = 0b1111; 1776 1777 // Encode instruction operands. 1778 let Inst{3-0} = Sm{4-1}; 1779 let Inst{5} = Sm{0}; 1780 let Inst{19-16} = Sn{4-1}; 1781 let Inst{7} = Sn{0}; 1782 let Inst{15-12} = Sd{4-1}; 1783 let Inst{22} = Sd{0}; 1784 1785 let Inst{27-23} = opcod1; 1786 let Inst{21-20} = opcod2; 1787 let Inst{11-9} = 0b101; 1788 let Inst{8} = 0; // Single precision 1789 let Inst{6} = opcod3; 1790 let Inst{4} = 0; 1791} 1792 1793// Single precision binary, if no NEON. Same as ASbI except not available if 1794// NEON is enabled. 1795class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1796 dag iops, InstrItinClass itin, string opc, string asm, 1797 list<dag> pattern> 1798 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1799 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1800 1801 // Instruction operands. 1802 bits<5> Sd; 1803 bits<5> Sn; 1804 bits<5> Sm; 1805 1806 // Encode instruction operands. 1807 let Inst{3-0} = Sm{4-1}; 1808 let Inst{5} = Sm{0}; 1809 let Inst{19-16} = Sn{4-1}; 1810 let Inst{7} = Sn{0}; 1811 let Inst{15-12} = Sd{4-1}; 1812 let Inst{22} = Sd{0}; 1813} 1814 1815// VFP conversion instructions 1816class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1817 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1818 list<dag> pattern> 1819 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { 1820 let Inst{27-23} = opcod1; 1821 let Inst{21-20} = opcod2; 1822 let Inst{19-16} = opcod3; 1823 let Inst{11-8} = opcod4; 1824 let Inst{6} = 1; 1825 let Inst{4} = 0; 1826} 1827 1828// VFP conversion between floating-point and fixed-point 1829class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 1830 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1831 list<dag> pattern> 1832 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { 1833 bits<5> fbits; 1834 // size (fixed-point number): sx == 0 ? 16 : 32 1835 let Inst{7} = op5; // sx 1836 let Inst{5} = fbits{0}; 1837 let Inst{3-0} = fbits{4-1}; 1838} 1839 1840// VFP conversion instructions, if no NEON 1841class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1842 dag oops, dag iops, InstrItinClass itin, 1843 string opc, string asm, list<dag> pattern> 1844 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1845 pattern> { 1846 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1847} 1848 1849class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1850 InstrItinClass itin, 1851 string opc, string asm, list<dag> pattern> 1852 : VFPAI<oops, iops, f, itin, opc, asm, pattern> { 1853 let Inst{27-20} = opcod1; 1854 let Inst{11-8} = opcod2; 1855 let Inst{4} = 1; 1856} 1857 1858class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1859 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1860 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; 1861 1862class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1863 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1864 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; 1865 1866class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1867 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1868 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; 1869 1870class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1871 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1872 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; 1873 1874//===----------------------------------------------------------------------===// 1875 1876//===----------------------------------------------------------------------===// 1877// ARM NEON Instruction templates. 1878// 1879 1880class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1881 InstrItinClass itin, string opc, string dt, string asm, string cstr, 1882 list<dag> pattern> 1883 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> { 1884 let OutOperandList = oops; 1885 let InOperandList = !con(iops, (ins pred:$p)); 1886 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1887 let Pattern = pattern; 1888 list<Predicate> Predicates = [HasNEON]; 1889 let DecoderNamespace = "NEON"; 1890} 1891 1892// Same as NeonI except it does not have a "data type" specifier. 1893class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1894 InstrItinClass itin, string opc, string asm, string cstr, 1895 list<dag> pattern> 1896 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> { 1897 let OutOperandList = oops; 1898 let InOperandList = !con(iops, (ins pred:$p)); 1899 let AsmString = !strconcat(opc, "${p}", "\t", asm); 1900 let Pattern = pattern; 1901 list<Predicate> Predicates = [HasNEON]; 1902 let DecoderNamespace = "NEON"; 1903} 1904 1905// Same as NeonI except it is not predicated 1906class NeonInp<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1907 InstrItinClass itin, string opc, string dt, string asm, string cstr, 1908 list<dag> pattern> 1909 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> { 1910 let OutOperandList = oops; 1911 let InOperandList = iops; 1912 let AsmString = !strconcat(opc, ".", dt, "\t", asm); 1913 let Pattern = pattern; 1914 list<Predicate> Predicates = [HasNEON]; 1915 let DecoderNamespace = "NEON"; 1916 1917 let Inst{31-28} = 0b1111; 1918} 1919 1920class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1921 dag oops, dag iops, InstrItinClass itin, 1922 string opc, string dt, string asm, string cstr, list<dag> pattern> 1923 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm, 1924 cstr, pattern> { 1925 let Inst{31-24} = 0b11110100; 1926 let Inst{23} = op23; 1927 let Inst{21-20} = op21_20; 1928 let Inst{11-8} = op11_8; 1929 let Inst{7-4} = op7_4; 1930 1931 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder"; 1932 let DecoderNamespace = "NEONLoadStore"; 1933 1934 bits<5> Vd; 1935 bits<6> Rn; 1936 bits<4> Rm; 1937 1938 let Inst{22} = Vd{4}; 1939 let Inst{15-12} = Vd{3-0}; 1940 let Inst{19-16} = Rn{3-0}; 1941 let Inst{3-0} = Rm{3-0}; 1942} 1943 1944class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1945 dag oops, dag iops, InstrItinClass itin, 1946 string opc, string dt, string asm, string cstr, list<dag> pattern> 1947 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc, 1948 dt, asm, cstr, pattern> { 1949 bits<3> lane; 1950} 1951 1952class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr> 1953 : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr, 1954 itin> { 1955 let OutOperandList = oops; 1956 let InOperandList = !con(iops, (ins pred:$p)); 1957 list<Predicate> Predicates = [HasNEON]; 1958} 1959 1960class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr, 1961 list<dag> pattern> 1962 : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr, 1963 itin> { 1964 let OutOperandList = oops; 1965 let InOperandList = !con(iops, (ins pred:$p)); 1966 let Pattern = pattern; 1967 list<Predicate> Predicates = [HasNEON]; 1968} 1969 1970class NDataI<dag oops, dag iops, Format f, InstrItinClass itin, 1971 string opc, string dt, string asm, string cstr, list<dag> pattern> 1972 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr, 1973 pattern> { 1974 let Inst{31-25} = 0b1111001; 1975 let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1976 let DecoderNamespace = "NEONData"; 1977} 1978 1979class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin, 1980 string opc, string asm, string cstr, list<dag> pattern> 1981 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm, 1982 cstr, pattern> { 1983 let Inst{31-25} = 0b1111001; 1984 let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1985 let DecoderNamespace = "NEONData"; 1986} 1987 1988// NEON "one register and a modified immediate" format. 1989class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1990 bit op5, bit op4, 1991 dag oops, dag iops, InstrItinClass itin, 1992 string opc, string dt, string asm, string cstr, 1993 list<dag> pattern> 1994 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> { 1995 let Inst{23} = op23; 1996 let Inst{21-19} = op21_19; 1997 let Inst{11-8} = op11_8; 1998 let Inst{7} = op7; 1999 let Inst{6} = op6; 2000 let Inst{5} = op5; 2001 let Inst{4} = op4; 2002 2003 // Instruction operands. 2004 bits<5> Vd; 2005 bits<13> SIMM; 2006 2007 let Inst{15-12} = Vd{3-0}; 2008 let Inst{22} = Vd{4}; 2009 let Inst{24} = SIMM{7}; 2010 let Inst{18-16} = SIMM{6-4}; 2011 let Inst{3-0} = SIMM{3-0}; 2012 let DecoderMethod = "DecodeNEONModImmInstruction"; 2013} 2014 2015// NEON 2 vector register format. 2016class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 2017 bits<5> op11_7, bit op6, bit op4, 2018 dag oops, dag iops, InstrItinClass itin, 2019 string opc, string dt, string asm, string cstr, list<dag> pattern> 2020 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> { 2021 let Inst{24-23} = op24_23; 2022 let Inst{21-20} = op21_20; 2023 let Inst{19-18} = op19_18; 2024 let Inst{17-16} = op17_16; 2025 let Inst{11-7} = op11_7; 2026 let Inst{6} = op6; 2027 let Inst{4} = op4; 2028 2029 // Instruction operands. 2030 bits<5> Vd; 2031 bits<5> Vm; 2032 2033 let Inst{15-12} = Vd{3-0}; 2034 let Inst{22} = Vd{4}; 2035 let Inst{3-0} = Vm{3-0}; 2036 let Inst{5} = Vm{4}; 2037} 2038 2039// Same as N2V but not predicated. 2040class N2Vnp<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6, 2041 dag oops, dag iops, InstrItinClass itin, string OpcodeStr, 2042 string Dt, list<dag> pattern> 2043 : NeonInp<oops, iops, AddrModeNone, IndexModeNone, N2RegFrm, itin, 2044 OpcodeStr, Dt, "$Vd, $Vm", "", pattern> { 2045 bits<5> Vd; 2046 bits<5> Vm; 2047 2048 // Encode instruction operands 2049 let Inst{22} = Vd{4}; 2050 let Inst{15-12} = Vd{3-0}; 2051 let Inst{5} = Vm{4}; 2052 let Inst{3-0} = Vm{3-0}; 2053 2054 // Encode constant bits 2055 let Inst{27-23} = 0b00111; 2056 let Inst{21-20} = 0b11; 2057 let Inst{19-18} = op19_18; 2058 let Inst{17-16} = op17_16; 2059 let Inst{11} = 0; 2060 let Inst{10-8} = op10_8; 2061 let Inst{7} = op7; 2062 let Inst{6} = op6; 2063 let Inst{4} = 0; 2064 2065 let DecoderNamespace = "NEON"; 2066} 2067 2068// Same as N2V except it doesn't have a datatype suffix. 2069class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 2070 bits<5> op11_7, bit op6, bit op4, 2071 dag oops, dag iops, InstrItinClass itin, 2072 string opc, string asm, string cstr, list<dag> pattern> 2073 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> { 2074 let Inst{24-23} = op24_23; 2075 let Inst{21-20} = op21_20; 2076 let Inst{19-18} = op19_18; 2077 let Inst{17-16} = op17_16; 2078 let Inst{11-7} = op11_7; 2079 let Inst{6} = op6; 2080 let Inst{4} = op4; 2081 2082 // Instruction operands. 2083 bits<5> Vd; 2084 bits<5> Vm; 2085 2086 let Inst{15-12} = Vd{3-0}; 2087 let Inst{22} = Vd{4}; 2088 let Inst{3-0} = Vm{3-0}; 2089 let Inst{5} = Vm{4}; 2090} 2091 2092// NEON 2 vector register with immediate. 2093class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 2094 dag oops, dag iops, Format f, InstrItinClass itin, 2095 string opc, string dt, string asm, string cstr, list<dag> pattern> 2096 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 2097 let Inst{24} = op24; 2098 let Inst{23} = op23; 2099 let Inst{11-8} = op11_8; 2100 let Inst{7} = op7; 2101 let Inst{6} = op6; 2102 let Inst{4} = op4; 2103 2104 // Instruction operands. 2105 bits<5> Vd; 2106 bits<5> Vm; 2107 bits<6> SIMM; 2108 2109 let Inst{15-12} = Vd{3-0}; 2110 let Inst{22} = Vd{4}; 2111 let Inst{3-0} = Vm{3-0}; 2112 let Inst{5} = Vm{4}; 2113 let Inst{21-16} = SIMM{5-0}; 2114} 2115 2116// NEON 3 vector register format. 2117 2118class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 2119 bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 2120 string opc, string dt, string asm, string cstr, 2121 list<dag> pattern> 2122 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 2123 let Inst{24} = op24; 2124 let Inst{23} = op23; 2125 let Inst{21-20} = op21_20; 2126 let Inst{11-8} = op11_8; 2127 let Inst{6} = op6; 2128 let Inst{4} = op4; 2129} 2130 2131class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 2132 dag oops, dag iops, Format f, InstrItinClass itin, 2133 string opc, string dt, string asm, string cstr, list<dag> pattern> 2134 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 2135 oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 2136 // Instruction operands. 2137 bits<5> Vd; 2138 bits<5> Vn; 2139 bits<5> Vm; 2140 2141 let Inst{15-12} = Vd{3-0}; 2142 let Inst{22} = Vd{4}; 2143 let Inst{19-16} = Vn{3-0}; 2144 let Inst{7} = Vn{4}; 2145 let Inst{3-0} = Vm{3-0}; 2146 let Inst{5} = Vm{4}; 2147} 2148 2149class N3Vnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6, 2150 bit op4, dag oops, dag iops,Format f, InstrItinClass itin, 2151 string OpcodeStr, string Dt, list<dag> pattern> 2152 : NeonInp<oops, iops, AddrModeNone, IndexModeNone, f, itin, OpcodeStr, 2153 Dt, "$Vd, $Vn, $Vm", "", pattern> { 2154 bits<5> Vd; 2155 bits<5> Vn; 2156 bits<5> Vm; 2157 2158 // Encode instruction operands 2159 let Inst{22} = Vd{4}; 2160 let Inst{15-12} = Vd{3-0}; 2161 let Inst{19-16} = Vn{3-0}; 2162 let Inst{7} = Vn{4}; 2163 let Inst{5} = Vm{4}; 2164 let Inst{3-0} = Vm{3-0}; 2165 2166 // Encode constant bits 2167 let Inst{27-23} = op27_23; 2168 let Inst{21-20} = op21_20; 2169 let Inst{11-8} = op11_8; 2170 let Inst{6} = op6; 2171 let Inst{4} = op4; 2172} 2173 2174class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 2175 bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 2176 string opc, string dt, string asm, string cstr, 2177 list<dag> pattern> 2178 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 2179 oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 2180 2181 // Instruction operands. 2182 bits<5> Vd; 2183 bits<5> Vn; 2184 bits<5> Vm; 2185 bit lane; 2186 2187 let Inst{15-12} = Vd{3-0}; 2188 let Inst{22} = Vd{4}; 2189 let Inst{19-16} = Vn{3-0}; 2190 let Inst{7} = Vn{4}; 2191 let Inst{3-0} = Vm{3-0}; 2192 let Inst{5} = lane; 2193} 2194 2195class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 2196 bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 2197 string opc, string dt, string asm, string cstr, 2198 list<dag> pattern> 2199 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 2200 oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 2201 2202 // Instruction operands. 2203 bits<5> Vd; 2204 bits<5> Vn; 2205 bits<5> Vm; 2206 bits<2> lane; 2207 2208 let Inst{15-12} = Vd{3-0}; 2209 let Inst{22} = Vd{4}; 2210 let Inst{19-16} = Vn{3-0}; 2211 let Inst{7} = Vn{4}; 2212 let Inst{2-0} = Vm{2-0}; 2213 let Inst{5} = lane{1}; 2214 let Inst{3} = lane{0}; 2215} 2216 2217// Same as N3V except it doesn't have a data type suffix. 2218class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 2219 bit op4, 2220 dag oops, dag iops, Format f, InstrItinClass itin, 2221 string opc, string asm, string cstr, list<dag> pattern> 2222 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> { 2223 let Inst{24} = op24; 2224 let Inst{23} = op23; 2225 let Inst{21-20} = op21_20; 2226 let Inst{11-8} = op11_8; 2227 let Inst{6} = op6; 2228 let Inst{4} = op4; 2229 2230 // Instruction operands. 2231 bits<5> Vd; 2232 bits<5> Vn; 2233 bits<5> Vm; 2234 2235 let Inst{15-12} = Vd{3-0}; 2236 let Inst{22} = Vd{4}; 2237 let Inst{19-16} = Vn{3-0}; 2238 let Inst{7} = Vn{4}; 2239 let Inst{3-0} = Vm{3-0}; 2240 let Inst{5} = Vm{4}; 2241} 2242 2243// NEON VMOVs between scalar and core registers. 2244class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2245 dag oops, dag iops, Format f, InstrItinClass itin, 2246 string opc, string dt, string asm, list<dag> pattern> 2247 : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain, 2248 "", itin> { 2249 let Inst{27-20} = opcod1; 2250 let Inst{11-8} = opcod2; 2251 let Inst{6-5} = opcod3; 2252 let Inst{4} = 1; 2253 // A8.6.303, A8.6.328, A8.6.329 2254 let Inst{3-0} = 0b0000; 2255 2256 let OutOperandList = oops; 2257 let InOperandList = !con(iops, (ins pred:$p)); 2258 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 2259 let Pattern = pattern; 2260 list<Predicate> Predicates = [HasNEON]; 2261 2262 let PostEncoderMethod = "NEONThumb2DupPostEncoder"; 2263 let DecoderNamespace = "NEONDup"; 2264 2265 bits<5> V; 2266 bits<4> R; 2267 bits<4> p; 2268 bits<4> lane; 2269 2270 let Inst{31-28} = p{3-0}; 2271 let Inst{7} = V{4}; 2272 let Inst{19-16} = V{3-0}; 2273 let Inst{15-12} = R{3-0}; 2274} 2275class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2276 dag oops, dag iops, InstrItinClass itin, 2277 string opc, string dt, string asm, list<dag> pattern> 2278 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin, 2279 opc, dt, asm, pattern>; 2280class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2281 dag oops, dag iops, InstrItinClass itin, 2282 string opc, string dt, string asm, list<dag> pattern> 2283 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin, 2284 opc, dt, asm, pattern>; 2285class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2286 dag oops, dag iops, InstrItinClass itin, 2287 string opc, string dt, string asm, list<dag> pattern> 2288 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin, 2289 opc, dt, asm, pattern>; 2290 2291// Vector Duplicate Lane (from scalar to all elements) 2292class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops, 2293 InstrItinClass itin, string opc, string dt, string asm, 2294 list<dag> pattern> 2295 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> { 2296 let Inst{24-23} = 0b11; 2297 let Inst{21-20} = 0b11; 2298 let Inst{19-16} = op19_16; 2299 let Inst{11-7} = 0b11000; 2300 let Inst{6} = op6; 2301 let Inst{4} = 0; 2302 2303 bits<5> Vd; 2304 bits<5> Vm; 2305 2306 let Inst{22} = Vd{4}; 2307 let Inst{15-12} = Vd{3-0}; 2308 let Inst{5} = Vm{4}; 2309 let Inst{3-0} = Vm{3-0}; 2310} 2311 2312// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON 2313// for single-precision FP. 2314class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { 2315 list<Predicate> Predicates = [HasNEON,UseNEONForFP]; 2316} 2317 2318// VFP/NEON Instruction aliases for type suffices. 2319class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> : 2320 InstAlias<!strconcat(opc, dt, "\t", asm), Result>, Requires<[HasVFP2]>; 2321 2322multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result> { 2323 def : VFPDataTypeInstAlias<opc, ".8", asm, Result>; 2324 def : VFPDataTypeInstAlias<opc, ".16", asm, Result>; 2325 def : VFPDataTypeInstAlias<opc, ".32", asm, Result>; 2326 def : VFPDataTypeInstAlias<opc, ".64", asm, Result>; 2327} 2328 2329multiclass NEONDTAnyInstAlias<string opc, string asm, dag Result> { 2330 let Predicates = [HasNEON] in { 2331 def : VFPDataTypeInstAlias<opc, ".8", asm, Result>; 2332 def : VFPDataTypeInstAlias<opc, ".16", asm, Result>; 2333 def : VFPDataTypeInstAlias<opc, ".32", asm, Result>; 2334 def : VFPDataTypeInstAlias<opc, ".64", asm, Result>; 2335} 2336} 2337 2338// The same alias classes using AsmPseudo instead, for the more complex 2339// stuff in NEON that InstAlias can't quite handle. 2340// Note that we can't use anonymous defm references here like we can 2341// above, as we care about the ultimate instruction enum names generated, unlike 2342// for instalias defs. 2343class NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> : 2344 AsmPseudoInst<!strconcat(opc, dt, "\t", asm), iops>, Requires<[HasNEON]>; 2345 2346// Data type suffix token aliases. Implements Table A7-3 in the ARM ARM. 2347def : TokenAlias<".s8", ".i8">; 2348def : TokenAlias<".u8", ".i8">; 2349def : TokenAlias<".s16", ".i16">; 2350def : TokenAlias<".u16", ".i16">; 2351def : TokenAlias<".s32", ".i32">; 2352def : TokenAlias<".u32", ".i32">; 2353def : TokenAlias<".s64", ".i64">; 2354def : TokenAlias<".u64", ".i64">; 2355 2356def : TokenAlias<".i8", ".8">; 2357def : TokenAlias<".i16", ".16">; 2358def : TokenAlias<".i32", ".32">; 2359def : TokenAlias<".i64", ".64">; 2360 2361def : TokenAlias<".p8", ".8">; 2362def : TokenAlias<".p16", ".16">; 2363 2364def : TokenAlias<".f32", ".32">; 2365def : TokenAlias<".f64", ".64">; 2366def : TokenAlias<".f", ".f32">; 2367def : TokenAlias<".d", ".f64">; 2368