ARMInstrFormats.td revision 276479
1//===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// ARM Instruction Format Definitions. 13// 14 15// Format specifies the encoding used by the instruction. This is part of the 16// ad-hoc solution used to emit machine instruction encodings by our machine 17// code emitter. 18class Format<bits<6> val> { 19 bits<6> Value = val; 20} 21 22def Pseudo : Format<0>; 23def MulFrm : Format<1>; 24def BrFrm : Format<2>; 25def BrMiscFrm : Format<3>; 26 27def DPFrm : Format<4>; 28def DPSoRegRegFrm : Format<5>; 29 30def LdFrm : Format<6>; 31def StFrm : Format<7>; 32def LdMiscFrm : Format<8>; 33def StMiscFrm : Format<9>; 34def LdStMulFrm : Format<10>; 35 36def LdStExFrm : Format<11>; 37 38def ArithMiscFrm : Format<12>; 39def SatFrm : Format<13>; 40def ExtFrm : Format<14>; 41 42def VFPUnaryFrm : Format<15>; 43def VFPBinaryFrm : Format<16>; 44def VFPConv1Frm : Format<17>; 45def VFPConv2Frm : Format<18>; 46def VFPConv3Frm : Format<19>; 47def VFPConv4Frm : Format<20>; 48def VFPConv5Frm : Format<21>; 49def VFPLdStFrm : Format<22>; 50def VFPLdStMulFrm : Format<23>; 51def VFPMiscFrm : Format<24>; 52 53def ThumbFrm : Format<25>; 54def MiscFrm : Format<26>; 55 56def NGetLnFrm : Format<27>; 57def NSetLnFrm : Format<28>; 58def NDupFrm : Format<29>; 59def NLdStFrm : Format<30>; 60def N1RegModImmFrm: Format<31>; 61def N2RegFrm : Format<32>; 62def NVCVTFrm : Format<33>; 63def NVDupLnFrm : Format<34>; 64def N2RegVShLFrm : Format<35>; 65def N2RegVShRFrm : Format<36>; 66def N3RegFrm : Format<37>; 67def N3RegVShFrm : Format<38>; 68def NVExtFrm : Format<39>; 69def NVMulSLFrm : Format<40>; 70def NVTBLFrm : Format<41>; 71def DPSoRegImmFrm : Format<42>; 72 73// Misc flags. 74 75// The instruction has an Rn register operand. 76// UnaryDP - Indicates this is a unary data processing instruction, i.e. 77// it doesn't have a Rn operand. 78class UnaryDP { bit isUnaryDataProc = 1; } 79 80// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 81// a 16-bit Thumb instruction if certain conditions are met. 82class Xform16Bit { bit canXformTo16Bit = 1; } 83 84//===----------------------------------------------------------------------===// 85// ARM Instruction flags. These need to match ARMBaseInstrInfo.h. 86// 87 88// FIXME: Once the JIT is MC-ized, these can go away. 89// Addressing mode. 90class AddrMode<bits<5> val> { 91 bits<5> Value = val; 92} 93def AddrModeNone : AddrMode<0>; 94def AddrMode1 : AddrMode<1>; 95def AddrMode2 : AddrMode<2>; 96def AddrMode3 : AddrMode<3>; 97def AddrMode4 : AddrMode<4>; 98def AddrMode5 : AddrMode<5>; 99def AddrMode6 : AddrMode<6>; 100def AddrModeT1_1 : AddrMode<7>; 101def AddrModeT1_2 : AddrMode<8>; 102def AddrModeT1_4 : AddrMode<9>; 103def AddrModeT1_s : AddrMode<10>; 104def AddrModeT2_i12 : AddrMode<11>; 105def AddrModeT2_i8 : AddrMode<12>; 106def AddrModeT2_so : AddrMode<13>; 107def AddrModeT2_pc : AddrMode<14>; 108def AddrModeT2_i8s4 : AddrMode<15>; 109def AddrMode_i12 : AddrMode<16>; 110 111// Load / store index mode. 112class IndexMode<bits<2> val> { 113 bits<2> Value = val; 114} 115def IndexModeNone : IndexMode<0>; 116def IndexModePre : IndexMode<1>; 117def IndexModePost : IndexMode<2>; 118def IndexModeUpd : IndexMode<3>; 119 120// Instruction execution domain. 121class Domain<bits<3> val> { 122 bits<3> Value = val; 123} 124def GenericDomain : Domain<0>; 125def VFPDomain : Domain<1>; // Instructions in VFP domain only 126def NeonDomain : Domain<2>; // Instructions in Neon domain only 127def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains 128def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8 129 130//===----------------------------------------------------------------------===// 131// ARM special operands. 132// 133 134// ARM imod and iflag operands, used only by the CPS instruction. 135def imod_op : Operand<i32> { 136 let PrintMethod = "printCPSIMod"; 137} 138 139def ProcIFlagsOperand : AsmOperandClass { 140 let Name = "ProcIFlags"; 141 let ParserMethod = "parseProcIFlagsOperand"; 142} 143def iflags_op : Operand<i32> { 144 let PrintMethod = "printCPSIFlag"; 145 let ParserMatchClass = ProcIFlagsOperand; 146} 147 148// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 149// register whose default is 0 (no register). 150def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; } 151def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), 152 (ops (i32 14), (i32 zero_reg))> { 153 let PrintMethod = "printPredicateOperand"; 154 let ParserMatchClass = CondCodeOperand; 155 let DecoderMethod = "DecodePredicateOperand"; 156} 157 158// Selectable predicate operand for CMOV instructions. We can't use a normal 159// predicate because the default values interfere with instruction selection. In 160// all other respects it is identical though: pseudo-instruction expansion 161// relies on the MachineOperands being compatible. 162def cmovpred : Operand<i32>, PredicateOp, 163 ComplexPattern<i32, 2, "SelectCMOVPred"> { 164 let MIOperandInfo = (ops i32imm, i32imm); 165 let PrintMethod = "printPredicateOperand"; 166} 167 168// Conditional code result for instructions whose 's' bit is set, e.g. subs. 169def CCOutOperand : AsmOperandClass { let Name = "CCOut"; } 170def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 171 let EncoderMethod = "getCCOutOpValue"; 172 let PrintMethod = "printSBitModifierOperand"; 173 let ParserMatchClass = CCOutOperand; 174 let DecoderMethod = "DecodeCCOutOperand"; 175} 176 177// Same as cc_out except it defaults to setting CPSR. 178def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 179 let EncoderMethod = "getCCOutOpValue"; 180 let PrintMethod = "printSBitModifierOperand"; 181 let ParserMatchClass = CCOutOperand; 182 let DecoderMethod = "DecodeCCOutOperand"; 183} 184 185// ARM special operands for disassembly only. 186// 187def SetEndAsmOperand : ImmAsmOperand { 188 let Name = "SetEndImm"; 189 let ParserMethod = "parseSetEndImm"; 190} 191def setend_op : Operand<i32> { 192 let PrintMethod = "printSetendOperand"; 193 let ParserMatchClass = SetEndAsmOperand; 194} 195 196def MSRMaskOperand : AsmOperandClass { 197 let Name = "MSRMask"; 198 let ParserMethod = "parseMSRMaskOperand"; 199} 200def msr_mask : Operand<i32> { 201 let PrintMethod = "printMSRMaskOperand"; 202 let DecoderMethod = "DecodeMSRMask"; 203 let ParserMatchClass = MSRMaskOperand; 204} 205 206// Shift Right Immediate - A shift right immediate is encoded differently from 207// other shift immediates. The imm6 field is encoded like so: 208// 209// Offset Encoding 210// 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0> 211// 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0> 212// 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0> 213// 64 64 - <imm> is encoded in imm6<5:0> 214def shr_imm8_asm_operand : ImmAsmOperand { let Name = "ShrImm8"; } 215def shr_imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 8; }]> { 216 let EncoderMethod = "getShiftRight8Imm"; 217 let DecoderMethod = "DecodeShiftRight8Imm"; 218 let ParserMatchClass = shr_imm8_asm_operand; 219} 220def shr_imm16_asm_operand : ImmAsmOperand { let Name = "ShrImm16"; } 221def shr_imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 16; }]> { 222 let EncoderMethod = "getShiftRight16Imm"; 223 let DecoderMethod = "DecodeShiftRight16Imm"; 224 let ParserMatchClass = shr_imm16_asm_operand; 225} 226def shr_imm32_asm_operand : ImmAsmOperand { let Name = "ShrImm32"; } 227def shr_imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]> { 228 let EncoderMethod = "getShiftRight32Imm"; 229 let DecoderMethod = "DecodeShiftRight32Imm"; 230 let ParserMatchClass = shr_imm32_asm_operand; 231} 232def shr_imm64_asm_operand : ImmAsmOperand { let Name = "ShrImm64"; } 233def shr_imm64 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 64; }]> { 234 let EncoderMethod = "getShiftRight64Imm"; 235 let DecoderMethod = "DecodeShiftRight64Imm"; 236 let ParserMatchClass = shr_imm64_asm_operand; 237} 238 239//===----------------------------------------------------------------------===// 240// ARM Assembler alias templates. 241// 242class ARMInstAlias<string Asm, dag Result, bit Emit = 0b1> 243 : InstAlias<Asm, Result, Emit>, Requires<[IsARM]>; 244class tInstAlias<string Asm, dag Result, bit Emit = 0b1> 245 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb]>; 246class t2InstAlias<string Asm, dag Result, bit Emit = 0b1> 247 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb2]>; 248class VFP2InstAlias<string Asm, dag Result, bit Emit = 0b1> 249 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP2]>; 250class VFP2DPInstAlias<string Asm, dag Result, bit Emit = 0b1> 251 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP2,HasDPVFP]>; 252class VFP3InstAlias<string Asm, dag Result, bit Emit = 0b1> 253 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP3]>; 254class NEONInstAlias<string Asm, dag Result, bit Emit = 0b1> 255 : InstAlias<Asm, Result, Emit>, Requires<[HasNEON]>; 256 257 258class VFP2MnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>, 259 Requires<[HasVFP2]>; 260class NEONMnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>, 261 Requires<[HasNEON]>; 262 263//===----------------------------------------------------------------------===// 264// ARM Instruction templates. 265// 266 267 268class InstTemplate<AddrMode am, int sz, IndexMode im, 269 Format f, Domain d, string cstr, InstrItinClass itin> 270 : Instruction { 271 let Namespace = "ARM"; 272 273 AddrMode AM = am; 274 int Size = sz; 275 IndexMode IM = im; 276 bits<2> IndexModeBits = IM.Value; 277 Format F = f; 278 bits<6> Form = F.Value; 279 Domain D = d; 280 bit isUnaryDataProc = 0; 281 bit canXformTo16Bit = 0; 282 // The instruction is a 16-bit flag setting Thumb instruction. Used 283 // by the parser to determine whether to require the 'S' suffix on the 284 // mnemonic (when not in an IT block) or preclude it (when in an IT block). 285 bit thumbArithFlagSetting = 0; 286 287 // If this is a pseudo instruction, mark it isCodeGenOnly. 288 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo"); 289 290 // The layout of TSFlags should be kept in sync with ARMBaseInfo.h. 291 let TSFlags{4-0} = AM.Value; 292 let TSFlags{6-5} = IndexModeBits; 293 let TSFlags{12-7} = Form; 294 let TSFlags{13} = isUnaryDataProc; 295 let TSFlags{14} = canXformTo16Bit; 296 let TSFlags{17-15} = D.Value; 297 let TSFlags{18} = thumbArithFlagSetting; 298 299 let Constraints = cstr; 300 let Itinerary = itin; 301} 302 303class Encoding { 304 field bits<32> Inst; 305 // Mask of bits that cause an encoding to be UNPREDICTABLE. 306 // If a bit is set, then if the corresponding bit in the 307 // target encoding differs from its value in the "Inst" field, 308 // the instruction is UNPREDICTABLE (SoftFail in abstract parlance). 309 field bits<32> Unpredictable = 0; 310 // SoftFail is the generic name for this field, but we alias it so 311 // as to make it more obvious what it means in ARM-land. 312 field bits<32> SoftFail = Unpredictable; 313} 314 315class InstARM<AddrMode am, int sz, IndexMode im, 316 Format f, Domain d, string cstr, InstrItinClass itin> 317 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding { 318 let DecoderNamespace = "ARM"; 319} 320 321// This Encoding-less class is used by Thumb1 to specify the encoding bits later 322// on by adding flavors to specific instructions. 323class InstThumb<AddrMode am, int sz, IndexMode im, 324 Format f, Domain d, string cstr, InstrItinClass itin> 325 : InstTemplate<am, sz, im, f, d, cstr, itin> { 326 let DecoderNamespace = "Thumb"; 327} 328 329// Pseudo-instructions for alternate assembly syntax (never used by codegen). 330// These are aliases that require C++ handling to convert to the target 331// instruction, while InstAliases can be handled directly by tblgen. 332class AsmPseudoInst<string asm, dag iops, dag oops = (outs)> 333 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 334 "", NoItinerary> { 335 let OutOperandList = oops; 336 let InOperandList = iops; 337 let Pattern = []; 338 let isCodeGenOnly = 0; // So we get asm matcher for it. 339 let AsmString = asm; 340 let isPseudo = 1; 341} 342 343class ARMAsmPseudo<string asm, dag iops, dag oops = (outs)> 344 : AsmPseudoInst<asm, iops, oops>, Requires<[IsARM]>; 345class tAsmPseudo<string asm, dag iops, dag oops = (outs)> 346 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb]>; 347class t2AsmPseudo<string asm, dag iops, dag oops = (outs)> 348 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb2]>; 349class VFP2AsmPseudo<string asm, dag iops, dag oops = (outs)> 350 : AsmPseudoInst<asm, iops, oops>, Requires<[HasVFP2]>; 351class NEONAsmPseudo<string asm, dag iops, dag oops = (outs)> 352 : AsmPseudoInst<asm, iops, oops>, Requires<[HasNEON]>; 353 354// Pseudo instructions for the code generator. 355class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern> 356 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, 357 GenericDomain, "", itin> { 358 let OutOperandList = oops; 359 let InOperandList = iops; 360 let Pattern = pattern; 361 let isCodeGenOnly = 1; 362 let isPseudo = 1; 363} 364 365// PseudoInst that's ARM-mode only. 366class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 367 list<dag> pattern> 368 : PseudoInst<oops, iops, itin, pattern> { 369 let Size = sz; 370 list<Predicate> Predicates = [IsARM]; 371} 372 373// PseudoInst that's Thumb-mode only. 374class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 375 list<dag> pattern> 376 : PseudoInst<oops, iops, itin, pattern> { 377 let Size = sz; 378 list<Predicate> Predicates = [IsThumb]; 379} 380 381// PseudoInst that's Thumb2-mode only. 382class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 383 list<dag> pattern> 384 : PseudoInst<oops, iops, itin, pattern> { 385 let Size = sz; 386 list<Predicate> Predicates = [IsThumb2]; 387} 388 389class ARMPseudoExpand<dag oops, dag iops, int sz, 390 InstrItinClass itin, list<dag> pattern, 391 dag Result> 392 : ARMPseudoInst<oops, iops, sz, itin, pattern>, 393 PseudoInstExpansion<Result>; 394 395class tPseudoExpand<dag oops, dag iops, int sz, 396 InstrItinClass itin, list<dag> pattern, 397 dag Result> 398 : tPseudoInst<oops, iops, sz, itin, pattern>, 399 PseudoInstExpansion<Result>; 400 401class t2PseudoExpand<dag oops, dag iops, int sz, 402 InstrItinClass itin, list<dag> pattern, 403 dag Result> 404 : t2PseudoInst<oops, iops, sz, itin, pattern>, 405 PseudoInstExpansion<Result>; 406 407// Almost all ARM instructions are predicable. 408class I<dag oops, dag iops, AddrMode am, int sz, 409 IndexMode im, Format f, InstrItinClass itin, 410 string opc, string asm, string cstr, 411 list<dag> pattern> 412 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 413 bits<4> p; 414 let Inst{31-28} = p; 415 let OutOperandList = oops; 416 let InOperandList = !con(iops, (ins pred:$p)); 417 let AsmString = !strconcat(opc, "${p}", asm); 418 let Pattern = pattern; 419 list<Predicate> Predicates = [IsARM]; 420} 421 422// A few are not predicable 423class InoP<dag oops, dag iops, AddrMode am, int sz, 424 IndexMode im, Format f, InstrItinClass itin, 425 string opc, string asm, string cstr, 426 list<dag> pattern> 427 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 428 let OutOperandList = oops; 429 let InOperandList = iops; 430 let AsmString = !strconcat(opc, asm); 431 let Pattern = pattern; 432 let isPredicable = 0; 433 list<Predicate> Predicates = [IsARM]; 434} 435 436// Same as I except it can optionally modify CPSR. Note it's modeled as an input 437// operand since by default it's a zero register. It will become an implicit def 438// once it's "flipped". 439class sI<dag oops, dag iops, AddrMode am, int sz, 440 IndexMode im, Format f, InstrItinClass itin, 441 string opc, string asm, string cstr, 442 list<dag> pattern> 443 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 444 bits<4> p; // Predicate operand 445 bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 446 let Inst{31-28} = p; 447 let Inst{20} = s; 448 449 let OutOperandList = oops; 450 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 451 let AsmString = !strconcat(opc, "${s}${p}", asm); 452 let Pattern = pattern; 453 list<Predicate> Predicates = [IsARM]; 454} 455 456// Special cases 457class XI<dag oops, dag iops, AddrMode am, int sz, 458 IndexMode im, Format f, InstrItinClass itin, 459 string asm, string cstr, list<dag> pattern> 460 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 461 let OutOperandList = oops; 462 let InOperandList = iops; 463 let AsmString = asm; 464 let Pattern = pattern; 465 list<Predicate> Predicates = [IsARM]; 466} 467 468class AI<dag oops, dag iops, Format f, InstrItinClass itin, 469 string opc, string asm, list<dag> pattern> 470 : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 471 opc, asm, "", pattern>; 472class AsI<dag oops, dag iops, Format f, InstrItinClass itin, 473 string opc, string asm, list<dag> pattern> 474 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 475 opc, asm, "", pattern>; 476class AXI<dag oops, dag iops, Format f, InstrItinClass itin, 477 string asm, list<dag> pattern> 478 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 479 asm, "", pattern>; 480class AXIM<dag oops, dag iops, AddrMode am, Format f, InstrItinClass itin, 481 string asm, list<dag> pattern> 482 : XI<oops, iops, am, 4, IndexModeNone, f, itin, 483 asm, "", pattern>; 484class AInoP<dag oops, dag iops, Format f, InstrItinClass itin, 485 string opc, string asm, list<dag> pattern> 486 : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 487 opc, asm, "", pattern>; 488 489// Ctrl flow instructions 490class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 491 string opc, string asm, list<dag> pattern> 492 : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin, 493 opc, asm, "", pattern> { 494 let Inst{27-24} = opcod; 495} 496class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 497 string asm, list<dag> pattern> 498 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin, 499 asm, "", pattern> { 500 let Inst{27-24} = opcod; 501} 502 503// BR_JT instructions 504class JTI<dag oops, dag iops, InstrItinClass itin, 505 string asm, list<dag> pattern> 506 : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin, 507 asm, "", pattern>; 508 509class AIldr_ex_or_acq<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin, 510 string opc, string asm, list<dag> pattern> 511 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin, 512 opc, asm, "", pattern> { 513 bits<4> Rt; 514 bits<4> addr; 515 let Inst{27-23} = 0b00011; 516 let Inst{22-21} = opcod; 517 let Inst{20} = 1; 518 let Inst{19-16} = addr; 519 let Inst{15-12} = Rt; 520 let Inst{11-10} = 0b11; 521 let Inst{9-8} = opcod2; 522 let Inst{7-0} = 0b10011111; 523} 524class AIstr_ex_or_rel<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin, 525 string opc, string asm, list<dag> pattern> 526 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin, 527 opc, asm, "", pattern> { 528 bits<4> Rt; 529 bits<4> addr; 530 let Inst{27-23} = 0b00011; 531 let Inst{22-21} = opcod; 532 let Inst{20} = 0; 533 let Inst{19-16} = addr; 534 let Inst{11-10} = 0b11; 535 let Inst{9-8} = opcod2; 536 let Inst{7-4} = 0b1001; 537 let Inst{3-0} = Rt; 538} 539// Atomic load/store instructions 540class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 541 string opc, string asm, list<dag> pattern> 542 : AIldr_ex_or_acq<opcod, 0b11, oops, iops, itin, opc, asm, pattern>; 543 544class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 545 string opc, string asm, list<dag> pattern> 546 : AIstr_ex_or_rel<opcod, 0b11, oops, iops, itin, opc, asm, pattern> { 547 bits<4> Rd; 548 let Inst{15-12} = Rd; 549} 550 551// Exclusive load/store instructions 552 553class AIldaex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 554 string opc, string asm, list<dag> pattern> 555 : AIldr_ex_or_acq<opcod, 0b10, oops, iops, itin, opc, asm, pattern>, 556 Requires<[IsARM, HasV8]>; 557 558class AIstlex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 559 string opc, string asm, list<dag> pattern> 560 : AIstr_ex_or_rel<opcod, 0b10, oops, iops, itin, opc, asm, pattern>, 561 Requires<[IsARM, HasV8]> { 562 bits<4> Rd; 563 let Inst{15-12} = Rd; 564} 565 566class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern> 567 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> { 568 bits<4> Rt; 569 bits<4> Rt2; 570 bits<4> addr; 571 let Inst{27-23} = 0b00010; 572 let Inst{22} = b; 573 let Inst{21-20} = 0b00; 574 let Inst{19-16} = addr; 575 let Inst{15-12} = Rt; 576 let Inst{11-4} = 0b00001001; 577 let Inst{3-0} = Rt2; 578 579 let Unpredictable{11-8} = 0b1111; 580 let DecoderMethod = "DecodeSwap"; 581} 582// Acquire/Release load/store instructions 583class AIldracq<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 584 string opc, string asm, list<dag> pattern> 585 : AIldr_ex_or_acq<opcod, 0b00, oops, iops, itin, opc, asm, pattern>, 586 Requires<[IsARM, HasV8]>; 587 588class AIstrrel<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 589 string opc, string asm, list<dag> pattern> 590 : AIstr_ex_or_rel<opcod, 0b00, oops, iops, itin, opc, asm, pattern>, 591 Requires<[IsARM, HasV8]> { 592 let Inst{15-12} = 0b1111; 593} 594 595// addrmode1 instructions 596class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 597 string opc, string asm, list<dag> pattern> 598 : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 599 opc, asm, "", pattern> { 600 let Inst{24-21} = opcod; 601 let Inst{27-26} = 0b00; 602} 603class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 604 string opc, string asm, list<dag> pattern> 605 : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 606 opc, asm, "", pattern> { 607 let Inst{24-21} = opcod; 608 let Inst{27-26} = 0b00; 609} 610class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 611 string asm, list<dag> pattern> 612 : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 613 asm, "", pattern> { 614 let Inst{24-21} = opcod; 615 let Inst{27-26} = 0b00; 616} 617 618// loads 619 620// LDR/LDRB/STR/STRB/... 621class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am, 622 Format f, InstrItinClass itin, string opc, string asm, 623 list<dag> pattern> 624 : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm, 625 "", pattern> { 626 let Inst{27-25} = op; 627 let Inst{24} = 1; // 24 == P 628 // 23 == U 629 let Inst{22} = isByte; 630 let Inst{21} = 0; // 21 == W 631 let Inst{20} = isLd; 632} 633// Indexed load/stores 634class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops, 635 IndexMode im, Format f, InstrItinClass itin, string opc, 636 string asm, string cstr, list<dag> pattern> 637 : I<oops, iops, AddrMode2, 4, im, f, itin, 638 opc, asm, cstr, pattern> { 639 bits<4> Rt; 640 let Inst{27-26} = 0b01; 641 let Inst{24} = isPre; // P bit 642 let Inst{22} = isByte; // B bit 643 let Inst{21} = isPre; // W bit 644 let Inst{20} = isLd; // L bit 645 let Inst{15-12} = Rt; 646} 647class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops, 648 IndexMode im, Format f, InstrItinClass itin, string opc, 649 string asm, string cstr, list<dag> pattern> 650 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 651 pattern> { 652 // AM2 store w/ two operands: (GPR, am2offset) 653 // {12} isAdd 654 // {11-0} imm12/Rm 655 bits<14> offset; 656 bits<4> Rn; 657 let Inst{25} = 1; 658 let Inst{23} = offset{12}; 659 let Inst{19-16} = Rn; 660 let Inst{11-5} = offset{11-5}; 661 let Inst{4} = 0; 662 let Inst{3-0} = offset{3-0}; 663} 664 665class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops, 666 IndexMode im, Format f, InstrItinClass itin, string opc, 667 string asm, string cstr, list<dag> pattern> 668 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 669 pattern> { 670 // AM2 store w/ two operands: (GPR, am2offset) 671 // {12} isAdd 672 // {11-0} imm12/Rm 673 bits<14> offset; 674 bits<4> Rn; 675 let Inst{25} = 0; 676 let Inst{23} = offset{12}; 677 let Inst{19-16} = Rn; 678 let Inst{11-0} = offset{11-0}; 679} 680 681 682// FIXME: Merge with the above class when addrmode2 gets used for STR, STRB 683// but for now use this class for STRT and STRBT. 684class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops, 685 IndexMode im, Format f, InstrItinClass itin, string opc, 686 string asm, string cstr, list<dag> pattern> 687 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 688 pattern> { 689 // AM2 store w/ two operands: (GPR, am2offset) 690 // {17-14} Rn 691 // {13} 1 == Rm, 0 == imm12 692 // {12} isAdd 693 // {11-0} imm12/Rm 694 bits<18> addr; 695 let Inst{25} = addr{13}; 696 let Inst{23} = addr{12}; 697 let Inst{19-16} = addr{17-14}; 698 let Inst{11-0} = addr{11-0}; 699} 700 701// addrmode3 instructions 702class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f, 703 InstrItinClass itin, string opc, string asm, list<dag> pattern> 704 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin, 705 opc, asm, "", pattern> { 706 bits<14> addr; 707 bits<4> Rt; 708 let Inst{27-25} = 0b000; 709 let Inst{24} = 1; // P bit 710 let Inst{23} = addr{8}; // U bit 711 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 712 let Inst{21} = 0; // W bit 713 let Inst{20} = op20; // L bit 714 let Inst{19-16} = addr{12-9}; // Rn 715 let Inst{15-12} = Rt; // Rt 716 let Inst{11-8} = addr{7-4}; // imm7_4/zero 717 let Inst{7-4} = op; 718 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 719 720 let DecoderMethod = "DecodeAddrMode3Instruction"; 721} 722 723class AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops, 724 IndexMode im, Format f, InstrItinClass itin, string opc, 725 string asm, string cstr, list<dag> pattern> 726 : I<oops, iops, AddrMode3, 4, im, f, itin, 727 opc, asm, cstr, pattern> { 728 bits<4> Rt; 729 let Inst{27-25} = 0b000; 730 let Inst{24} = isPre; // P bit 731 let Inst{21} = isPre; // W bit 732 let Inst{20} = op20; // L bit 733 let Inst{15-12} = Rt; // Rt 734 let Inst{7-4} = op; 735} 736 737// FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB 738// but for now use this class for LDRSBT, LDRHT, LDSHT. 739class AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops, 740 IndexMode im, Format f, InstrItinClass itin, string opc, 741 string asm, string cstr, list<dag> pattern> 742 : I<oops, iops, AddrMode3, 4, im, f, itin, opc, asm, cstr, pattern> { 743 // {13} 1 == imm8, 0 == Rm 744 // {12-9} Rn 745 // {8} isAdd 746 // {7-4} imm7_4/zero 747 // {3-0} imm3_0/Rm 748 bits<4> addr; 749 bits<4> Rt; 750 let Inst{27-25} = 0b000; 751 let Inst{24} = 0; // P bit 752 let Inst{21} = 1; 753 let Inst{20} = isLoad; // L bit 754 let Inst{19-16} = addr; // Rn 755 let Inst{15-12} = Rt; // Rt 756 let Inst{7-4} = op; 757} 758 759// stores 760class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin, 761 string opc, string asm, list<dag> pattern> 762 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin, 763 opc, asm, "", pattern> { 764 bits<14> addr; 765 bits<4> Rt; 766 let Inst{27-25} = 0b000; 767 let Inst{24} = 1; // P bit 768 let Inst{23} = addr{8}; // U bit 769 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 770 let Inst{21} = 0; // W bit 771 let Inst{20} = 0; // L bit 772 let Inst{19-16} = addr{12-9}; // Rn 773 let Inst{15-12} = Rt; // Rt 774 let Inst{11-8} = addr{7-4}; // imm7_4/zero 775 let Inst{7-4} = op; 776 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 777 let DecoderMethod = "DecodeAddrMode3Instruction"; 778} 779 780// addrmode4 instructions 781class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, 782 string asm, string cstr, list<dag> pattern> 783 : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> { 784 bits<4> p; 785 bits<16> regs; 786 bits<4> Rn; 787 let Inst{31-28} = p; 788 let Inst{27-25} = 0b100; 789 let Inst{22} = 0; // S bit 790 let Inst{19-16} = Rn; 791 let Inst{15-0} = regs; 792} 793 794// Unsigned multiply, multiply-accumulate instructions. 795class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 796 string opc, string asm, list<dag> pattern> 797 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 798 opc, asm, "", pattern> { 799 let Inst{7-4} = 0b1001; 800 let Inst{20} = 0; // S bit 801 let Inst{27-21} = opcod; 802} 803class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 804 string opc, string asm, list<dag> pattern> 805 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 806 opc, asm, "", pattern> { 807 let Inst{7-4} = 0b1001; 808 let Inst{27-21} = opcod; 809} 810 811// Most significant word multiply 812class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 813 InstrItinClass itin, string opc, string asm, list<dag> pattern> 814 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 815 opc, asm, "", pattern> { 816 bits<4> Rd; 817 bits<4> Rn; 818 bits<4> Rm; 819 let Inst{7-4} = opc7_4; 820 let Inst{20} = 1; 821 let Inst{27-21} = opcod; 822 let Inst{19-16} = Rd; 823 let Inst{11-8} = Rm; 824 let Inst{3-0} = Rn; 825} 826// MSW multiple w/ Ra operand 827class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 828 InstrItinClass itin, string opc, string asm, list<dag> pattern> 829 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> { 830 bits<4> Ra; 831 let Inst{15-12} = Ra; 832} 833 834// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 835class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 836 InstrItinClass itin, string opc, string asm, list<dag> pattern> 837 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 838 opc, asm, "", pattern> { 839 bits<4> Rn; 840 bits<4> Rm; 841 let Inst{4} = 0; 842 let Inst{7} = 1; 843 let Inst{20} = 0; 844 let Inst{27-21} = opcod; 845 let Inst{6-5} = bit6_5; 846 let Inst{11-8} = Rm; 847 let Inst{3-0} = Rn; 848} 849class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 850 InstrItinClass itin, string opc, string asm, list<dag> pattern> 851 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 852 bits<4> Rd; 853 let Inst{19-16} = Rd; 854} 855 856// AMulxyI with Ra operand 857class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 858 InstrItinClass itin, string opc, string asm, list<dag> pattern> 859 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 860 bits<4> Ra; 861 let Inst{15-12} = Ra; 862} 863// SMLAL* 864class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 865 InstrItinClass itin, string opc, string asm, list<dag> pattern> 866 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 867 bits<4> RdLo; 868 bits<4> RdHi; 869 let Inst{19-16} = RdHi; 870 let Inst{15-12} = RdLo; 871} 872 873// Extend instructions. 874class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 875 string opc, string asm, list<dag> pattern> 876 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin, 877 opc, asm, "", pattern> { 878 // All AExtI instructions have Rd and Rm register operands. 879 bits<4> Rd; 880 bits<4> Rm; 881 let Inst{15-12} = Rd; 882 let Inst{3-0} = Rm; 883 let Inst{7-4} = 0b0111; 884 let Inst{9-8} = 0b00; 885 let Inst{27-20} = opcod; 886 887 let Unpredictable{9-8} = 0b11; 888} 889 890// Misc Arithmetic instructions. 891class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops, 892 InstrItinClass itin, string opc, string asm, list<dag> pattern> 893 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, 894 opc, asm, "", pattern> { 895 bits<4> Rd; 896 bits<4> Rm; 897 let Inst{27-20} = opcod; 898 let Inst{19-16} = 0b1111; 899 let Inst{15-12} = Rd; 900 let Inst{11-8} = 0b1111; 901 let Inst{7-4} = opc7_4; 902 let Inst{3-0} = Rm; 903} 904 905// Division instructions. 906class ADivA1I<bits<3> opcod, dag oops, dag iops, 907 InstrItinClass itin, string opc, string asm, list<dag> pattern> 908 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, 909 opc, asm, "", pattern> { 910 bits<4> Rd; 911 bits<4> Rn; 912 bits<4> Rm; 913 let Inst{27-23} = 0b01110; 914 let Inst{22-20} = opcod; 915 let Inst{19-16} = Rd; 916 let Inst{15-12} = 0b1111; 917 let Inst{11-8} = Rm; 918 let Inst{7-4} = 0b0001; 919 let Inst{3-0} = Rn; 920} 921 922// PKH instructions 923def PKHLSLAsmOperand : ImmAsmOperand { 924 let Name = "PKHLSLImm"; 925 let ParserMethod = "parsePKHLSLImm"; 926} 927def pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{ 928 let PrintMethod = "printPKHLSLShiftImm"; 929 let ParserMatchClass = PKHLSLAsmOperand; 930} 931def PKHASRAsmOperand : AsmOperandClass { 932 let Name = "PKHASRImm"; 933 let ParserMethod = "parsePKHASRImm"; 934} 935def pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{ 936 let PrintMethod = "printPKHASRShiftImm"; 937 let ParserMatchClass = PKHASRAsmOperand; 938} 939 940class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin, 941 string opc, string asm, list<dag> pattern> 942 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, 943 opc, asm, "", pattern> { 944 bits<4> Rd; 945 bits<4> Rn; 946 bits<4> Rm; 947 bits<5> sh; 948 let Inst{27-20} = opcod; 949 let Inst{19-16} = Rn; 950 let Inst{15-12} = Rd; 951 let Inst{11-7} = sh; 952 let Inst{6} = tb; 953 let Inst{5-4} = 0b01; 954 let Inst{3-0} = Rm; 955} 956 957//===----------------------------------------------------------------------===// 958 959// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 960class ARMPat<dag pattern, dag result> : Pat<pattern, result> { 961 list<Predicate> Predicates = [IsARM]; 962} 963class ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> { 964 list<Predicate> Predicates = [IsARM, HasV5T]; 965} 966class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 967 list<Predicate> Predicates = [IsARM, HasV5TE]; 968} 969// ARMV5MOPat - Same as ARMV5TEPat with UseMulOps. 970class ARMV5MOPat<dag pattern, dag result> : Pat<pattern, result> { 971 list<Predicate> Predicates = [IsARM, HasV5TE, UseMulOps]; 972} 973class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 974 list<Predicate> Predicates = [IsARM, HasV6]; 975} 976 977//===----------------------------------------------------------------------===// 978// Thumb Instruction Format Definitions. 979// 980 981class ThumbI<dag oops, dag iops, AddrMode am, int sz, 982 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 983 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 984 let OutOperandList = oops; 985 let InOperandList = iops; 986 let AsmString = asm; 987 let Pattern = pattern; 988 list<Predicate> Predicates = [IsThumb]; 989} 990 991// TI - Thumb instruction. 992class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 993 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>; 994 995// Two-address instructions 996class TIt<dag oops, dag iops, InstrItinClass itin, string asm, 997 list<dag> pattern> 998 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst", 999 pattern>; 1000 1001// tBL, tBX 32-bit instructions 1002class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, 1003 dag oops, dag iops, InstrItinClass itin, string asm, 1004 list<dag> pattern> 1005 : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>, 1006 Encoding { 1007 let Inst{31-27} = opcod1; 1008 let Inst{15-14} = opcod2; 1009 let Inst{12} = opcod3; 1010} 1011 1012// BR_JT instructions 1013class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, 1014 list<dag> pattern> 1015 : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>; 1016 1017// Thumb1 only 1018class Thumb1I<dag oops, dag iops, AddrMode am, int sz, 1019 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 1020 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1021 let OutOperandList = oops; 1022 let InOperandList = iops; 1023 let AsmString = asm; 1024 let Pattern = pattern; 1025 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1026} 1027 1028class T1I<dag oops, dag iops, InstrItinClass itin, 1029 string asm, list<dag> pattern> 1030 : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>; 1031class T1Ix2<dag oops, dag iops, InstrItinClass itin, 1032 string asm, list<dag> pattern> 1033 : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>; 1034 1035// Two-address instructions 1036class T1It<dag oops, dag iops, InstrItinClass itin, 1037 string asm, string cstr, list<dag> pattern> 1038 : Thumb1I<oops, iops, AddrModeNone, 2, itin, 1039 asm, cstr, pattern>; 1040 1041// Thumb1 instruction that can either be predicated or set CPSR. 1042class Thumb1sI<dag oops, dag iops, AddrMode am, int sz, 1043 InstrItinClass itin, 1044 string opc, string asm, string cstr, list<dag> pattern> 1045 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1046 let OutOperandList = !con(oops, (outs s_cc_out:$s)); 1047 let InOperandList = !con(iops, (ins pred:$p)); 1048 let AsmString = !strconcat(opc, "${s}${p}", asm); 1049 let Pattern = pattern; 1050 let thumbArithFlagSetting = 1; 1051 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1052 let DecoderNamespace = "ThumbSBit"; 1053} 1054 1055class T1sI<dag oops, dag iops, InstrItinClass itin, 1056 string opc, string asm, list<dag> pattern> 1057 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>; 1058 1059// Two-address instructions 1060class T1sIt<dag oops, dag iops, InstrItinClass itin, 1061 string opc, string asm, list<dag> pattern> 1062 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, 1063 "$Rn = $Rdn", pattern>; 1064 1065// Thumb1 instruction that can be predicated. 1066class Thumb1pI<dag oops, dag iops, AddrMode am, int sz, 1067 InstrItinClass itin, 1068 string opc, string asm, string cstr, list<dag> pattern> 1069 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1070 let OutOperandList = oops; 1071 let InOperandList = !con(iops, (ins pred:$p)); 1072 let AsmString = !strconcat(opc, "${p}", asm); 1073 let Pattern = pattern; 1074 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1075} 1076 1077class T1pI<dag oops, dag iops, InstrItinClass itin, 1078 string opc, string asm, list<dag> pattern> 1079 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>; 1080 1081// Two-address instructions 1082class T1pIt<dag oops, dag iops, InstrItinClass itin, 1083 string opc, string asm, list<dag> pattern> 1084 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, 1085 "$Rn = $Rdn", pattern>; 1086 1087class T1pIs<dag oops, dag iops, 1088 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1089 : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>; 1090 1091class Encoding16 : Encoding { 1092 let Inst{31-16} = 0x0000; 1093} 1094 1095// A6.2 16-bit Thumb instruction encoding 1096class T1Encoding<bits<6> opcode> : Encoding16 { 1097 let Inst{15-10} = opcode; 1098} 1099 1100// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. 1101class T1General<bits<5> opcode> : Encoding16 { 1102 let Inst{15-14} = 0b00; 1103 let Inst{13-9} = opcode; 1104} 1105 1106// A6.2.2 Data-processing encoding. 1107class T1DataProcessing<bits<4> opcode> : Encoding16 { 1108 let Inst{15-10} = 0b010000; 1109 let Inst{9-6} = opcode; 1110} 1111 1112// A6.2.3 Special data instructions and branch and exchange encoding. 1113class T1Special<bits<4> opcode> : Encoding16 { 1114 let Inst{15-10} = 0b010001; 1115 let Inst{9-6} = opcode; 1116} 1117 1118// A6.2.4 Load/store single data item encoding. 1119class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { 1120 let Inst{15-12} = opA; 1121 let Inst{11-9} = opB; 1122} 1123class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative 1124 1125class T1BranchCond<bits<4> opcode> : Encoding16 { 1126 let Inst{15-12} = opcode; 1127} 1128 1129// Helper classes to encode Thumb1 loads and stores. For immediates, the 1130// following bits are used for "opA" (see A6.2.4): 1131// 1132// 0b0110 => Immediate, 4 bytes 1133// 0b1000 => Immediate, 2 bytes 1134// 0b0111 => Immediate, 1 byte 1135class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am, 1136 InstrItinClass itin, string opc, string asm, 1137 list<dag> pattern> 1138 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>, 1139 T1LoadStore<0b0101, opcode> { 1140 bits<3> Rt; 1141 bits<8> addr; 1142 let Inst{8-6} = addr{5-3}; // Rm 1143 let Inst{5-3} = addr{2-0}; // Rn 1144 let Inst{2-0} = Rt; 1145} 1146class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am, 1147 InstrItinClass itin, string opc, string asm, 1148 list<dag> pattern> 1149 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>, 1150 T1LoadStore<opA, {opB,?,?}> { 1151 bits<3> Rt; 1152 bits<8> addr; 1153 let Inst{10-6} = addr{7-3}; // imm5 1154 let Inst{5-3} = addr{2-0}; // Rn 1155 let Inst{2-0} = Rt; 1156} 1157 1158// A6.2.5 Miscellaneous 16-bit instructions encoding. 1159class T1Misc<bits<7> opcode> : Encoding16 { 1160 let Inst{15-12} = 0b1011; 1161 let Inst{11-5} = opcode; 1162} 1163 1164// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 1165class Thumb2I<dag oops, dag iops, AddrMode am, int sz, 1166 InstrItinClass itin, 1167 string opc, string asm, string cstr, list<dag> pattern> 1168 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1169 let OutOperandList = oops; 1170 let InOperandList = !con(iops, (ins pred:$p)); 1171 let AsmString = !strconcat(opc, "${p}", asm); 1172 let Pattern = pattern; 1173 list<Predicate> Predicates = [IsThumb2]; 1174 let DecoderNamespace = "Thumb2"; 1175} 1176 1177// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an 1178// input operand since by default it's a zero register. It will become an 1179// implicit def once it's "flipped". 1180// 1181// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 1182// more consistent. 1183class Thumb2sI<dag oops, dag iops, AddrMode am, int sz, 1184 InstrItinClass itin, 1185 string opc, string asm, string cstr, list<dag> pattern> 1186 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1187 bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 1188 let Inst{20} = s; 1189 1190 let OutOperandList = oops; 1191 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 1192 let AsmString = !strconcat(opc, "${s}${p}", asm); 1193 let Pattern = pattern; 1194 list<Predicate> Predicates = [IsThumb2]; 1195 let DecoderNamespace = "Thumb2"; 1196} 1197 1198// Special cases 1199class Thumb2XI<dag oops, dag iops, AddrMode am, int sz, 1200 InstrItinClass itin, 1201 string asm, string cstr, list<dag> pattern> 1202 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1203 let OutOperandList = oops; 1204 let InOperandList = iops; 1205 let AsmString = asm; 1206 let Pattern = pattern; 1207 list<Predicate> Predicates = [IsThumb2]; 1208 let DecoderNamespace = "Thumb2"; 1209} 1210 1211class ThumbXI<dag oops, dag iops, AddrMode am, int sz, 1212 InstrItinClass itin, 1213 string asm, string cstr, list<dag> pattern> 1214 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1215 let OutOperandList = oops; 1216 let InOperandList = iops; 1217 let AsmString = asm; 1218 let Pattern = pattern; 1219 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1220 let DecoderNamespace = "Thumb"; 1221} 1222 1223class T2I<dag oops, dag iops, InstrItinClass itin, 1224 string opc, string asm, list<dag> pattern> 1225 : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>; 1226class T2Ii12<dag oops, dag iops, InstrItinClass itin, 1227 string opc, string asm, list<dag> pattern> 1228 : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>; 1229class T2Ii8<dag oops, dag iops, InstrItinClass itin, 1230 string opc, string asm, list<dag> pattern> 1231 : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>; 1232class T2Iso<dag oops, dag iops, InstrItinClass itin, 1233 string opc, string asm, list<dag> pattern> 1234 : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>; 1235class T2Ipc<dag oops, dag iops, InstrItinClass itin, 1236 string opc, string asm, list<dag> pattern> 1237 : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>; 1238class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin, 1239 string opc, string asm, string cstr, list<dag> pattern> 1240 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr, 1241 pattern> { 1242 bits<4> Rt; 1243 bits<4> Rt2; 1244 bits<13> addr; 1245 let Inst{31-25} = 0b1110100; 1246 let Inst{24} = P; 1247 let Inst{23} = addr{8}; 1248 let Inst{22} = 1; 1249 let Inst{21} = W; 1250 let Inst{20} = isLoad; 1251 let Inst{19-16} = addr{12-9}; 1252 let Inst{15-12} = Rt{3-0}; 1253 let Inst{11-8} = Rt2{3-0}; 1254 let Inst{7-0} = addr{7-0}; 1255} 1256class T2Ii8s4post<bit P, bit W, bit isLoad, dag oops, dag iops, 1257 InstrItinClass itin, string opc, string asm, string cstr, 1258 list<dag> pattern> 1259 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr, 1260 pattern> { 1261 bits<4> Rt; 1262 bits<4> Rt2; 1263 bits<4> addr; 1264 bits<9> imm; 1265 let Inst{31-25} = 0b1110100; 1266 let Inst{24} = P; 1267 let Inst{23} = imm{8}; 1268 let Inst{22} = 1; 1269 let Inst{21} = W; 1270 let Inst{20} = isLoad; 1271 let Inst{19-16} = addr; 1272 let Inst{15-12} = Rt{3-0}; 1273 let Inst{11-8} = Rt2{3-0}; 1274 let Inst{7-0} = imm{7-0}; 1275} 1276 1277class T2sI<dag oops, dag iops, InstrItinClass itin, 1278 string opc, string asm, list<dag> pattern> 1279 : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>; 1280 1281class T2XI<dag oops, dag iops, InstrItinClass itin, 1282 string asm, list<dag> pattern> 1283 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>; 1284class T2JTI<dag oops, dag iops, InstrItinClass itin, 1285 string asm, list<dag> pattern> 1286 : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>; 1287 1288// Move to/from coprocessor instructions 1289class T2Cop<bits<4> opc, dag oops, dag iops, string opcstr, string asm, 1290 list<dag> pattern> 1291 : T2I <oops, iops, NoItinerary, opcstr, asm, pattern>, Requires<[IsThumb2]> { 1292 let Inst{31-28} = opc; 1293} 1294 1295// Two-address instructions 1296class T2XIt<dag oops, dag iops, InstrItinClass itin, 1297 string asm, string cstr, list<dag> pattern> 1298 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>; 1299 1300// T2Ipreldst - Thumb2 pre-indexed load / store instructions. 1301class T2Ipreldst<bit signed, bits<2> opcod, bit load, bit pre, 1302 dag oops, dag iops, 1303 AddrMode am, IndexMode im, InstrItinClass itin, 1304 string opc, string asm, string cstr, list<dag> pattern> 1305 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> { 1306 let OutOperandList = oops; 1307 let InOperandList = !con(iops, (ins pred:$p)); 1308 let AsmString = !strconcat(opc, "${p}", asm); 1309 let Pattern = pattern; 1310 list<Predicate> Predicates = [IsThumb2]; 1311 let DecoderNamespace = "Thumb2"; 1312 1313 bits<4> Rt; 1314 bits<13> addr; 1315 let Inst{31-27} = 0b11111; 1316 let Inst{26-25} = 0b00; 1317 let Inst{24} = signed; 1318 let Inst{23} = 0; 1319 let Inst{22-21} = opcod; 1320 let Inst{20} = load; 1321 let Inst{19-16} = addr{12-9}; 1322 let Inst{15-12} = Rt{3-0}; 1323 let Inst{11} = 1; 1324 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1325 let Inst{10} = pre; // The P bit. 1326 let Inst{9} = addr{8}; // Sign bit 1327 let Inst{8} = 1; // The W bit. 1328 let Inst{7-0} = addr{7-0}; 1329 1330 let DecoderMethod = "DecodeT2LdStPre"; 1331} 1332 1333// T2Ipostldst - Thumb2 post-indexed load / store instructions. 1334class T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre, 1335 dag oops, dag iops, 1336 AddrMode am, IndexMode im, InstrItinClass itin, 1337 string opc, string asm, string cstr, list<dag> pattern> 1338 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> { 1339 let OutOperandList = oops; 1340 let InOperandList = !con(iops, (ins pred:$p)); 1341 let AsmString = !strconcat(opc, "${p}", asm); 1342 let Pattern = pattern; 1343 list<Predicate> Predicates = [IsThumb2]; 1344 let DecoderNamespace = "Thumb2"; 1345 1346 bits<4> Rt; 1347 bits<4> Rn; 1348 bits<9> offset; 1349 let Inst{31-27} = 0b11111; 1350 let Inst{26-25} = 0b00; 1351 let Inst{24} = signed; 1352 let Inst{23} = 0; 1353 let Inst{22-21} = opcod; 1354 let Inst{20} = load; 1355 let Inst{19-16} = Rn; 1356 let Inst{15-12} = Rt{3-0}; 1357 let Inst{11} = 1; 1358 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1359 let Inst{10} = pre; // The P bit. 1360 let Inst{9} = offset{8}; // Sign bit 1361 let Inst{8} = 1; // The W bit. 1362 let Inst{7-0} = offset{7-0}; 1363 1364 let DecoderMethod = "DecodeT2LdStPre"; 1365} 1366 1367// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 1368class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 1369 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T]; 1370} 1371 1372// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 1373class T1Pat<dag pattern, dag result> : Pat<pattern, result> { 1374 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1375} 1376 1377// T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode. 1378class T2v6Pat<dag pattern, dag result> : Pat<pattern, result> { 1379 list<Predicate> Predicates = [IsThumb2, HasV6T2]; 1380} 1381 1382// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 1383class T2Pat<dag pattern, dag result> : Pat<pattern, result> { 1384 list<Predicate> Predicates = [IsThumb2]; 1385} 1386 1387//===----------------------------------------------------------------------===// 1388 1389//===----------------------------------------------------------------------===// 1390// ARM VFP Instruction templates. 1391// 1392 1393// Almost all VFP instructions are predicable. 1394class VFPI<dag oops, dag iops, AddrMode am, int sz, 1395 IndexMode im, Format f, InstrItinClass itin, 1396 string opc, string asm, string cstr, list<dag> pattern> 1397 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1398 bits<4> p; 1399 let Inst{31-28} = p; 1400 let OutOperandList = oops; 1401 let InOperandList = !con(iops, (ins pred:$p)); 1402 let AsmString = !strconcat(opc, "${p}", asm); 1403 let Pattern = pattern; 1404 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1405 let DecoderNamespace = "VFP"; 1406 list<Predicate> Predicates = [HasVFP2]; 1407} 1408 1409// Special cases 1410class VFPXI<dag oops, dag iops, AddrMode am, int sz, 1411 IndexMode im, Format f, InstrItinClass itin, 1412 string asm, string cstr, list<dag> pattern> 1413 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1414 bits<4> p; 1415 let Inst{31-28} = p; 1416 let OutOperandList = oops; 1417 let InOperandList = iops; 1418 let AsmString = asm; 1419 let Pattern = pattern; 1420 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1421 let DecoderNamespace = "VFP"; 1422 list<Predicate> Predicates = [HasVFP2]; 1423} 1424 1425class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, 1426 string opc, string asm, list<dag> pattern> 1427 : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 1428 opc, asm, "", pattern> { 1429 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1430} 1431 1432// ARM VFP addrmode5 loads and stores 1433class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1434 InstrItinClass itin, 1435 string opc, string asm, list<dag> pattern> 1436 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone, 1437 VFPLdStFrm, itin, opc, asm, "", pattern> { 1438 // Instruction operands. 1439 bits<5> Dd; 1440 bits<13> addr; 1441 1442 // Encode instruction operands. 1443 let Inst{23} = addr{8}; // U (add = (U == '1')) 1444 let Inst{22} = Dd{4}; 1445 let Inst{19-16} = addr{12-9}; // Rn 1446 let Inst{15-12} = Dd{3-0}; 1447 let Inst{7-0} = addr{7-0}; // imm8 1448 1449 let Inst{27-24} = opcod1; 1450 let Inst{21-20} = opcod2; 1451 let Inst{11-9} = 0b101; 1452 let Inst{8} = 1; // Double precision 1453 1454 // Loads & stores operate on both NEON and VFP pipelines. 1455 let D = VFPNeonDomain; 1456} 1457 1458class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1459 InstrItinClass itin, 1460 string opc, string asm, list<dag> pattern> 1461 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone, 1462 VFPLdStFrm, itin, opc, asm, "", pattern> { 1463 // Instruction operands. 1464 bits<5> Sd; 1465 bits<13> addr; 1466 1467 // Encode instruction operands. 1468 let Inst{23} = addr{8}; // U (add = (U == '1')) 1469 let Inst{22} = Sd{0}; 1470 let Inst{19-16} = addr{12-9}; // Rn 1471 let Inst{15-12} = Sd{4-1}; 1472 let Inst{7-0} = addr{7-0}; // imm8 1473 1474 let Inst{27-24} = opcod1; 1475 let Inst{21-20} = opcod2; 1476 let Inst{11-9} = 0b101; 1477 let Inst{8} = 0; // Single precision 1478 1479 // Loads & stores operate on both NEON and VFP pipelines. 1480 let D = VFPNeonDomain; 1481} 1482 1483// VFP Load / store multiple pseudo instructions. 1484class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr, 1485 list<dag> pattern> 1486 : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain, 1487 cstr, itin> { 1488 let OutOperandList = oops; 1489 let InOperandList = !con(iops, (ins pred:$p)); 1490 let Pattern = pattern; 1491 list<Predicate> Predicates = [HasVFP2]; 1492} 1493 1494// Load / store multiple 1495 1496// Unknown precision 1497class AXXI4<dag oops, dag iops, IndexMode im, 1498 string asm, string cstr, list<dag> pattern> 1499 : VFPXI<oops, iops, AddrMode4, 4, im, 1500 VFPLdStFrm, NoItinerary, asm, cstr, pattern> { 1501 // Instruction operands. 1502 bits<4> Rn; 1503 bits<13> regs; 1504 1505 // Encode instruction operands. 1506 let Inst{19-16} = Rn; 1507 let Inst{22} = 0; 1508 let Inst{15-12} = regs{11-8}; 1509 let Inst{7-1} = regs{7-1}; 1510 1511 let Inst{27-25} = 0b110; 1512 let Inst{11-8} = 0b1011; 1513 let Inst{0} = 1; 1514} 1515 1516// Double precision 1517class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1518 string asm, string cstr, list<dag> pattern> 1519 : VFPXI<oops, iops, AddrMode4, 4, im, 1520 VFPLdStMulFrm, itin, asm, cstr, pattern> { 1521 // Instruction operands. 1522 bits<4> Rn; 1523 bits<13> regs; 1524 1525 // Encode instruction operands. 1526 let Inst{19-16} = Rn; 1527 let Inst{22} = regs{12}; 1528 let Inst{15-12} = regs{11-8}; 1529 let Inst{7-1} = regs{7-1}; 1530 1531 let Inst{27-25} = 0b110; 1532 let Inst{11-9} = 0b101; 1533 let Inst{8} = 1; // Double precision 1534 let Inst{0} = 0; 1535} 1536 1537// Single Precision 1538class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1539 string asm, string cstr, list<dag> pattern> 1540 : VFPXI<oops, iops, AddrMode4, 4, im, 1541 VFPLdStMulFrm, itin, asm, cstr, pattern> { 1542 // Instruction operands. 1543 bits<4> Rn; 1544 bits<13> regs; 1545 1546 // Encode instruction operands. 1547 let Inst{19-16} = Rn; 1548 let Inst{22} = regs{8}; 1549 let Inst{15-12} = regs{12-9}; 1550 let Inst{7-0} = regs{7-0}; 1551 1552 let Inst{27-25} = 0b110; 1553 let Inst{11-9} = 0b101; 1554 let Inst{8} = 0; // Single precision 1555} 1556 1557// Double precision, unary 1558class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1559 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1560 string asm, list<dag> pattern> 1561 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1562 // Instruction operands. 1563 bits<5> Dd; 1564 bits<5> Dm; 1565 1566 // Encode instruction operands. 1567 let Inst{3-0} = Dm{3-0}; 1568 let Inst{5} = Dm{4}; 1569 let Inst{15-12} = Dd{3-0}; 1570 let Inst{22} = Dd{4}; 1571 1572 let Inst{27-23} = opcod1; 1573 let Inst{21-20} = opcod2; 1574 let Inst{19-16} = opcod3; 1575 let Inst{11-9} = 0b101; 1576 let Inst{8} = 1; // Double precision 1577 let Inst{7-6} = opcod4; 1578 let Inst{4} = opcod5; 1579 1580 let Predicates = [HasVFP2, HasDPVFP]; 1581} 1582 1583// Double precision, unary, not-predicated 1584class ADuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1585 bit opcod5, dag oops, dag iops, InstrItinClass itin, 1586 string asm, list<dag> pattern> 1587 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, VFPUnaryFrm, itin, asm, "", pattern> { 1588 // Instruction operands. 1589 bits<5> Dd; 1590 bits<5> Dm; 1591 1592 let Inst{31-28} = 0b1111; 1593 1594 // Encode instruction operands. 1595 let Inst{3-0} = Dm{3-0}; 1596 let Inst{5} = Dm{4}; 1597 let Inst{15-12} = Dd{3-0}; 1598 let Inst{22} = Dd{4}; 1599 1600 let Inst{27-23} = opcod1; 1601 let Inst{21-20} = opcod2; 1602 let Inst{19-16} = opcod3; 1603 let Inst{11-9} = 0b101; 1604 let Inst{8} = 1; // Double precision 1605 let Inst{7-6} = opcod4; 1606 let Inst{4} = opcod5; 1607} 1608 1609// Double precision, binary 1610class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1611 dag iops, InstrItinClass itin, string opc, string asm, 1612 list<dag> pattern> 1613 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1614 // Instruction operands. 1615 bits<5> Dd; 1616 bits<5> Dn; 1617 bits<5> Dm; 1618 1619 // Encode instruction operands. 1620 let Inst{3-0} = Dm{3-0}; 1621 let Inst{5} = Dm{4}; 1622 let Inst{19-16} = Dn{3-0}; 1623 let Inst{7} = Dn{4}; 1624 let Inst{15-12} = Dd{3-0}; 1625 let Inst{22} = Dd{4}; 1626 1627 let Inst{27-23} = opcod1; 1628 let Inst{21-20} = opcod2; 1629 let Inst{11-9} = 0b101; 1630 let Inst{8} = 1; // Double precision 1631 let Inst{6} = op6; 1632 let Inst{4} = op4; 1633 1634 let Predicates = [HasVFP2, HasDPVFP]; 1635} 1636 1637// FP, binary, not predicated 1638class ADbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops, 1639 InstrItinClass itin, string asm, list<dag> pattern> 1640 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, VFPBinaryFrm, itin, 1641 asm, "", pattern> 1642{ 1643 // Instruction operands. 1644 bits<5> Dd; 1645 bits<5> Dn; 1646 bits<5> Dm; 1647 1648 let Inst{31-28} = 0b1111; 1649 1650 // Encode instruction operands. 1651 let Inst{3-0} = Dm{3-0}; 1652 let Inst{5} = Dm{4}; 1653 let Inst{19-16} = Dn{3-0}; 1654 let Inst{7} = Dn{4}; 1655 let Inst{15-12} = Dd{3-0}; 1656 let Inst{22} = Dd{4}; 1657 1658 let Inst{27-23} = opcod1; 1659 let Inst{21-20} = opcod2; 1660 let Inst{11-9} = 0b101; 1661 let Inst{8} = 1; // double precision 1662 let Inst{6} = opcod3; 1663 let Inst{4} = 0; 1664 1665 let Predicates = [HasVFP2, HasDPVFP]; 1666} 1667 1668// Single precision, unary, predicated 1669class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1670 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1671 string asm, list<dag> pattern> 1672 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1673 // Instruction operands. 1674 bits<5> Sd; 1675 bits<5> Sm; 1676 1677 // Encode instruction operands. 1678 let Inst{3-0} = Sm{4-1}; 1679 let Inst{5} = Sm{0}; 1680 let Inst{15-12} = Sd{4-1}; 1681 let Inst{22} = Sd{0}; 1682 1683 let Inst{27-23} = opcod1; 1684 let Inst{21-20} = opcod2; 1685 let Inst{19-16} = opcod3; 1686 let Inst{11-9} = 0b101; 1687 let Inst{8} = 0; // Single precision 1688 let Inst{7-6} = opcod4; 1689 let Inst{4} = opcod5; 1690} 1691 1692// Single precision, unary, non-predicated 1693class ASuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1694 bit opcod5, dag oops, dag iops, InstrItinClass itin, 1695 string asm, list<dag> pattern> 1696 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, 1697 VFPUnaryFrm, itin, asm, "", pattern> { 1698 // Instruction operands. 1699 bits<5> Sd; 1700 bits<5> Sm; 1701 1702 let Inst{31-28} = 0b1111; 1703 1704 // Encode instruction operands. 1705 let Inst{3-0} = Sm{4-1}; 1706 let Inst{5} = Sm{0}; 1707 let Inst{15-12} = Sd{4-1}; 1708 let Inst{22} = Sd{0}; 1709 1710 let Inst{27-23} = opcod1; 1711 let Inst{21-20} = opcod2; 1712 let Inst{19-16} = opcod3; 1713 let Inst{11-9} = 0b101; 1714 let Inst{8} = 0; // Single precision 1715 let Inst{7-6} = opcod4; 1716 let Inst{4} = opcod5; 1717} 1718 1719// Single precision unary, if no NEON. Same as ASuI except not available if 1720// NEON is enabled. 1721class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1722 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1723 string asm, list<dag> pattern> 1724 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm, 1725 pattern> { 1726 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1727} 1728 1729// Single precision, binary 1730class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1731 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1732 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1733 // Instruction operands. 1734 bits<5> Sd; 1735 bits<5> Sn; 1736 bits<5> Sm; 1737 1738 // Encode instruction operands. 1739 let Inst{3-0} = Sm{4-1}; 1740 let Inst{5} = Sm{0}; 1741 let Inst{19-16} = Sn{4-1}; 1742 let Inst{7} = Sn{0}; 1743 let Inst{15-12} = Sd{4-1}; 1744 let Inst{22} = Sd{0}; 1745 1746 let Inst{27-23} = opcod1; 1747 let Inst{21-20} = opcod2; 1748 let Inst{11-9} = 0b101; 1749 let Inst{8} = 0; // Single precision 1750 let Inst{6} = op6; 1751 let Inst{4} = op4; 1752} 1753 1754// Single precision, binary, not predicated 1755class ASbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops, 1756 InstrItinClass itin, string asm, list<dag> pattern> 1757 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, 1758 VFPBinaryFrm, itin, asm, "", pattern> 1759{ 1760 // Instruction operands. 1761 bits<5> Sd; 1762 bits<5> Sn; 1763 bits<5> Sm; 1764 1765 let Inst{31-28} = 0b1111; 1766 1767 // Encode instruction operands. 1768 let Inst{3-0} = Sm{4-1}; 1769 let Inst{5} = Sm{0}; 1770 let Inst{19-16} = Sn{4-1}; 1771 let Inst{7} = Sn{0}; 1772 let Inst{15-12} = Sd{4-1}; 1773 let Inst{22} = Sd{0}; 1774 1775 let Inst{27-23} = opcod1; 1776 let Inst{21-20} = opcod2; 1777 let Inst{11-9} = 0b101; 1778 let Inst{8} = 0; // Single precision 1779 let Inst{6} = opcod3; 1780 let Inst{4} = 0; 1781} 1782 1783// Single precision binary, if no NEON. Same as ASbI except not available if 1784// NEON is enabled. 1785class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1786 dag iops, InstrItinClass itin, string opc, string asm, 1787 list<dag> pattern> 1788 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1789 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1790 1791 // Instruction operands. 1792 bits<5> Sd; 1793 bits<5> Sn; 1794 bits<5> Sm; 1795 1796 // Encode instruction operands. 1797 let Inst{3-0} = Sm{4-1}; 1798 let Inst{5} = Sm{0}; 1799 let Inst{19-16} = Sn{4-1}; 1800 let Inst{7} = Sn{0}; 1801 let Inst{15-12} = Sd{4-1}; 1802 let Inst{22} = Sd{0}; 1803} 1804 1805// VFP conversion instructions 1806class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1807 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1808 list<dag> pattern> 1809 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { 1810 let Inst{27-23} = opcod1; 1811 let Inst{21-20} = opcod2; 1812 let Inst{19-16} = opcod3; 1813 let Inst{11-8} = opcod4; 1814 let Inst{6} = 1; 1815 let Inst{4} = 0; 1816} 1817 1818// VFP conversion between floating-point and fixed-point 1819class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 1820 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1821 list<dag> pattern> 1822 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { 1823 bits<5> fbits; 1824 // size (fixed-point number): sx == 0 ? 16 : 32 1825 let Inst{7} = op5; // sx 1826 let Inst{5} = fbits{0}; 1827 let Inst{3-0} = fbits{4-1}; 1828} 1829 1830// VFP conversion instructions, if no NEON 1831class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1832 dag oops, dag iops, InstrItinClass itin, 1833 string opc, string asm, list<dag> pattern> 1834 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1835 pattern> { 1836 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1837} 1838 1839class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1840 InstrItinClass itin, 1841 string opc, string asm, list<dag> pattern> 1842 : VFPAI<oops, iops, f, itin, opc, asm, pattern> { 1843 let Inst{27-20} = opcod1; 1844 let Inst{11-8} = opcod2; 1845 let Inst{4} = 1; 1846} 1847 1848class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1849 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1850 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; 1851 1852class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1853 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1854 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; 1855 1856class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1857 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1858 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; 1859 1860class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1861 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1862 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; 1863 1864//===----------------------------------------------------------------------===// 1865 1866//===----------------------------------------------------------------------===// 1867// ARM NEON Instruction templates. 1868// 1869 1870class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1871 InstrItinClass itin, string opc, string dt, string asm, string cstr, 1872 list<dag> pattern> 1873 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> { 1874 let OutOperandList = oops; 1875 let InOperandList = !con(iops, (ins pred:$p)); 1876 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1877 let Pattern = pattern; 1878 list<Predicate> Predicates = [HasNEON]; 1879 let DecoderNamespace = "NEON"; 1880} 1881 1882// Same as NeonI except it does not have a "data type" specifier. 1883class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1884 InstrItinClass itin, string opc, string asm, string cstr, 1885 list<dag> pattern> 1886 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> { 1887 let OutOperandList = oops; 1888 let InOperandList = !con(iops, (ins pred:$p)); 1889 let AsmString = !strconcat(opc, "${p}", "\t", asm); 1890 let Pattern = pattern; 1891 list<Predicate> Predicates = [HasNEON]; 1892 let DecoderNamespace = "NEON"; 1893} 1894 1895// Same as NeonI except it is not predicated 1896class NeonInp<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1897 InstrItinClass itin, string opc, string dt, string asm, string cstr, 1898 list<dag> pattern> 1899 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> { 1900 let OutOperandList = oops; 1901 let InOperandList = iops; 1902 let AsmString = !strconcat(opc, ".", dt, "\t", asm); 1903 let Pattern = pattern; 1904 list<Predicate> Predicates = [HasNEON]; 1905 let DecoderNamespace = "NEON"; 1906 1907 let Inst{31-28} = 0b1111; 1908} 1909 1910class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1911 dag oops, dag iops, InstrItinClass itin, 1912 string opc, string dt, string asm, string cstr, list<dag> pattern> 1913 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm, 1914 cstr, pattern> { 1915 let Inst{31-24} = 0b11110100; 1916 let Inst{23} = op23; 1917 let Inst{21-20} = op21_20; 1918 let Inst{11-8} = op11_8; 1919 let Inst{7-4} = op7_4; 1920 1921 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder"; 1922 let DecoderNamespace = "NEONLoadStore"; 1923 1924 bits<5> Vd; 1925 bits<6> Rn; 1926 bits<4> Rm; 1927 1928 let Inst{22} = Vd{4}; 1929 let Inst{15-12} = Vd{3-0}; 1930 let Inst{19-16} = Rn{3-0}; 1931 let Inst{3-0} = Rm{3-0}; 1932} 1933 1934class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1935 dag oops, dag iops, InstrItinClass itin, 1936 string opc, string dt, string asm, string cstr, list<dag> pattern> 1937 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc, 1938 dt, asm, cstr, pattern> { 1939 bits<3> lane; 1940} 1941 1942class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr> 1943 : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr, 1944 itin> { 1945 let OutOperandList = oops; 1946 let InOperandList = !con(iops, (ins pred:$p)); 1947 list<Predicate> Predicates = [HasNEON]; 1948} 1949 1950class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr, 1951 list<dag> pattern> 1952 : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr, 1953 itin> { 1954 let OutOperandList = oops; 1955 let InOperandList = !con(iops, (ins pred:$p)); 1956 let Pattern = pattern; 1957 list<Predicate> Predicates = [HasNEON]; 1958} 1959 1960class NDataI<dag oops, dag iops, Format f, InstrItinClass itin, 1961 string opc, string dt, string asm, string cstr, list<dag> pattern> 1962 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr, 1963 pattern> { 1964 let Inst{31-25} = 0b1111001; 1965 let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1966 let DecoderNamespace = "NEONData"; 1967} 1968 1969class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin, 1970 string opc, string asm, string cstr, list<dag> pattern> 1971 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm, 1972 cstr, pattern> { 1973 let Inst{31-25} = 0b1111001; 1974 let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1975 let DecoderNamespace = "NEONData"; 1976} 1977 1978// NEON "one register and a modified immediate" format. 1979class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1980 bit op5, bit op4, 1981 dag oops, dag iops, InstrItinClass itin, 1982 string opc, string dt, string asm, string cstr, 1983 list<dag> pattern> 1984 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> { 1985 let Inst{23} = op23; 1986 let Inst{21-19} = op21_19; 1987 let Inst{11-8} = op11_8; 1988 let Inst{7} = op7; 1989 let Inst{6} = op6; 1990 let Inst{5} = op5; 1991 let Inst{4} = op4; 1992 1993 // Instruction operands. 1994 bits<5> Vd; 1995 bits<13> SIMM; 1996 1997 let Inst{15-12} = Vd{3-0}; 1998 let Inst{22} = Vd{4}; 1999 let Inst{24} = SIMM{7}; 2000 let Inst{18-16} = SIMM{6-4}; 2001 let Inst{3-0} = SIMM{3-0}; 2002 let DecoderMethod = "DecodeNEONModImmInstruction"; 2003} 2004 2005// NEON 2 vector register format. 2006class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 2007 bits<5> op11_7, bit op6, bit op4, 2008 dag oops, dag iops, InstrItinClass itin, 2009 string opc, string dt, string asm, string cstr, list<dag> pattern> 2010 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> { 2011 let Inst{24-23} = op24_23; 2012 let Inst{21-20} = op21_20; 2013 let Inst{19-18} = op19_18; 2014 let Inst{17-16} = op17_16; 2015 let Inst{11-7} = op11_7; 2016 let Inst{6} = op6; 2017 let Inst{4} = op4; 2018 2019 // Instruction operands. 2020 bits<5> Vd; 2021 bits<5> Vm; 2022 2023 let Inst{15-12} = Vd{3-0}; 2024 let Inst{22} = Vd{4}; 2025 let Inst{3-0} = Vm{3-0}; 2026 let Inst{5} = Vm{4}; 2027} 2028 2029// Same as N2V but not predicated. 2030class N2Vnp<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6, 2031 dag oops, dag iops, InstrItinClass itin, string OpcodeStr, 2032 string Dt, list<dag> pattern> 2033 : NeonInp<oops, iops, AddrModeNone, IndexModeNone, N2RegFrm, itin, 2034 OpcodeStr, Dt, "$Vd, $Vm", "", pattern> { 2035 bits<5> Vd; 2036 bits<5> Vm; 2037 2038 // Encode instruction operands 2039 let Inst{22} = Vd{4}; 2040 let Inst{15-12} = Vd{3-0}; 2041 let Inst{5} = Vm{4}; 2042 let Inst{3-0} = Vm{3-0}; 2043 2044 // Encode constant bits 2045 let Inst{27-23} = 0b00111; 2046 let Inst{21-20} = 0b11; 2047 let Inst{19-18} = op19_18; 2048 let Inst{17-16} = op17_16; 2049 let Inst{11} = 0; 2050 let Inst{10-8} = op10_8; 2051 let Inst{7} = op7; 2052 let Inst{6} = op6; 2053 let Inst{4} = 0; 2054 2055 let DecoderNamespace = "NEON"; 2056} 2057 2058// Same as N2V except it doesn't have a datatype suffix. 2059class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 2060 bits<5> op11_7, bit op6, bit op4, 2061 dag oops, dag iops, InstrItinClass itin, 2062 string opc, string asm, string cstr, list<dag> pattern> 2063 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> { 2064 let Inst{24-23} = op24_23; 2065 let Inst{21-20} = op21_20; 2066 let Inst{19-18} = op19_18; 2067 let Inst{17-16} = op17_16; 2068 let Inst{11-7} = op11_7; 2069 let Inst{6} = op6; 2070 let Inst{4} = op4; 2071 2072 // Instruction operands. 2073 bits<5> Vd; 2074 bits<5> Vm; 2075 2076 let Inst{15-12} = Vd{3-0}; 2077 let Inst{22} = Vd{4}; 2078 let Inst{3-0} = Vm{3-0}; 2079 let Inst{5} = Vm{4}; 2080} 2081 2082// NEON 2 vector register with immediate. 2083class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 2084 dag oops, dag iops, Format f, InstrItinClass itin, 2085 string opc, string dt, string asm, string cstr, list<dag> pattern> 2086 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 2087 let Inst{24} = op24; 2088 let Inst{23} = op23; 2089 let Inst{11-8} = op11_8; 2090 let Inst{7} = op7; 2091 let Inst{6} = op6; 2092 let Inst{4} = op4; 2093 2094 // Instruction operands. 2095 bits<5> Vd; 2096 bits<5> Vm; 2097 bits<6> SIMM; 2098 2099 let Inst{15-12} = Vd{3-0}; 2100 let Inst{22} = Vd{4}; 2101 let Inst{3-0} = Vm{3-0}; 2102 let Inst{5} = Vm{4}; 2103 let Inst{21-16} = SIMM{5-0}; 2104} 2105 2106// NEON 3 vector register format. 2107 2108class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 2109 bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 2110 string opc, string dt, string asm, string cstr, 2111 list<dag> pattern> 2112 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 2113 let Inst{24} = op24; 2114 let Inst{23} = op23; 2115 let Inst{21-20} = op21_20; 2116 let Inst{11-8} = op11_8; 2117 let Inst{6} = op6; 2118 let Inst{4} = op4; 2119} 2120 2121class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 2122 dag oops, dag iops, Format f, InstrItinClass itin, 2123 string opc, string dt, string asm, string cstr, list<dag> pattern> 2124 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 2125 oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 2126 // Instruction operands. 2127 bits<5> Vd; 2128 bits<5> Vn; 2129 bits<5> Vm; 2130 2131 let Inst{15-12} = Vd{3-0}; 2132 let Inst{22} = Vd{4}; 2133 let Inst{19-16} = Vn{3-0}; 2134 let Inst{7} = Vn{4}; 2135 let Inst{3-0} = Vm{3-0}; 2136 let Inst{5} = Vm{4}; 2137} 2138 2139class N3Vnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6, 2140 bit op4, dag oops, dag iops,Format f, InstrItinClass itin, 2141 string OpcodeStr, string Dt, list<dag> pattern> 2142 : NeonInp<oops, iops, AddrModeNone, IndexModeNone, f, itin, OpcodeStr, 2143 Dt, "$Vd, $Vn, $Vm", "", pattern> { 2144 bits<5> Vd; 2145 bits<5> Vn; 2146 bits<5> Vm; 2147 2148 // Encode instruction operands 2149 let Inst{22} = Vd{4}; 2150 let Inst{15-12} = Vd{3-0}; 2151 let Inst{19-16} = Vn{3-0}; 2152 let Inst{7} = Vn{4}; 2153 let Inst{5} = Vm{4}; 2154 let Inst{3-0} = Vm{3-0}; 2155 2156 // Encode constant bits 2157 let Inst{27-23} = op27_23; 2158 let Inst{21-20} = op21_20; 2159 let Inst{11-8} = op11_8; 2160 let Inst{6} = op6; 2161 let Inst{4} = op4; 2162} 2163 2164class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 2165 bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 2166 string opc, string dt, string asm, string cstr, 2167 list<dag> pattern> 2168 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 2169 oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 2170 2171 // Instruction operands. 2172 bits<5> Vd; 2173 bits<5> Vn; 2174 bits<5> Vm; 2175 bit lane; 2176 2177 let Inst{15-12} = Vd{3-0}; 2178 let Inst{22} = Vd{4}; 2179 let Inst{19-16} = Vn{3-0}; 2180 let Inst{7} = Vn{4}; 2181 let Inst{3-0} = Vm{3-0}; 2182 let Inst{5} = lane; 2183} 2184 2185class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 2186 bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 2187 string opc, string dt, string asm, string cstr, 2188 list<dag> pattern> 2189 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 2190 oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 2191 2192 // Instruction operands. 2193 bits<5> Vd; 2194 bits<5> Vn; 2195 bits<5> Vm; 2196 bits<2> lane; 2197 2198 let Inst{15-12} = Vd{3-0}; 2199 let Inst{22} = Vd{4}; 2200 let Inst{19-16} = Vn{3-0}; 2201 let Inst{7} = Vn{4}; 2202 let Inst{2-0} = Vm{2-0}; 2203 let Inst{5} = lane{1}; 2204 let Inst{3} = lane{0}; 2205} 2206 2207// Same as N3V except it doesn't have a data type suffix. 2208class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 2209 bit op4, 2210 dag oops, dag iops, Format f, InstrItinClass itin, 2211 string opc, string asm, string cstr, list<dag> pattern> 2212 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> { 2213 let Inst{24} = op24; 2214 let Inst{23} = op23; 2215 let Inst{21-20} = op21_20; 2216 let Inst{11-8} = op11_8; 2217 let Inst{6} = op6; 2218 let Inst{4} = op4; 2219 2220 // Instruction operands. 2221 bits<5> Vd; 2222 bits<5> Vn; 2223 bits<5> Vm; 2224 2225 let Inst{15-12} = Vd{3-0}; 2226 let Inst{22} = Vd{4}; 2227 let Inst{19-16} = Vn{3-0}; 2228 let Inst{7} = Vn{4}; 2229 let Inst{3-0} = Vm{3-0}; 2230 let Inst{5} = Vm{4}; 2231} 2232 2233// NEON VMOVs between scalar and core registers. 2234class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2235 dag oops, dag iops, Format f, InstrItinClass itin, 2236 string opc, string dt, string asm, list<dag> pattern> 2237 : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain, 2238 "", itin> { 2239 let Inst{27-20} = opcod1; 2240 let Inst{11-8} = opcod2; 2241 let Inst{6-5} = opcod3; 2242 let Inst{4} = 1; 2243 // A8.6.303, A8.6.328, A8.6.329 2244 let Inst{3-0} = 0b0000; 2245 2246 let OutOperandList = oops; 2247 let InOperandList = !con(iops, (ins pred:$p)); 2248 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 2249 let Pattern = pattern; 2250 list<Predicate> Predicates = [HasNEON]; 2251 2252 let PostEncoderMethod = "NEONThumb2DupPostEncoder"; 2253 let DecoderNamespace = "NEONDup"; 2254 2255 bits<5> V; 2256 bits<4> R; 2257 bits<4> p; 2258 bits<4> lane; 2259 2260 let Inst{31-28} = p{3-0}; 2261 let Inst{7} = V{4}; 2262 let Inst{19-16} = V{3-0}; 2263 let Inst{15-12} = R{3-0}; 2264} 2265class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2266 dag oops, dag iops, InstrItinClass itin, 2267 string opc, string dt, string asm, list<dag> pattern> 2268 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin, 2269 opc, dt, asm, pattern>; 2270class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2271 dag oops, dag iops, InstrItinClass itin, 2272 string opc, string dt, string asm, list<dag> pattern> 2273 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin, 2274 opc, dt, asm, pattern>; 2275class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2276 dag oops, dag iops, InstrItinClass itin, 2277 string opc, string dt, string asm, list<dag> pattern> 2278 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin, 2279 opc, dt, asm, pattern>; 2280 2281// Vector Duplicate Lane (from scalar to all elements) 2282class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops, 2283 InstrItinClass itin, string opc, string dt, string asm, 2284 list<dag> pattern> 2285 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> { 2286 let Inst{24-23} = 0b11; 2287 let Inst{21-20} = 0b11; 2288 let Inst{19-16} = op19_16; 2289 let Inst{11-7} = 0b11000; 2290 let Inst{6} = op6; 2291 let Inst{4} = 0; 2292 2293 bits<5> Vd; 2294 bits<5> Vm; 2295 2296 let Inst{22} = Vd{4}; 2297 let Inst{15-12} = Vd{3-0}; 2298 let Inst{5} = Vm{4}; 2299 let Inst{3-0} = Vm{3-0}; 2300} 2301 2302// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON 2303// for single-precision FP. 2304class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { 2305 list<Predicate> Predicates = [HasNEON,UseNEONForFP]; 2306} 2307 2308// VFP/NEON Instruction aliases for type suffices. 2309class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> : 2310 InstAlias<!strconcat(opc, dt, "\t", asm), Result>, Requires<[HasVFP2]>; 2311 2312multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result> { 2313 def : VFPDataTypeInstAlias<opc, ".8", asm, Result>; 2314 def : VFPDataTypeInstAlias<opc, ".16", asm, Result>; 2315 def : VFPDataTypeInstAlias<opc, ".32", asm, Result>; 2316 def : VFPDataTypeInstAlias<opc, ".64", asm, Result>; 2317} 2318 2319multiclass NEONDTAnyInstAlias<string opc, string asm, dag Result> { 2320 let Predicates = [HasNEON] in { 2321 def : VFPDataTypeInstAlias<opc, ".8", asm, Result>; 2322 def : VFPDataTypeInstAlias<opc, ".16", asm, Result>; 2323 def : VFPDataTypeInstAlias<opc, ".32", asm, Result>; 2324 def : VFPDataTypeInstAlias<opc, ".64", asm, Result>; 2325} 2326} 2327 2328// The same alias classes using AsmPseudo instead, for the more complex 2329// stuff in NEON that InstAlias can't quite handle. 2330// Note that we can't use anonymous defm references here like we can 2331// above, as we care about the ultimate instruction enum names generated, unlike 2332// for instalias defs. 2333class NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> : 2334 AsmPseudoInst<!strconcat(opc, dt, "\t", asm), iops>, Requires<[HasNEON]>; 2335 2336// Data type suffix token aliases. Implements Table A7-3 in the ARM ARM. 2337def : TokenAlias<".s8", ".i8">; 2338def : TokenAlias<".u8", ".i8">; 2339def : TokenAlias<".s16", ".i16">; 2340def : TokenAlias<".u16", ".i16">; 2341def : TokenAlias<".s32", ".i32">; 2342def : TokenAlias<".u32", ".i32">; 2343def : TokenAlias<".s64", ".i64">; 2344def : TokenAlias<".u64", ".i64">; 2345 2346def : TokenAlias<".i8", ".8">; 2347def : TokenAlias<".i16", ".16">; 2348def : TokenAlias<".i32", ".32">; 2349def : TokenAlias<".i64", ".64">; 2350 2351def : TokenAlias<".p8", ".8">; 2352def : TokenAlias<".p16", ".16">; 2353 2354def : TokenAlias<".f32", ".32">; 2355def : TokenAlias<".f64", ".64">; 2356def : TokenAlias<".f", ".f32">; 2357def : TokenAlias<".d", ".f64">; 2358