ARMInstrFormats.td revision 221345
11553Srgrimes//===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=// 274532Sru// 31553Srgrimes// The LLVM Compiler Infrastructure 480029Sobrien// 580029Sobrien// This file is distributed under the University of Illinois Open Source 61553Srgrimes// License. See LICENSE.TXT for details. 780029Sobrien// 81553Srgrimes//===----------------------------------------------------------------------===// 983391Sru 1080029Sobrien//===----------------------------------------------------------------------===// 111553Srgrimes// 12189090Sed// ARM Instruction Format Definitions. 13189090Sed// 141553Srgrimes 151553Srgrimes// Format specifies the encoding used by the instruction. This is part of the 16// ad-hoc solution used to emit machine instruction encodings by our machine 17// code emitter. 18class Format<bits<6> val> { 19 bits<6> Value = val; 20} 21 22def Pseudo : Format<0>; 23def MulFrm : Format<1>; 24def BrFrm : Format<2>; 25def BrMiscFrm : Format<3>; 26 27def DPFrm : Format<4>; 28def DPSoRegFrm : Format<5>; 29 30def LdFrm : Format<6>; 31def StFrm : Format<7>; 32def LdMiscFrm : Format<8>; 33def StMiscFrm : Format<9>; 34def LdStMulFrm : Format<10>; 35 36def LdStExFrm : Format<11>; 37 38def ArithMiscFrm : Format<12>; 39def SatFrm : Format<13>; 40def ExtFrm : Format<14>; 41 42def VFPUnaryFrm : Format<15>; 43def VFPBinaryFrm : Format<16>; 44def VFPConv1Frm : Format<17>; 45def VFPConv2Frm : Format<18>; 46def VFPConv3Frm : Format<19>; 47def VFPConv4Frm : Format<20>; 48def VFPConv5Frm : Format<21>; 49def VFPLdStFrm : Format<22>; 50def VFPLdStMulFrm : Format<23>; 51def VFPMiscFrm : Format<24>; 52 53def ThumbFrm : Format<25>; 54def MiscFrm : Format<26>; 55 56def NGetLnFrm : Format<27>; 57def NSetLnFrm : Format<28>; 58def NDupFrm : Format<29>; 59def NLdStFrm : Format<30>; 60def N1RegModImmFrm: Format<31>; 61def N2RegFrm : Format<32>; 62def NVCVTFrm : Format<33>; 63def NVDupLnFrm : Format<34>; 64def N2RegVShLFrm : Format<35>; 65def N2RegVShRFrm : Format<36>; 66def N3RegFrm : Format<37>; 67def N3RegVShFrm : Format<38>; 68def NVExtFrm : Format<39>; 69def NVMulSLFrm : Format<40>; 70def NVTBLFrm : Format<41>; 71 72// Misc flags. 73 74// The instruction has an Rn register operand. 75// UnaryDP - Indicates this is a unary data processing instruction, i.e. 76// it doesn't have a Rn operand. 77class UnaryDP { bit isUnaryDataProc = 1; } 78 79// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 80// a 16-bit Thumb instruction if certain conditions are met. 81class Xform16Bit { bit canXformTo16Bit = 1; } 82 83//===----------------------------------------------------------------------===// 84// ARM Instruction flags. These need to match ARMBaseInstrInfo.h. 85// 86 87// FIXME: Once the JIT is MC-ized, these can go away. 88// Addressing mode. 89class AddrMode<bits<5> val> { 90 bits<5> Value = val; 91} 92def AddrModeNone : AddrMode<0>; 93def AddrMode1 : AddrMode<1>; 94def AddrMode2 : AddrMode<2>; 95def AddrMode3 : AddrMode<3>; 96def AddrMode4 : AddrMode<4>; 97def AddrMode5 : AddrMode<5>; 98def AddrMode6 : AddrMode<6>; 99def AddrModeT1_1 : AddrMode<7>; 100def AddrModeT1_2 : AddrMode<8>; 101def AddrModeT1_4 : AddrMode<9>; 102def AddrModeT1_s : AddrMode<10>; 103def AddrModeT2_i12 : AddrMode<11>; 104def AddrModeT2_i8 : AddrMode<12>; 105def AddrModeT2_so : AddrMode<13>; 106def AddrModeT2_pc : AddrMode<14>; 107def AddrModeT2_i8s4 : AddrMode<15>; 108def AddrMode_i12 : AddrMode<16>; 109 110// Instruction size. 111class SizeFlagVal<bits<3> val> { 112 bits<3> Value = val; 113} 114def SizeInvalid : SizeFlagVal<0>; // Unset. 115def SizeSpecial : SizeFlagVal<1>; // Pseudo or special. 116def Size8Bytes : SizeFlagVal<2>; 117def Size4Bytes : SizeFlagVal<3>; 118def Size2Bytes : SizeFlagVal<4>; 119 120// Load / store index mode. 121class IndexMode<bits<2> val> { 122 bits<2> Value = val; 123} 124def IndexModeNone : IndexMode<0>; 125def IndexModePre : IndexMode<1>; 126def IndexModePost : IndexMode<2>; 127def IndexModeUpd : IndexMode<3>; 128 129// Instruction execution domain. 130class Domain<bits<3> val> { 131 bits<3> Value = val; 132} 133def GenericDomain : Domain<0>; 134def VFPDomain : Domain<1>; // Instructions in VFP domain only 135def NeonDomain : Domain<2>; // Instructions in Neon domain only 136def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains 137def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8 138 139//===----------------------------------------------------------------------===// 140// ARM special operands. 141// 142 143def CondCodeOperand : AsmOperandClass { 144 let Name = "CondCode"; 145 let SuperClasses = []; 146} 147 148def CCOutOperand : AsmOperandClass { 149 let Name = "CCOut"; 150 let SuperClasses = []; 151} 152 153def MemBarrierOptOperand : AsmOperandClass { 154 let Name = "MemBarrierOpt"; 155 let SuperClasses = []; 156 let ParserMethod = "tryParseMemBarrierOptOperand"; 157} 158 159def ProcIFlagsOperand : AsmOperandClass { 160 let Name = "ProcIFlags"; 161 let SuperClasses = []; 162 let ParserMethod = "tryParseProcIFlagsOperand"; 163} 164 165def MSRMaskOperand : AsmOperandClass { 166 let Name = "MSRMask"; 167 let SuperClasses = []; 168 let ParserMethod = "tryParseMSRMaskOperand"; 169} 170 171// ARM imod and iflag operands, used only by the CPS instruction. 172def imod_op : Operand<i32> { 173 let PrintMethod = "printCPSIMod"; 174} 175 176def iflags_op : Operand<i32> { 177 let PrintMethod = "printCPSIFlag"; 178 let ParserMatchClass = ProcIFlagsOperand; 179} 180 181// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 182// register whose default is 0 (no register). 183def pred : PredicateOperand<OtherVT, (ops i32imm, CCR), 184 (ops (i32 14), (i32 zero_reg))> { 185 let PrintMethod = "printPredicateOperand"; 186 let ParserMatchClass = CondCodeOperand; 187} 188 189// Conditional code result for instructions whose 's' bit is set, e.g. subs. 190def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 191 let EncoderMethod = "getCCOutOpValue"; 192 let PrintMethod = "printSBitModifierOperand"; 193 let ParserMatchClass = CCOutOperand; 194} 195 196// Same as cc_out except it defaults to setting CPSR. 197def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 198 let EncoderMethod = "getCCOutOpValue"; 199 let PrintMethod = "printSBitModifierOperand"; 200 let ParserMatchClass = CCOutOperand; 201} 202 203// ARM special operands for disassembly only. 204// 205def setend_op : Operand<i32> { 206 let PrintMethod = "printSetendOperand"; 207} 208 209def msr_mask : Operand<i32> { 210 let PrintMethod = "printMSRMaskOperand"; 211 let ParserMatchClass = MSRMaskOperand; 212} 213 214// Shift Right Immediate - A shift right immediate is encoded differently from 215// other shift immediates. The imm6 field is encoded like so: 216// 217// Offset Encoding 218// 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0> 219// 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0> 220// 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0> 221// 64 64 - <imm> is encoded in imm6<5:0> 222def shr_imm8 : Operand<i32> { 223 let EncoderMethod = "getShiftRight8Imm"; 224} 225def shr_imm16 : Operand<i32> { 226 let EncoderMethod = "getShiftRight16Imm"; 227} 228def shr_imm32 : Operand<i32> { 229 let EncoderMethod = "getShiftRight32Imm"; 230} 231def shr_imm64 : Operand<i32> { 232 let EncoderMethod = "getShiftRight64Imm"; 233} 234 235//===----------------------------------------------------------------------===// 236// ARM Instruction templates. 237// 238 239class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im, 240 Format f, Domain d, string cstr, InstrItinClass itin> 241 : Instruction { 242 let Namespace = "ARM"; 243 244 AddrMode AM = am; 245 SizeFlagVal SZ = sz; 246 IndexMode IM = im; 247 bits<2> IndexModeBits = IM.Value; 248 Format F = f; 249 bits<6> Form = F.Value; 250 Domain D = d; 251 bit isUnaryDataProc = 0; 252 bit canXformTo16Bit = 0; 253 254 // If this is a pseudo instruction, mark it isCodeGenOnly. 255 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo"); 256 257 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h. 258 let TSFlags{4-0} = AM.Value; 259 let TSFlags{7-5} = SZ.Value; 260 let TSFlags{9-8} = IndexModeBits; 261 let TSFlags{15-10} = Form; 262 let TSFlags{16} = isUnaryDataProc; 263 let TSFlags{17} = canXformTo16Bit; 264 let TSFlags{20-18} = D.Value; 265 266 let Constraints = cstr; 267 let Itinerary = itin; 268} 269 270class Encoding { 271 field bits<32> Inst; 272} 273 274class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im, 275 Format f, Domain d, string cstr, InstrItinClass itin> 276 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding; 277 278// This Encoding-less class is used by Thumb1 to specify the encoding bits later 279// on by adding flavors to specific instructions. 280class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im, 281 Format f, Domain d, string cstr, InstrItinClass itin> 282 : InstTemplate<am, sz, im, f, d, cstr, itin>; 283 284class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern> 285 // FIXME: This really should derive from InstTemplate instead, as pseudos 286 // don't need encoding information. TableGen doesn't like that 287 // currently. Need to figure out why and fix it. 288 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain, 289 "", itin> { 290 let OutOperandList = oops; 291 let InOperandList = iops; 292 let Pattern = pattern; 293 let isCodeGenOnly = 1; 294} 295 296// PseudoInst that's ARM-mode only. 297class ARMPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin, 298 list<dag> pattern> 299 : PseudoInst<oops, iops, itin, pattern> { 300 let SZ = sz; 301 list<Predicate> Predicates = [IsARM]; 302} 303 304// PseudoInst that's Thumb-mode only. 305class tPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin, 306 list<dag> pattern> 307 : PseudoInst<oops, iops, itin, pattern> { 308 let SZ = sz; 309 list<Predicate> Predicates = [IsThumb]; 310} 311 312// PseudoInst that's Thumb2-mode only. 313class t2PseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin, 314 list<dag> pattern> 315 : PseudoInst<oops, iops, itin, pattern> { 316 let SZ = sz; 317 list<Predicate> Predicates = [IsThumb2]; 318} 319// Almost all ARM instructions are predicable. 320class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 321 IndexMode im, Format f, InstrItinClass itin, 322 string opc, string asm, string cstr, 323 list<dag> pattern> 324 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 325 bits<4> p; 326 let Inst{31-28} = p; 327 let OutOperandList = oops; 328 let InOperandList = !con(iops, (ins pred:$p)); 329 let AsmString = !strconcat(opc, "${p}", asm); 330 let Pattern = pattern; 331 list<Predicate> Predicates = [IsARM]; 332} 333 334// A few are not predicable 335class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 336 IndexMode im, Format f, InstrItinClass itin, 337 string opc, string asm, string cstr, 338 list<dag> pattern> 339 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 340 let OutOperandList = oops; 341 let InOperandList = iops; 342 let AsmString = !strconcat(opc, asm); 343 let Pattern = pattern; 344 let isPredicable = 0; 345 list<Predicate> Predicates = [IsARM]; 346} 347 348// Same as I except it can optionally modify CPSR. Note it's modeled as an input 349// operand since by default it's a zero register. It will become an implicit def 350// once it's "flipped". 351class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 352 IndexMode im, Format f, InstrItinClass itin, 353 string opc, string asm, string cstr, 354 list<dag> pattern> 355 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 356 bits<4> p; // Predicate operand 357 bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 358 let Inst{31-28} = p; 359 let Inst{20} = s; 360 361 let OutOperandList = oops; 362 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 363 let AsmString = !strconcat(opc, "${s}${p}", asm); 364 let Pattern = pattern; 365 list<Predicate> Predicates = [IsARM]; 366} 367 368// Special cases 369class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 370 IndexMode im, Format f, InstrItinClass itin, 371 string asm, string cstr, list<dag> pattern> 372 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 373 let OutOperandList = oops; 374 let InOperandList = iops; 375 let AsmString = asm; 376 let Pattern = pattern; 377 list<Predicate> Predicates = [IsARM]; 378} 379 380class AI<dag oops, dag iops, Format f, InstrItinClass itin, 381 string opc, string asm, list<dag> pattern> 382 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 383 opc, asm, "", pattern>; 384class AsI<dag oops, dag iops, Format f, InstrItinClass itin, 385 string opc, string asm, list<dag> pattern> 386 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 387 opc, asm, "", pattern>; 388class AXI<dag oops, dag iops, Format f, InstrItinClass itin, 389 string asm, list<dag> pattern> 390 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 391 asm, "", pattern>; 392class AInoP<dag oops, dag iops, Format f, InstrItinClass itin, 393 string opc, string asm, list<dag> pattern> 394 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 395 opc, asm, "", pattern>; 396 397// Ctrl flow instructions 398class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 399 string opc, string asm, list<dag> pattern> 400 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 401 opc, asm, "", pattern> { 402 let Inst{27-24} = opcod; 403} 404class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 405 string asm, list<dag> pattern> 406 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 407 asm, "", pattern> { 408 let Inst{27-24} = opcod; 409} 410 411// BR_JT instructions 412class JTI<dag oops, dag iops, InstrItinClass itin, 413 string asm, list<dag> pattern> 414 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin, 415 asm, "", pattern>; 416 417// Atomic load/store instructions 418class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 419 string opc, string asm, list<dag> pattern> 420 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 421 opc, asm, "", pattern> { 422 bits<4> Rt; 423 bits<4> Rn; 424 let Inst{27-23} = 0b00011; 425 let Inst{22-21} = opcod; 426 let Inst{20} = 1; 427 let Inst{19-16} = Rn; 428 let Inst{15-12} = Rt; 429 let Inst{11-0} = 0b111110011111; 430} 431class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 432 string opc, string asm, list<dag> pattern> 433 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 434 opc, asm, "", pattern> { 435 bits<4> Rd; 436 bits<4> Rt; 437 bits<4> addr; 438 let Inst{27-23} = 0b00011; 439 let Inst{22-21} = opcod; 440 let Inst{20} = 0; 441 let Inst{19-16} = addr; 442 let Inst{15-12} = Rd; 443 let Inst{11-4} = 0b11111001; 444 let Inst{3-0} = Rt; 445} 446class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern> 447 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> { 448 bits<4> Rt; 449 bits<4> Rt2; 450 bits<4> Rn; 451 let Inst{27-23} = 0b00010; 452 let Inst{22} = b; 453 let Inst{21-20} = 0b00; 454 let Inst{19-16} = Rn; 455 let Inst{15-12} = Rt; 456 let Inst{11-4} = 0b00001001; 457 let Inst{3-0} = Rt2; 458} 459 460// addrmode1 instructions 461class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 462 string opc, string asm, list<dag> pattern> 463 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 464 opc, asm, "", pattern> { 465 let Inst{24-21} = opcod; 466 let Inst{27-26} = 0b00; 467} 468class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 469 string opc, string asm, list<dag> pattern> 470 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 471 opc, asm, "", pattern> { 472 let Inst{24-21} = opcod; 473 let Inst{27-26} = 0b00; 474} 475class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 476 string asm, list<dag> pattern> 477 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 478 asm, "", pattern> { 479 let Inst{24-21} = opcod; 480 let Inst{27-26} = 0b00; 481} 482 483// loads 484 485// LDR/LDRB/STR/STRB/... 486class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am, 487 Format f, InstrItinClass itin, string opc, string asm, 488 list<dag> pattern> 489 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm, 490 "", pattern> { 491 let Inst{27-25} = op; 492 let Inst{24} = 1; // 24 == P 493 // 23 == U 494 let Inst{22} = isByte; 495 let Inst{21} = 0; // 21 == W 496 let Inst{20} = isLd; 497} 498// Indexed load/stores 499class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops, 500 IndexMode im, Format f, InstrItinClass itin, string opc, 501 string asm, string cstr, list<dag> pattern> 502 : I<oops, iops, AddrMode2, Size4Bytes, im, f, itin, 503 opc, asm, cstr, pattern> { 504 bits<4> Rt; 505 let Inst{27-26} = 0b01; 506 let Inst{24} = isPre; // P bit 507 let Inst{22} = isByte; // B bit 508 let Inst{21} = isPre; // W bit 509 let Inst{20} = isLd; // L bit 510 let Inst{15-12} = Rt; 511} 512class AI2stridx<bit isByte, bit isPre, dag oops, dag iops, 513 IndexMode im, Format f, InstrItinClass itin, string opc, 514 string asm, string cstr, list<dag> pattern> 515 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 516 pattern> { 517 // AM2 store w/ two operands: (GPR, am2offset) 518 // {13} 1 == Rm, 0 == imm12 519 // {12} isAdd 520 // {11-0} imm12/Rm 521 bits<14> offset; 522 bits<4> Rn; 523 let Inst{25} = offset{13}; 524 let Inst{23} = offset{12}; 525 let Inst{19-16} = Rn; 526 let Inst{11-0} = offset{11-0}; 527} 528// FIXME: Merge with the above class when addrmode2 gets used for STR, STRB 529// but for now use this class for STRT and STRBT. 530class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops, 531 IndexMode im, Format f, InstrItinClass itin, string opc, 532 string asm, string cstr, list<dag> pattern> 533 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 534 pattern> { 535 // AM2 store w/ two operands: (GPR, am2offset) 536 // {17-14} Rn 537 // {13} 1 == Rm, 0 == imm12 538 // {12} isAdd 539 // {11-0} imm12/Rm 540 bits<18> addr; 541 let Inst{25} = addr{13}; 542 let Inst{23} = addr{12}; 543 let Inst{19-16} = addr{17-14}; 544 let Inst{11-0} = addr{11-0}; 545} 546 547// addrmode3 instructions 548class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f, 549 InstrItinClass itin, string opc, string asm, list<dag> pattern> 550 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 551 opc, asm, "", pattern> { 552 bits<14> addr; 553 bits<4> Rt; 554 let Inst{27-25} = 0b000; 555 let Inst{24} = 1; // P bit 556 let Inst{23} = addr{8}; // U bit 557 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 558 let Inst{21} = 0; // W bit 559 let Inst{20} = op20; // L bit 560 let Inst{19-16} = addr{12-9}; // Rn 561 let Inst{15-12} = Rt; // Rt 562 let Inst{11-8} = addr{7-4}; // imm7_4/zero 563 let Inst{7-4} = op; 564 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 565} 566 567class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops, 568 IndexMode im, Format f, InstrItinClass itin, string opc, 569 string asm, string cstr, list<dag> pattern> 570 : I<oops, iops, AddrMode3, Size4Bytes, im, f, itin, 571 opc, asm, cstr, pattern> { 572 bits<4> Rt; 573 let Inst{27-25} = 0b000; 574 let Inst{24} = isPre; // P bit 575 let Inst{21} = isPre; // W bit 576 let Inst{20} = op20; // L bit 577 let Inst{15-12} = Rt; // Rt 578 let Inst{7-4} = op; 579} 580 581// FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB 582// but for now use this class for LDRSBT, LDRHT, LDSHT. 583class AI3ldstidxT<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops, 584 IndexMode im, Format f, InstrItinClass itin, string opc, 585 string asm, string cstr, list<dag> pattern> 586 : I<oops, iops, AddrMode3, Size4Bytes, im, f, itin, 587 opc, asm, cstr, pattern> { 588 // {13} 1 == imm8, 0 == Rm 589 // {12-9} Rn 590 // {8} isAdd 591 // {7-4} imm7_4/zero 592 // {3-0} imm3_0/Rm 593 bits<14> addr; 594 bits<4> Rt; 595 let Inst{27-25} = 0b000; 596 let Inst{24} = isPre; // P bit 597 let Inst{23} = addr{8}; // U bit 598 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 599 let Inst{20} = op20; // L bit 600 let Inst{19-16} = addr{12-9}; // Rn 601 let Inst{15-12} = Rt; // Rt 602 let Inst{11-8} = addr{7-4}; // imm7_4/zero 603 let Inst{7-4} = op; 604 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 605 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode3"; 606} 607 608class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops, 609 IndexMode im, Format f, InstrItinClass itin, string opc, 610 string asm, string cstr, list<dag> pattern> 611 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 612 pattern> { 613 // AM3 store w/ two operands: (GPR, am3offset) 614 bits<14> offset; 615 bits<4> Rt; 616 bits<4> Rn; 617 let Inst{27-25} = 0b000; 618 let Inst{23} = offset{8}; 619 let Inst{22} = offset{9}; 620 let Inst{19-16} = Rn; 621 let Inst{15-12} = Rt; // Rt 622 let Inst{11-8} = offset{7-4}; // imm7_4/zero 623 let Inst{7-4} = op; 624 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 625} 626 627// stores 628class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin, 629 string opc, string asm, list<dag> pattern> 630 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 631 opc, asm, "", pattern> { 632 bits<14> addr; 633 bits<4> Rt; 634 let Inst{27-25} = 0b000; 635 let Inst{24} = 1; // P bit 636 let Inst{23} = addr{8}; // U bit 637 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 638 let Inst{21} = 0; // W bit 639 let Inst{20} = 0; // L bit 640 let Inst{19-16} = addr{12-9}; // Rn 641 let Inst{15-12} = Rt; // Rt 642 let Inst{11-8} = addr{7-4}; // imm7_4/zero 643 let Inst{7-4} = op; 644 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 645} 646 647// Pre-indexed stores 648class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin, 649 string opc, string asm, string cstr, list<dag> pattern> 650 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 651 opc, asm, cstr, pattern> { 652 let Inst{4} = 1; 653 let Inst{5} = 1; // H bit 654 let Inst{6} = 0; // S bit 655 let Inst{7} = 1; 656 let Inst{20} = 0; // L bit 657 let Inst{21} = 1; // W bit 658 let Inst{24} = 1; // P bit 659 let Inst{27-25} = 0b000; 660} 661class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin, 662 string opc, string asm, string cstr, list<dag> pattern> 663 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 664 opc, asm, cstr, pattern> { 665 let Inst{4} = 1; 666 let Inst{5} = 1; // H bit 667 let Inst{6} = 1; // S bit 668 let Inst{7} = 1; 669 let Inst{20} = 0; // L bit 670 let Inst{21} = 1; // W bit 671 let Inst{24} = 1; // P bit 672 let Inst{27-25} = 0b000; 673} 674 675// Post-indexed stores 676class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin, 677 string opc, string asm, string cstr, list<dag> pattern> 678 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 679 opc, asm, cstr,pattern> { 680 // {13} 1 == imm8, 0 == Rm 681 // {12-9} Rn 682 // {8} isAdd 683 // {7-4} imm7_4/zero 684 // {3-0} imm3_0/Rm 685 bits<14> addr; 686 bits<4> Rt; 687 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 688 let Inst{4} = 1; 689 let Inst{5} = 1; // H bit 690 let Inst{6} = 0; // S bit 691 let Inst{7} = 1; 692 let Inst{11-8} = addr{7-4}; // imm7_4/zero 693 let Inst{15-12} = Rt; // Rt 694 let Inst{19-16} = addr{12-9}; // Rn 695 let Inst{20} = 0; // L bit 696 let Inst{21} = 0; // W bit 697 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 698 let Inst{23} = addr{8}; // U bit 699 let Inst{24} = 0; // P bit 700 let Inst{27-25} = 0b000; 701} 702class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin, 703 string opc, string asm, string cstr, list<dag> pattern> 704 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 705 opc, asm, cstr, pattern> { 706 let Inst{4} = 1; 707 let Inst{5} = 1; // H bit 708 let Inst{6} = 1; // S bit 709 let Inst{7} = 1; 710 let Inst{20} = 0; // L bit 711 let Inst{21} = 0; // W bit 712 let Inst{24} = 0; // P bit 713 let Inst{27-25} = 0b000; 714} 715 716// addrmode4 instructions 717class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, 718 string asm, string cstr, list<dag> pattern> 719 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, asm, cstr, pattern> { 720 bits<4> p; 721 bits<16> regs; 722 bits<4> Rn; 723 let Inst{31-28} = p; 724 let Inst{27-25} = 0b100; 725 let Inst{22} = 0; // S bit 726 let Inst{19-16} = Rn; 727 let Inst{15-0} = regs; 728} 729 730// Unsigned multiply, multiply-accumulate instructions. 731class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 732 string opc, string asm, list<dag> pattern> 733 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 734 opc, asm, "", pattern> { 735 let Inst{7-4} = 0b1001; 736 let Inst{20} = 0; // S bit 737 let Inst{27-21} = opcod; 738} 739class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 740 string opc, string asm, list<dag> pattern> 741 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 742 opc, asm, "", pattern> { 743 let Inst{7-4} = 0b1001; 744 let Inst{27-21} = opcod; 745} 746 747// Most significant word multiply 748class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 749 InstrItinClass itin, string opc, string asm, list<dag> pattern> 750 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 751 opc, asm, "", pattern> { 752 bits<4> Rd; 753 bits<4> Rn; 754 bits<4> Rm; 755 let Inst{7-4} = opc7_4; 756 let Inst{20} = 1; 757 let Inst{27-21} = opcod; 758 let Inst{19-16} = Rd; 759 let Inst{11-8} = Rm; 760 let Inst{3-0} = Rn; 761} 762// MSW multiple w/ Ra operand 763class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 764 InstrItinClass itin, string opc, string asm, list<dag> pattern> 765 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> { 766 bits<4> Ra; 767 let Inst{15-12} = Ra; 768} 769 770// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 771class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 772 InstrItinClass itin, string opc, string asm, list<dag> pattern> 773 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 774 opc, asm, "", pattern> { 775 bits<4> Rn; 776 bits<4> Rm; 777 let Inst{4} = 0; 778 let Inst{7} = 1; 779 let Inst{20} = 0; 780 let Inst{27-21} = opcod; 781 let Inst{6-5} = bit6_5; 782 let Inst{11-8} = Rm; 783 let Inst{3-0} = Rn; 784} 785class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 786 InstrItinClass itin, string opc, string asm, list<dag> pattern> 787 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 788 bits<4> Rd; 789 let Inst{19-16} = Rd; 790} 791 792// AMulxyI with Ra operand 793class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 794 InstrItinClass itin, string opc, string asm, list<dag> pattern> 795 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 796 bits<4> Ra; 797 let Inst{15-12} = Ra; 798} 799// SMLAL* 800class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 801 InstrItinClass itin, string opc, string asm, list<dag> pattern> 802 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 803 bits<4> RdLo; 804 bits<4> RdHi; 805 let Inst{19-16} = RdHi; 806 let Inst{15-12} = RdLo; 807} 808 809// Extend instructions. 810class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 811 string opc, string asm, list<dag> pattern> 812 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin, 813 opc, asm, "", pattern> { 814 // All AExtI instructions have Rd and Rm register operands. 815 bits<4> Rd; 816 bits<4> Rm; 817 let Inst{15-12} = Rd; 818 let Inst{3-0} = Rm; 819 let Inst{7-4} = 0b0111; 820 let Inst{9-8} = 0b00; 821 let Inst{27-20} = opcod; 822} 823 824// Misc Arithmetic instructions. 825class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops, 826 InstrItinClass itin, string opc, string asm, list<dag> pattern> 827 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin, 828 opc, asm, "", pattern> { 829 bits<4> Rd; 830 bits<4> Rm; 831 let Inst{27-20} = opcod; 832 let Inst{19-16} = 0b1111; 833 let Inst{15-12} = Rd; 834 let Inst{11-8} = 0b1111; 835 let Inst{7-4} = opc7_4; 836 let Inst{3-0} = Rm; 837} 838 839// PKH instructions 840class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin, 841 string opc, string asm, list<dag> pattern> 842 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin, 843 opc, asm, "", pattern> { 844 bits<4> Rd; 845 bits<4> Rn; 846 bits<4> Rm; 847 bits<8> sh; 848 let Inst{27-20} = opcod; 849 let Inst{19-16} = Rn; 850 let Inst{15-12} = Rd; 851 let Inst{11-7} = sh{7-3}; 852 let Inst{6} = tb; 853 let Inst{5-4} = 0b01; 854 let Inst{3-0} = Rm; 855} 856 857//===----------------------------------------------------------------------===// 858 859// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 860class ARMPat<dag pattern, dag result> : Pat<pattern, result> { 861 list<Predicate> Predicates = [IsARM]; 862} 863class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 864 list<Predicate> Predicates = [IsARM, HasV5TE]; 865} 866class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 867 list<Predicate> Predicates = [IsARM, HasV6]; 868} 869 870//===----------------------------------------------------------------------===// 871// Thumb Instruction Format Definitions. 872// 873 874class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 875 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 876 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 877 let OutOperandList = oops; 878 let InOperandList = iops; 879 let AsmString = asm; 880 let Pattern = pattern; 881 list<Predicate> Predicates = [IsThumb]; 882} 883 884// TI - Thumb instruction. 885class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 886 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 887 888// Two-address instructions 889class TIt<dag oops, dag iops, InstrItinClass itin, string asm, 890 list<dag> pattern> 891 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", 892 pattern>; 893 894// tBL, tBX 32-bit instructions 895class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, 896 dag oops, dag iops, InstrItinClass itin, string asm, 897 list<dag> pattern> 898 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, 899 Encoding { 900 let Inst{31-27} = opcod1; 901 let Inst{15-14} = opcod2; 902 let Inst{12} = opcod3; 903} 904 905// Move to/from coprocessor instructions 906class T1Cop<dag oops, dag iops, string asm, list<dag> pattern> 907 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, NoItinerary, asm, "", pattern>, 908 Encoding, Requires<[IsThumb, HasV6]> { 909 let Inst{31-28} = 0b1110; 910} 911 912// BR_JT instructions 913class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, 914 list<dag> pattern> 915 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 916 917// Thumb1 only 918class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 919 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 920 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 921 let OutOperandList = oops; 922 let InOperandList = iops; 923 let AsmString = asm; 924 let Pattern = pattern; 925 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 926} 927 928class T1I<dag oops, dag iops, InstrItinClass itin, 929 string asm, list<dag> pattern> 930 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 931class T1Ix2<dag oops, dag iops, InstrItinClass itin, 932 string asm, list<dag> pattern> 933 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 934 935// Two-address instructions 936class T1It<dag oops, dag iops, InstrItinClass itin, 937 string asm, string cstr, list<dag> pattern> 938 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, 939 asm, cstr, pattern>; 940 941// Thumb1 instruction that can either be predicated or set CPSR. 942class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 943 InstrItinClass itin, 944 string opc, string asm, string cstr, list<dag> pattern> 945 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 946 let OutOperandList = !con(oops, (outs s_cc_out:$s)); 947 let InOperandList = !con(iops, (ins pred:$p)); 948 let AsmString = !strconcat(opc, "${s}${p}", asm); 949 let Pattern = pattern; 950 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 951} 952 953class T1sI<dag oops, dag iops, InstrItinClass itin, 954 string opc, string asm, list<dag> pattern> 955 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 956 957// Two-address instructions 958class T1sIt<dag oops, dag iops, InstrItinClass itin, 959 string opc, string asm, list<dag> pattern> 960 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 961 "$Rn = $Rdn", pattern>; 962 963// Thumb1 instruction that can be predicated. 964class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 965 InstrItinClass itin, 966 string opc, string asm, string cstr, list<dag> pattern> 967 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 968 let OutOperandList = oops; 969 let InOperandList = !con(iops, (ins pred:$p)); 970 let AsmString = !strconcat(opc, "${p}", asm); 971 let Pattern = pattern; 972 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 973} 974 975class T1pI<dag oops, dag iops, InstrItinClass itin, 976 string opc, string asm, list<dag> pattern> 977 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 978 979// Two-address instructions 980class T1pIt<dag oops, dag iops, InstrItinClass itin, 981 string opc, string asm, list<dag> pattern> 982 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 983 "$Rn = $Rdn", pattern>; 984 985class T1pIs<dag oops, dag iops, 986 InstrItinClass itin, string opc, string asm, list<dag> pattern> 987 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>; 988 989class Encoding16 : Encoding { 990 let Inst{31-16} = 0x0000; 991} 992 993// A6.2 16-bit Thumb instruction encoding 994class T1Encoding<bits<6> opcode> : Encoding16 { 995 let Inst{15-10} = opcode; 996} 997 998// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. 999class T1General<bits<5> opcode> : Encoding16 { 1000 let Inst{15-14} = 0b00; 1001 let Inst{13-9} = opcode; 1002} 1003 1004// A6.2.2 Data-processing encoding. 1005class T1DataProcessing<bits<4> opcode> : Encoding16 { 1006 let Inst{15-10} = 0b010000; 1007 let Inst{9-6} = opcode; 1008} 1009 1010// A6.2.3 Special data instructions and branch and exchange encoding. 1011class T1Special<bits<4> opcode> : Encoding16 { 1012 let Inst{15-10} = 0b010001; 1013 let Inst{9-6} = opcode; 1014} 1015 1016// A6.2.4 Load/store single data item encoding. 1017class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { 1018 let Inst{15-12} = opA; 1019 let Inst{11-9} = opB; 1020} 1021class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative 1022 1023// Helper classes to encode Thumb1 loads and stores. For immediates, the 1024// following bits are used for "opA" (see A6.2.4): 1025// 1026// 0b0110 => Immediate, 4 bytes 1027// 0b1000 => Immediate, 2 bytes 1028// 0b0111 => Immediate, 1 byte 1029class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am, 1030 InstrItinClass itin, string opc, string asm, 1031 list<dag> pattern> 1032 : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>, 1033 T1LoadStore<0b0101, opcode> { 1034 bits<3> Rt; 1035 bits<8> addr; 1036 let Inst{8-6} = addr{5-3}; // Rm 1037 let Inst{5-3} = addr{2-0}; // Rn 1038 let Inst{2-0} = Rt; 1039} 1040class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am, 1041 InstrItinClass itin, string opc, string asm, 1042 list<dag> pattern> 1043 : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>, 1044 T1LoadStore<opA, {opB,?,?}> { 1045 bits<3> Rt; 1046 bits<8> addr; 1047 let Inst{10-6} = addr{7-3}; // imm5 1048 let Inst{5-3} = addr{2-0}; // Rn 1049 let Inst{2-0} = Rt; 1050} 1051 1052// A6.2.5 Miscellaneous 16-bit instructions encoding. 1053class T1Misc<bits<7> opcode> : Encoding16 { 1054 let Inst{15-12} = 0b1011; 1055 let Inst{11-5} = opcode; 1056} 1057 1058// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 1059class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1060 InstrItinClass itin, 1061 string opc, string asm, string cstr, list<dag> pattern> 1062 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1063 let OutOperandList = oops; 1064 let InOperandList = !con(iops, (ins pred:$p)); 1065 let AsmString = !strconcat(opc, "${p}", asm); 1066 let Pattern = pattern; 1067 list<Predicate> Predicates = [IsThumb2]; 1068} 1069 1070// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an 1071// input operand since by default it's a zero register. It will become an 1072// implicit def once it's "flipped". 1073// 1074// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 1075// more consistent. 1076class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1077 InstrItinClass itin, 1078 string opc, string asm, string cstr, list<dag> pattern> 1079 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1080 bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 1081 let Inst{20} = s; 1082 1083 let OutOperandList = oops; 1084 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 1085 let AsmString = !strconcat(opc, "${s}${p}", asm); 1086 let Pattern = pattern; 1087 list<Predicate> Predicates = [IsThumb2]; 1088} 1089 1090// Special cases 1091class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1092 InstrItinClass itin, 1093 string asm, string cstr, list<dag> pattern> 1094 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1095 let OutOperandList = oops; 1096 let InOperandList = iops; 1097 let AsmString = asm; 1098 let Pattern = pattern; 1099 list<Predicate> Predicates = [IsThumb2]; 1100} 1101 1102class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1103 InstrItinClass itin, 1104 string asm, string cstr, list<dag> pattern> 1105 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1106 let OutOperandList = oops; 1107 let InOperandList = iops; 1108 let AsmString = asm; 1109 let Pattern = pattern; 1110 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1111} 1112 1113class T2I<dag oops, dag iops, InstrItinClass itin, 1114 string opc, string asm, list<dag> pattern> 1115 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1116class T2Ii12<dag oops, dag iops, InstrItinClass itin, 1117 string opc, string asm, list<dag> pattern> 1118 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>; 1119class T2Ii8<dag oops, dag iops, InstrItinClass itin, 1120 string opc, string asm, list<dag> pattern> 1121 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>; 1122class T2Iso<dag oops, dag iops, InstrItinClass itin, 1123 string opc, string asm, list<dag> pattern> 1124 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>; 1125class T2Ipc<dag oops, dag iops, InstrItinClass itin, 1126 string opc, string asm, list<dag> pattern> 1127 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>; 1128class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin, 1129 string opc, string asm, list<dag> pattern> 1130 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "", 1131 pattern> { 1132 bits<4> Rt; 1133 bits<4> Rt2; 1134 bits<13> addr; 1135 let Inst{31-25} = 0b1110100; 1136 let Inst{24} = P; 1137 let Inst{23} = addr{8}; 1138 let Inst{22} = 1; 1139 let Inst{21} = W; 1140 let Inst{20} = isLoad; 1141 let Inst{19-16} = addr{12-9}; 1142 let Inst{15-12} = Rt{3-0}; 1143 let Inst{11-8} = Rt2{3-0}; 1144 let Inst{7-0} = addr{7-0}; 1145} 1146 1147class T2sI<dag oops, dag iops, InstrItinClass itin, 1148 string opc, string asm, list<dag> pattern> 1149 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1150 1151class T2XI<dag oops, dag iops, InstrItinClass itin, 1152 string asm, list<dag> pattern> 1153 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 1154class T2JTI<dag oops, dag iops, InstrItinClass itin, 1155 string asm, list<dag> pattern> 1156 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 1157 1158// Move to/from coprocessor instructions 1159class T2Cop<dag oops, dag iops, string asm, list<dag> pattern> 1160 : T2XI<oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2, HasV6]> { 1161 let Inst{31-28} = 0b1111; 1162} 1163 1164// Two-address instructions 1165class T2XIt<dag oops, dag iops, InstrItinClass itin, 1166 string asm, string cstr, list<dag> pattern> 1167 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>; 1168 1169// T2Iidxldst - Thumb2 indexed load / store instructions. 1170class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre, 1171 dag oops, dag iops, 1172 AddrMode am, IndexMode im, InstrItinClass itin, 1173 string opc, string asm, string cstr, list<dag> pattern> 1174 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> { 1175 let OutOperandList = oops; 1176 let InOperandList = !con(iops, (ins pred:$p)); 1177 let AsmString = !strconcat(opc, "${p}", asm); 1178 let Pattern = pattern; 1179 list<Predicate> Predicates = [IsThumb2]; 1180 let Inst{31-27} = 0b11111; 1181 let Inst{26-25} = 0b00; 1182 let Inst{24} = signed; 1183 let Inst{23} = 0; 1184 let Inst{22-21} = opcod; 1185 let Inst{20} = load; 1186 let Inst{11} = 1; 1187 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1188 let Inst{10} = pre; // The P bit. 1189 let Inst{8} = 1; // The W bit. 1190 1191 bits<9> addr; 1192 let Inst{7-0} = addr{7-0}; 1193 let Inst{9} = addr{8}; // Sign bit 1194 1195 bits<4> Rt; 1196 bits<4> Rn; 1197 let Inst{15-12} = Rt{3-0}; 1198 let Inst{19-16} = Rn{3-0}; 1199} 1200 1201// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 1202class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 1203 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T]; 1204} 1205 1206// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 1207class T1Pat<dag pattern, dag result> : Pat<pattern, result> { 1208 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1209} 1210 1211// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 1212class T2Pat<dag pattern, dag result> : Pat<pattern, result> { 1213 list<Predicate> Predicates = [IsThumb2]; 1214} 1215 1216//===----------------------------------------------------------------------===// 1217 1218//===----------------------------------------------------------------------===// 1219// ARM VFP Instruction templates. 1220// 1221 1222// Almost all VFP instructions are predicable. 1223class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1224 IndexMode im, Format f, InstrItinClass itin, 1225 string opc, string asm, string cstr, list<dag> pattern> 1226 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1227 bits<4> p; 1228 let Inst{31-28} = p; 1229 let OutOperandList = oops; 1230 let InOperandList = !con(iops, (ins pred:$p)); 1231 let AsmString = !strconcat(opc, "${p}", asm); 1232 let Pattern = pattern; 1233 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1234 list<Predicate> Predicates = [HasVFP2]; 1235} 1236 1237// Special cases 1238class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1239 IndexMode im, Format f, InstrItinClass itin, 1240 string asm, string cstr, list<dag> pattern> 1241 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1242 bits<4> p; 1243 let Inst{31-28} = p; 1244 let OutOperandList = oops; 1245 let InOperandList = iops; 1246 let AsmString = asm; 1247 let Pattern = pattern; 1248 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1249 list<Predicate> Predicates = [HasVFP2]; 1250} 1251 1252class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, 1253 string opc, string asm, list<dag> pattern> 1254 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 1255 opc, asm, "", pattern> { 1256 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1257} 1258 1259// ARM VFP addrmode5 loads and stores 1260class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1261 InstrItinClass itin, 1262 string opc, string asm, list<dag> pattern> 1263 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1264 VFPLdStFrm, itin, opc, asm, "", pattern> { 1265 // Instruction operands. 1266 bits<5> Dd; 1267 bits<13> addr; 1268 1269 // Encode instruction operands. 1270 let Inst{23} = addr{8}; // U (add = (U == '1')) 1271 let Inst{22} = Dd{4}; 1272 let Inst{19-16} = addr{12-9}; // Rn 1273 let Inst{15-12} = Dd{3-0}; 1274 let Inst{7-0} = addr{7-0}; // imm8 1275 1276 // TODO: Mark the instructions with the appropriate subtarget info. 1277 let Inst{27-24} = opcod1; 1278 let Inst{21-20} = opcod2; 1279 let Inst{11-9} = 0b101; 1280 let Inst{8} = 1; // Double precision 1281 1282 // Loads & stores operate on both NEON and VFP pipelines. 1283 let D = VFPNeonDomain; 1284} 1285 1286class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1287 InstrItinClass itin, 1288 string opc, string asm, list<dag> pattern> 1289 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1290 VFPLdStFrm, itin, opc, asm, "", pattern> { 1291 // Instruction operands. 1292 bits<5> Sd; 1293 bits<13> addr; 1294 1295 // Encode instruction operands. 1296 let Inst{23} = addr{8}; // U (add = (U == '1')) 1297 let Inst{22} = Sd{0}; 1298 let Inst{19-16} = addr{12-9}; // Rn 1299 let Inst{15-12} = Sd{4-1}; 1300 let Inst{7-0} = addr{7-0}; // imm8 1301 1302 // TODO: Mark the instructions with the appropriate subtarget info. 1303 let Inst{27-24} = opcod1; 1304 let Inst{21-20} = opcod2; 1305 let Inst{11-9} = 0b101; 1306 let Inst{8} = 0; // Single precision 1307 1308 // Loads & stores operate on both NEON and VFP pipelines. 1309 let D = VFPNeonDomain; 1310} 1311 1312// VFP Load / store multiple pseudo instructions. 1313class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr, 1314 list<dag> pattern> 1315 : InstARM<AddrMode4, Size4Bytes, IndexModeNone, Pseudo, VFPNeonDomain, 1316 cstr, itin> { 1317 let OutOperandList = oops; 1318 let InOperandList = !con(iops, (ins pred:$p)); 1319 let Pattern = pattern; 1320 list<Predicate> Predicates = [HasVFP2]; 1321} 1322 1323// Load / store multiple 1324class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1325 string asm, string cstr, list<dag> pattern> 1326 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im, 1327 VFPLdStMulFrm, itin, asm, cstr, pattern> { 1328 // Instruction operands. 1329 bits<4> Rn; 1330 bits<13> regs; 1331 1332 // Encode instruction operands. 1333 let Inst{19-16} = Rn; 1334 let Inst{22} = regs{12}; 1335 let Inst{15-12} = regs{11-8}; 1336 let Inst{7-0} = regs{7-0}; 1337 1338 // TODO: Mark the instructions with the appropriate subtarget info. 1339 let Inst{27-25} = 0b110; 1340 let Inst{11-9} = 0b101; 1341 let Inst{8} = 1; // Double precision 1342} 1343 1344class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1345 string asm, string cstr, list<dag> pattern> 1346 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im, 1347 VFPLdStMulFrm, itin, asm, cstr, pattern> { 1348 // Instruction operands. 1349 bits<4> Rn; 1350 bits<13> regs; 1351 1352 // Encode instruction operands. 1353 let Inst{19-16} = Rn; 1354 let Inst{22} = regs{8}; 1355 let Inst{15-12} = regs{12-9}; 1356 let Inst{7-0} = regs{7-0}; 1357 1358 // TODO: Mark the instructions with the appropriate subtarget info. 1359 let Inst{27-25} = 0b110; 1360 let Inst{11-9} = 0b101; 1361 let Inst{8} = 0; // Single precision 1362} 1363 1364// Double precision, unary 1365class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1366 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1367 string asm, list<dag> pattern> 1368 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1369 // Instruction operands. 1370 bits<5> Dd; 1371 bits<5> Dm; 1372 1373 // Encode instruction operands. 1374 let Inst{3-0} = Dm{3-0}; 1375 let Inst{5} = Dm{4}; 1376 let Inst{15-12} = Dd{3-0}; 1377 let Inst{22} = Dd{4}; 1378 1379 let Inst{27-23} = opcod1; 1380 let Inst{21-20} = opcod2; 1381 let Inst{19-16} = opcod3; 1382 let Inst{11-9} = 0b101; 1383 let Inst{8} = 1; // Double precision 1384 let Inst{7-6} = opcod4; 1385 let Inst{4} = opcod5; 1386} 1387 1388// Double precision, binary 1389class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1390 dag iops, InstrItinClass itin, string opc, string asm, 1391 list<dag> pattern> 1392 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1393 // Instruction operands. 1394 bits<5> Dd; 1395 bits<5> Dn; 1396 bits<5> Dm; 1397 1398 // Encode instruction operands. 1399 let Inst{3-0} = Dm{3-0}; 1400 let Inst{5} = Dm{4}; 1401 let Inst{19-16} = Dn{3-0}; 1402 let Inst{7} = Dn{4}; 1403 let Inst{15-12} = Dd{3-0}; 1404 let Inst{22} = Dd{4}; 1405 1406 let Inst{27-23} = opcod1; 1407 let Inst{21-20} = opcod2; 1408 let Inst{11-9} = 0b101; 1409 let Inst{8} = 1; // Double precision 1410 let Inst{6} = op6; 1411 let Inst{4} = op4; 1412} 1413 1414// Single precision, unary 1415class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1416 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1417 string asm, list<dag> pattern> 1418 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1419 // Instruction operands. 1420 bits<5> Sd; 1421 bits<5> Sm; 1422 1423 // Encode instruction operands. 1424 let Inst{3-0} = Sm{4-1}; 1425 let Inst{5} = Sm{0}; 1426 let Inst{15-12} = Sd{4-1}; 1427 let Inst{22} = Sd{0}; 1428 1429 let Inst{27-23} = opcod1; 1430 let Inst{21-20} = opcod2; 1431 let Inst{19-16} = opcod3; 1432 let Inst{11-9} = 0b101; 1433 let Inst{8} = 0; // Single precision 1434 let Inst{7-6} = opcod4; 1435 let Inst{4} = opcod5; 1436} 1437 1438// Single precision unary, if no NEON. Same as ASuI except not available if 1439// NEON is enabled. 1440class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1441 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1442 string asm, list<dag> pattern> 1443 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm, 1444 pattern> { 1445 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1446} 1447 1448// Single precision, binary 1449class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1450 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1451 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1452 // Instruction operands. 1453 bits<5> Sd; 1454 bits<5> Sn; 1455 bits<5> Sm; 1456 1457 // Encode instruction operands. 1458 let Inst{3-0} = Sm{4-1}; 1459 let Inst{5} = Sm{0}; 1460 let Inst{19-16} = Sn{4-1}; 1461 let Inst{7} = Sn{0}; 1462 let Inst{15-12} = Sd{4-1}; 1463 let Inst{22} = Sd{0}; 1464 1465 let Inst{27-23} = opcod1; 1466 let Inst{21-20} = opcod2; 1467 let Inst{11-9} = 0b101; 1468 let Inst{8} = 0; // Single precision 1469 let Inst{6} = op6; 1470 let Inst{4} = op4; 1471} 1472 1473// Single precision binary, if no NEON. Same as ASbI except not available if 1474// NEON is enabled. 1475class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1476 dag iops, InstrItinClass itin, string opc, string asm, 1477 list<dag> pattern> 1478 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1479 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1480 1481 // Instruction operands. 1482 bits<5> Sd; 1483 bits<5> Sn; 1484 bits<5> Sm; 1485 1486 // Encode instruction operands. 1487 let Inst{3-0} = Sm{4-1}; 1488 let Inst{5} = Sm{0}; 1489 let Inst{19-16} = Sn{4-1}; 1490 let Inst{7} = Sn{0}; 1491 let Inst{15-12} = Sd{4-1}; 1492 let Inst{22} = Sd{0}; 1493} 1494 1495// VFP conversion instructions 1496class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1497 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1498 list<dag> pattern> 1499 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { 1500 let Inst{27-23} = opcod1; 1501 let Inst{21-20} = opcod2; 1502 let Inst{19-16} = opcod3; 1503 let Inst{11-8} = opcod4; 1504 let Inst{6} = 1; 1505 let Inst{4} = 0; 1506} 1507 1508// VFP conversion between floating-point and fixed-point 1509class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 1510 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1511 list<dag> pattern> 1512 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { 1513 // size (fixed-point number): sx == 0 ? 16 : 32 1514 let Inst{7} = op5; // sx 1515} 1516 1517// VFP conversion instructions, if no NEON 1518class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1519 dag oops, dag iops, InstrItinClass itin, 1520 string opc, string asm, list<dag> pattern> 1521 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1522 pattern> { 1523 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1524} 1525 1526class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1527 InstrItinClass itin, 1528 string opc, string asm, list<dag> pattern> 1529 : VFPAI<oops, iops, f, itin, opc, asm, pattern> { 1530 let Inst{27-20} = opcod1; 1531 let Inst{11-8} = opcod2; 1532 let Inst{4} = 1; 1533} 1534 1535class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1536 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1537 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; 1538 1539class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1540 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1541 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; 1542 1543class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1544 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1545 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; 1546 1547class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1548 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1549 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; 1550 1551//===----------------------------------------------------------------------===// 1552 1553//===----------------------------------------------------------------------===// 1554// ARM NEON Instruction templates. 1555// 1556 1557class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1558 InstrItinClass itin, string opc, string dt, string asm, string cstr, 1559 list<dag> pattern> 1560 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> { 1561 let OutOperandList = oops; 1562 let InOperandList = !con(iops, (ins pred:$p)); 1563 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1564 let Pattern = pattern; 1565 list<Predicate> Predicates = [HasNEON]; 1566} 1567 1568// Same as NeonI except it does not have a "data type" specifier. 1569class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1570 InstrItinClass itin, string opc, string asm, string cstr, 1571 list<dag> pattern> 1572 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> { 1573 let OutOperandList = oops; 1574 let InOperandList = !con(iops, (ins pred:$p)); 1575 let AsmString = !strconcat(opc, "${p}", "\t", asm); 1576 let Pattern = pattern; 1577 list<Predicate> Predicates = [HasNEON]; 1578} 1579 1580class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1581 dag oops, dag iops, InstrItinClass itin, 1582 string opc, string dt, string asm, string cstr, list<dag> pattern> 1583 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm, 1584 cstr, pattern> { 1585 let Inst{31-24} = 0b11110100; 1586 let Inst{23} = op23; 1587 let Inst{21-20} = op21_20; 1588 let Inst{11-8} = op11_8; 1589 let Inst{7-4} = op7_4; 1590 1591 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder"; 1592 1593 bits<5> Vd; 1594 bits<6> Rn; 1595 bits<4> Rm; 1596 1597 let Inst{22} = Vd{4}; 1598 let Inst{15-12} = Vd{3-0}; 1599 let Inst{19-16} = Rn{3-0}; 1600 let Inst{3-0} = Rm{3-0}; 1601} 1602 1603class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1604 dag oops, dag iops, InstrItinClass itin, 1605 string opc, string dt, string asm, string cstr, list<dag> pattern> 1606 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc, 1607 dt, asm, cstr, pattern> { 1608 bits<3> lane; 1609} 1610 1611class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr> 1612 : InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr, 1613 itin> { 1614 let OutOperandList = oops; 1615 let InOperandList = !con(iops, (ins pred:$p)); 1616 list<Predicate> Predicates = [HasNEON]; 1617} 1618 1619class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr, 1620 list<dag> pattern> 1621 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr, 1622 itin> { 1623 let OutOperandList = oops; 1624 let InOperandList = !con(iops, (ins pred:$p)); 1625 let Pattern = pattern; 1626 list<Predicate> Predicates = [HasNEON]; 1627} 1628 1629class NDataI<dag oops, dag iops, Format f, InstrItinClass itin, 1630 string opc, string dt, string asm, string cstr, list<dag> pattern> 1631 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr, 1632 pattern> { 1633 let Inst{31-25} = 0b1111001; 1634 let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1635} 1636 1637class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin, 1638 string opc, string asm, string cstr, list<dag> pattern> 1639 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm, 1640 cstr, pattern> { 1641 let Inst{31-25} = 0b1111001; 1642 let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1643} 1644 1645// NEON "one register and a modified immediate" format. 1646class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1647 bit op5, bit op4, 1648 dag oops, dag iops, InstrItinClass itin, 1649 string opc, string dt, string asm, string cstr, 1650 list<dag> pattern> 1651 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> { 1652 let Inst{23} = op23; 1653 let Inst{21-19} = op21_19; 1654 let Inst{11-8} = op11_8; 1655 let Inst{7} = op7; 1656 let Inst{6} = op6; 1657 let Inst{5} = op5; 1658 let Inst{4} = op4; 1659 1660 // Instruction operands. 1661 bits<5> Vd; 1662 bits<13> SIMM; 1663 1664 let Inst{15-12} = Vd{3-0}; 1665 let Inst{22} = Vd{4}; 1666 let Inst{24} = SIMM{7}; 1667 let Inst{18-16} = SIMM{6-4}; 1668 let Inst{3-0} = SIMM{3-0}; 1669} 1670 1671// NEON 2 vector register format. 1672class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1673 bits<5> op11_7, bit op6, bit op4, 1674 dag oops, dag iops, InstrItinClass itin, 1675 string opc, string dt, string asm, string cstr, list<dag> pattern> 1676 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> { 1677 let Inst{24-23} = op24_23; 1678 let Inst{21-20} = op21_20; 1679 let Inst{19-18} = op19_18; 1680 let Inst{17-16} = op17_16; 1681 let Inst{11-7} = op11_7; 1682 let Inst{6} = op6; 1683 let Inst{4} = op4; 1684 1685 // Instruction operands. 1686 bits<5> Vd; 1687 bits<5> Vm; 1688 1689 let Inst{15-12} = Vd{3-0}; 1690 let Inst{22} = Vd{4}; 1691 let Inst{3-0} = Vm{3-0}; 1692 let Inst{5} = Vm{4}; 1693} 1694 1695// Same as N2V except it doesn't have a datatype suffix. 1696class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1697 bits<5> op11_7, bit op6, bit op4, 1698 dag oops, dag iops, InstrItinClass itin, 1699 string opc, string asm, string cstr, list<dag> pattern> 1700 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> { 1701 let Inst{24-23} = op24_23; 1702 let Inst{21-20} = op21_20; 1703 let Inst{19-18} = op19_18; 1704 let Inst{17-16} = op17_16; 1705 let Inst{11-7} = op11_7; 1706 let Inst{6} = op6; 1707 let Inst{4} = op4; 1708 1709 // Instruction operands. 1710 bits<5> Vd; 1711 bits<5> Vm; 1712 1713 let Inst{15-12} = Vd{3-0}; 1714 let Inst{22} = Vd{4}; 1715 let Inst{3-0} = Vm{3-0}; 1716 let Inst{5} = Vm{4}; 1717} 1718 1719// NEON 2 vector register with immediate. 1720class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 1721 dag oops, dag iops, Format f, InstrItinClass itin, 1722 string opc, string dt, string asm, string cstr, list<dag> pattern> 1723 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1724 let Inst{24} = op24; 1725 let Inst{23} = op23; 1726 let Inst{11-8} = op11_8; 1727 let Inst{7} = op7; 1728 let Inst{6} = op6; 1729 let Inst{4} = op4; 1730 1731 // Instruction operands. 1732 bits<5> Vd; 1733 bits<5> Vm; 1734 bits<6> SIMM; 1735 1736 let Inst{15-12} = Vd{3-0}; 1737 let Inst{22} = Vd{4}; 1738 let Inst{3-0} = Vm{3-0}; 1739 let Inst{5} = Vm{4}; 1740 let Inst{21-16} = SIMM{5-0}; 1741} 1742 1743// NEON 3 vector register format. 1744 1745class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1746 dag oops, dag iops, Format f, InstrItinClass itin, 1747 string opc, string dt, string asm, string cstr, list<dag> pattern> 1748 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1749 let Inst{24} = op24; 1750 let Inst{23} = op23; 1751 let Inst{21-20} = op21_20; 1752 let Inst{11-8} = op11_8; 1753 let Inst{6} = op6; 1754 let Inst{4} = op4; 1755} 1756 1757class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1758 dag oops, dag iops, Format f, InstrItinClass itin, 1759 string opc, string dt, string asm, string cstr, list<dag> pattern> 1760 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1761 oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1762 1763 // Instruction operands. 1764 bits<5> Vd; 1765 bits<5> Vn; 1766 bits<5> Vm; 1767 1768 let Inst{15-12} = Vd{3-0}; 1769 let Inst{22} = Vd{4}; 1770 let Inst{19-16} = Vn{3-0}; 1771 let Inst{7} = Vn{4}; 1772 let Inst{3-0} = Vm{3-0}; 1773 let Inst{5} = Vm{4}; 1774} 1775 1776class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1777 dag oops, dag iops, Format f, InstrItinClass itin, 1778 string opc, string dt, string asm, string cstr, list<dag> pattern> 1779 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1780 oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1781 1782 // Instruction operands. 1783 bits<5> Vd; 1784 bits<5> Vn; 1785 bits<5> Vm; 1786 bit lane; 1787 1788 let Inst{15-12} = Vd{3-0}; 1789 let Inst{22} = Vd{4}; 1790 let Inst{19-16} = Vn{3-0}; 1791 let Inst{7} = Vn{4}; 1792 let Inst{3-0} = Vm{3-0}; 1793 let Inst{5} = lane; 1794} 1795 1796class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1797 dag oops, dag iops, Format f, InstrItinClass itin, 1798 string opc, string dt, string asm, string cstr, list<dag> pattern> 1799 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1800 oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1801 1802 // Instruction operands. 1803 bits<5> Vd; 1804 bits<5> Vn; 1805 bits<5> Vm; 1806 bits<2> lane; 1807 1808 let Inst{15-12} = Vd{3-0}; 1809 let Inst{22} = Vd{4}; 1810 let Inst{19-16} = Vn{3-0}; 1811 let Inst{7} = Vn{4}; 1812 let Inst{2-0} = Vm{2-0}; 1813 let Inst{5} = lane{1}; 1814 let Inst{3} = lane{0}; 1815} 1816 1817// Same as N3V except it doesn't have a data type suffix. 1818class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1819 bit op4, 1820 dag oops, dag iops, Format f, InstrItinClass itin, 1821 string opc, string asm, string cstr, list<dag> pattern> 1822 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> { 1823 let Inst{24} = op24; 1824 let Inst{23} = op23; 1825 let Inst{21-20} = op21_20; 1826 let Inst{11-8} = op11_8; 1827 let Inst{6} = op6; 1828 let Inst{4} = op4; 1829 1830 // Instruction operands. 1831 bits<5> Vd; 1832 bits<5> Vn; 1833 bits<5> Vm; 1834 1835 let Inst{15-12} = Vd{3-0}; 1836 let Inst{22} = Vd{4}; 1837 let Inst{19-16} = Vn{3-0}; 1838 let Inst{7} = Vn{4}; 1839 let Inst{3-0} = Vm{3-0}; 1840 let Inst{5} = Vm{4}; 1841} 1842 1843// NEON VMOVs between scalar and core registers. 1844class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1845 dag oops, dag iops, Format f, InstrItinClass itin, 1846 string opc, string dt, string asm, list<dag> pattern> 1847 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, NeonDomain, 1848 "", itin> { 1849 let Inst{27-20} = opcod1; 1850 let Inst{11-8} = opcod2; 1851 let Inst{6-5} = opcod3; 1852 let Inst{4} = 1; 1853 // A8.6.303, A8.6.328, A8.6.329 1854 let Inst{3-0} = 0b0000; 1855 1856 let OutOperandList = oops; 1857 let InOperandList = !con(iops, (ins pred:$p)); 1858 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1859 let Pattern = pattern; 1860 list<Predicate> Predicates = [HasNEON]; 1861 1862 let PostEncoderMethod = "NEONThumb2DupPostEncoder"; 1863 1864 bits<5> V; 1865 bits<4> R; 1866 bits<4> p; 1867 bits<4> lane; 1868 1869 let Inst{31-28} = p{3-0}; 1870 let Inst{7} = V{4}; 1871 let Inst{19-16} = V{3-0}; 1872 let Inst{15-12} = R{3-0}; 1873} 1874class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1875 dag oops, dag iops, InstrItinClass itin, 1876 string opc, string dt, string asm, list<dag> pattern> 1877 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin, 1878 opc, dt, asm, pattern>; 1879class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1880 dag oops, dag iops, InstrItinClass itin, 1881 string opc, string dt, string asm, list<dag> pattern> 1882 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin, 1883 opc, dt, asm, pattern>; 1884class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1885 dag oops, dag iops, InstrItinClass itin, 1886 string opc, string dt, string asm, list<dag> pattern> 1887 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin, 1888 opc, dt, asm, pattern>; 1889 1890// Vector Duplicate Lane (from scalar to all elements) 1891class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops, 1892 InstrItinClass itin, string opc, string dt, string asm, 1893 list<dag> pattern> 1894 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> { 1895 let Inst{24-23} = 0b11; 1896 let Inst{21-20} = 0b11; 1897 let Inst{19-16} = op19_16; 1898 let Inst{11-7} = 0b11000; 1899 let Inst{6} = op6; 1900 let Inst{4} = 0; 1901 1902 bits<5> Vd; 1903 bits<5> Vm; 1904 bits<4> lane; 1905 1906 let Inst{22} = Vd{4}; 1907 let Inst{15-12} = Vd{3-0}; 1908 let Inst{5} = Vm{4}; 1909 let Inst{3-0} = Vm{3-0}; 1910} 1911 1912// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON 1913// for single-precision FP. 1914class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { 1915 list<Predicate> Predicates = [HasNEON,UseNEONForFP]; 1916} 1917