ARMInstrFormats.td revision 218893
1//===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// ARM Instruction Format Definitions. 13// 14 15// Format specifies the encoding used by the instruction. This is part of the 16// ad-hoc solution used to emit machine instruction encodings by our machine 17// code emitter. 18class Format<bits<6> val> { 19 bits<6> Value = val; 20} 21 22def Pseudo : Format<0>; 23def MulFrm : Format<1>; 24def BrFrm : Format<2>; 25def BrMiscFrm : Format<3>; 26 27def DPFrm : Format<4>; 28def DPSoRegFrm : Format<5>; 29 30def LdFrm : Format<6>; 31def StFrm : Format<7>; 32def LdMiscFrm : Format<8>; 33def StMiscFrm : Format<9>; 34def LdStMulFrm : Format<10>; 35 36def LdStExFrm : Format<11>; 37 38def ArithMiscFrm : Format<12>; 39def SatFrm : Format<13>; 40def ExtFrm : Format<14>; 41 42def VFPUnaryFrm : Format<15>; 43def VFPBinaryFrm : Format<16>; 44def VFPConv1Frm : Format<17>; 45def VFPConv2Frm : Format<18>; 46def VFPConv3Frm : Format<19>; 47def VFPConv4Frm : Format<20>; 48def VFPConv5Frm : Format<21>; 49def VFPLdStFrm : Format<22>; 50def VFPLdStMulFrm : Format<23>; 51def VFPMiscFrm : Format<24>; 52 53def ThumbFrm : Format<25>; 54def MiscFrm : Format<26>; 55 56def NGetLnFrm : Format<27>; 57def NSetLnFrm : Format<28>; 58def NDupFrm : Format<29>; 59def NLdStFrm : Format<30>; 60def N1RegModImmFrm: Format<31>; 61def N2RegFrm : Format<32>; 62def NVCVTFrm : Format<33>; 63def NVDupLnFrm : Format<34>; 64def N2RegVShLFrm : Format<35>; 65def N2RegVShRFrm : Format<36>; 66def N3RegFrm : Format<37>; 67def N3RegVShFrm : Format<38>; 68def NVExtFrm : Format<39>; 69def NVMulSLFrm : Format<40>; 70def NVTBLFrm : Format<41>; 71 72// Misc flags. 73 74// The instruction has an Rn register operand. 75// UnaryDP - Indicates this is a unary data processing instruction, i.e. 76// it doesn't have a Rn operand. 77class UnaryDP { bit isUnaryDataProc = 1; } 78 79// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 80// a 16-bit Thumb instruction if certain conditions are met. 81class Xform16Bit { bit canXformTo16Bit = 1; } 82 83//===----------------------------------------------------------------------===// 84// ARM Instruction flags. These need to match ARMBaseInstrInfo.h. 85// 86 87// FIXME: Once the JIT is MC-ized, these can go away. 88// Addressing mode. 89class AddrMode<bits<5> val> { 90 bits<5> Value = val; 91} 92def AddrModeNone : AddrMode<0>; 93def AddrMode1 : AddrMode<1>; 94def AddrMode2 : AddrMode<2>; 95def AddrMode3 : AddrMode<3>; 96def AddrMode4 : AddrMode<4>; 97def AddrMode5 : AddrMode<5>; 98def AddrMode6 : AddrMode<6>; 99def AddrModeT1_1 : AddrMode<7>; 100def AddrModeT1_2 : AddrMode<8>; 101def AddrModeT1_4 : AddrMode<9>; 102def AddrModeT1_s : AddrMode<10>; 103def AddrModeT2_i12 : AddrMode<11>; 104def AddrModeT2_i8 : AddrMode<12>; 105def AddrModeT2_so : AddrMode<13>; 106def AddrModeT2_pc : AddrMode<14>; 107def AddrModeT2_i8s4 : AddrMode<15>; 108def AddrMode_i12 : AddrMode<16>; 109 110// Instruction size. 111class SizeFlagVal<bits<3> val> { 112 bits<3> Value = val; 113} 114def SizeInvalid : SizeFlagVal<0>; // Unset. 115def SizeSpecial : SizeFlagVal<1>; // Pseudo or special. 116def Size8Bytes : SizeFlagVal<2>; 117def Size4Bytes : SizeFlagVal<3>; 118def Size2Bytes : SizeFlagVal<4>; 119 120// Load / store index mode. 121class IndexMode<bits<2> val> { 122 bits<2> Value = val; 123} 124def IndexModeNone : IndexMode<0>; 125def IndexModePre : IndexMode<1>; 126def IndexModePost : IndexMode<2>; 127def IndexModeUpd : IndexMode<3>; 128 129// Instruction execution domain. 130class Domain<bits<2> val> { 131 bits<2> Value = val; 132} 133def GenericDomain : Domain<0>; 134def VFPDomain : Domain<1>; // Instructions in VFP domain only 135def NeonDomain : Domain<2>; // Instructions in Neon domain only 136def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains 137 138//===----------------------------------------------------------------------===// 139// ARM special operands. 140// 141 142def CondCodeOperand : AsmOperandClass { 143 let Name = "CondCode"; 144 let SuperClasses = []; 145} 146 147def CCOutOperand : AsmOperandClass { 148 let Name = "CCOut"; 149 let SuperClasses = []; 150} 151 152def MemBarrierOptOperand : AsmOperandClass { 153 let Name = "MemBarrierOpt"; 154 let SuperClasses = []; 155 let ParserMethod = "tryParseMemBarrierOptOperand"; 156} 157 158def ProcIFlagsOperand : AsmOperandClass { 159 let Name = "ProcIFlags"; 160 let SuperClasses = []; 161 let ParserMethod = "tryParseProcIFlagsOperand"; 162} 163 164def MSRMaskOperand : AsmOperandClass { 165 let Name = "MSRMask"; 166 let SuperClasses = []; 167 let ParserMethod = "tryParseMSRMaskOperand"; 168} 169 170// ARM imod and iflag operands, used only by the CPS instruction. 171def imod_op : Operand<i32> { 172 let PrintMethod = "printCPSIMod"; 173} 174 175def iflags_op : Operand<i32> { 176 let PrintMethod = "printCPSIFlag"; 177 let ParserMatchClass = ProcIFlagsOperand; 178} 179 180// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 181// register whose default is 0 (no register). 182def pred : PredicateOperand<OtherVT, (ops i32imm, CCR), 183 (ops (i32 14), (i32 zero_reg))> { 184 let PrintMethod = "printPredicateOperand"; 185 let ParserMatchClass = CondCodeOperand; 186} 187 188// Conditional code result for instructions whose 's' bit is set, e.g. subs. 189def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 190 let EncoderMethod = "getCCOutOpValue"; 191 let PrintMethod = "printSBitModifierOperand"; 192 let ParserMatchClass = CCOutOperand; 193} 194 195// Same as cc_out except it defaults to setting CPSR. 196def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 197 let EncoderMethod = "getCCOutOpValue"; 198 let PrintMethod = "printSBitModifierOperand"; 199 let ParserMatchClass = CCOutOperand; 200} 201 202// ARM special operands for disassembly only. 203// 204def setend_op : Operand<i32> { 205 let PrintMethod = "printSetendOperand"; 206} 207 208def cps_opt : Operand<i32> { 209 let PrintMethod = "printCPSOptionOperand"; 210} 211 212def msr_mask : Operand<i32> { 213 let PrintMethod = "printMSRMaskOperand"; 214 let ParserMatchClass = MSRMaskOperand; 215} 216 217// A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0. 218// The neg_zero operand translates -0 to -1, -1 to -2, ..., etc. 219def neg_zero : Operand<i32> { 220 let PrintMethod = "printNegZeroOperand"; 221} 222 223//===----------------------------------------------------------------------===// 224// ARM Instruction templates. 225// 226 227class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im, 228 Format f, Domain d, string cstr, InstrItinClass itin> 229 : Instruction { 230 let Namespace = "ARM"; 231 232 AddrMode AM = am; 233 SizeFlagVal SZ = sz; 234 IndexMode IM = im; 235 bits<2> IndexModeBits = IM.Value; 236 Format F = f; 237 bits<6> Form = F.Value; 238 Domain D = d; 239 bit isUnaryDataProc = 0; 240 bit canXformTo16Bit = 0; 241 242 // If this is a pseudo instruction, mark it isCodeGenOnly. 243 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo"); 244 245 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h. 246 let TSFlags{4-0} = AM.Value; 247 let TSFlags{7-5} = SZ.Value; 248 let TSFlags{9-8} = IndexModeBits; 249 let TSFlags{15-10} = Form; 250 let TSFlags{16} = isUnaryDataProc; 251 let TSFlags{17} = canXformTo16Bit; 252 let TSFlags{19-18} = D.Value; 253 254 let Constraints = cstr; 255 let Itinerary = itin; 256} 257 258class Encoding { 259 field bits<32> Inst; 260} 261 262class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im, 263 Format f, Domain d, string cstr, InstrItinClass itin> 264 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding; 265 266// This Encoding-less class is used by Thumb1 to specify the encoding bits later 267// on by adding flavors to specific instructions. 268class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im, 269 Format f, Domain d, string cstr, InstrItinClass itin> 270 : InstTemplate<am, sz, im, f, d, cstr, itin>; 271 272class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern> 273 // FIXME: This really should derive from InstTemplate instead, as pseudos 274 // don't need encoding information. TableGen doesn't like that 275 // currently. Need to figure out why and fix it. 276 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain, 277 "", itin> { 278 let OutOperandList = oops; 279 let InOperandList = iops; 280 let Pattern = pattern; 281} 282 283// PseudoInst that's ARM-mode only. 284class ARMPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin, 285 list<dag> pattern> 286 : PseudoInst<oops, iops, itin, pattern> { 287 let SZ = sz; 288 list<Predicate> Predicates = [IsARM]; 289} 290 291// PseudoInst that's Thumb-mode only. 292class tPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin, 293 list<dag> pattern> 294 : PseudoInst<oops, iops, itin, pattern> { 295 let SZ = sz; 296 list<Predicate> Predicates = [IsThumb]; 297} 298 299// PseudoInst that's Thumb2-mode only. 300class t2PseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin, 301 list<dag> pattern> 302 : PseudoInst<oops, iops, itin, pattern> { 303 let SZ = sz; 304 list<Predicate> Predicates = [IsThumb2]; 305} 306// Almost all ARM instructions are predicable. 307class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 308 IndexMode im, Format f, InstrItinClass itin, 309 string opc, string asm, string cstr, 310 list<dag> pattern> 311 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 312 bits<4> p; 313 let Inst{31-28} = p; 314 let OutOperandList = oops; 315 let InOperandList = !con(iops, (ins pred:$p)); 316 let AsmString = !strconcat(opc, "${p}", asm); 317 let Pattern = pattern; 318 list<Predicate> Predicates = [IsARM]; 319} 320 321// A few are not predicable 322class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 323 IndexMode im, Format f, InstrItinClass itin, 324 string opc, string asm, string cstr, 325 list<dag> pattern> 326 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 327 let OutOperandList = oops; 328 let InOperandList = iops; 329 let AsmString = !strconcat(opc, asm); 330 let Pattern = pattern; 331 let isPredicable = 0; 332 list<Predicate> Predicates = [IsARM]; 333} 334 335// Same as I except it can optionally modify CPSR. Note it's modeled as an input 336// operand since by default it's a zero register. It will become an implicit def 337// once it's "flipped". 338class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 339 IndexMode im, Format f, InstrItinClass itin, 340 string opc, string asm, string cstr, 341 list<dag> pattern> 342 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 343 bits<4> p; // Predicate operand 344 bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 345 let Inst{31-28} = p; 346 let Inst{20} = s; 347 348 let OutOperandList = oops; 349 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 350 let AsmString = !strconcat(opc, "${s}${p}", asm); 351 let Pattern = pattern; 352 list<Predicate> Predicates = [IsARM]; 353} 354 355// Special cases 356class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 357 IndexMode im, Format f, InstrItinClass itin, 358 string asm, string cstr, list<dag> pattern> 359 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 360 let OutOperandList = oops; 361 let InOperandList = iops; 362 let AsmString = asm; 363 let Pattern = pattern; 364 list<Predicate> Predicates = [IsARM]; 365} 366 367class AI<dag oops, dag iops, Format f, InstrItinClass itin, 368 string opc, string asm, list<dag> pattern> 369 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 370 opc, asm, "", pattern>; 371class AsI<dag oops, dag iops, Format f, InstrItinClass itin, 372 string opc, string asm, list<dag> pattern> 373 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 374 opc, asm, "", pattern>; 375class AXI<dag oops, dag iops, Format f, InstrItinClass itin, 376 string asm, list<dag> pattern> 377 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 378 asm, "", pattern>; 379class AInoP<dag oops, dag iops, Format f, InstrItinClass itin, 380 string opc, string asm, list<dag> pattern> 381 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 382 opc, asm, "", pattern>; 383 384// Ctrl flow instructions 385class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 386 string opc, string asm, list<dag> pattern> 387 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 388 opc, asm, "", pattern> { 389 let Inst{27-24} = opcod; 390} 391class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 392 string asm, list<dag> pattern> 393 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 394 asm, "", pattern> { 395 let Inst{27-24} = opcod; 396} 397 398// BR_JT instructions 399class JTI<dag oops, dag iops, InstrItinClass itin, 400 string asm, list<dag> pattern> 401 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin, 402 asm, "", pattern>; 403 404// Atomic load/store instructions 405class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 406 string opc, string asm, list<dag> pattern> 407 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 408 opc, asm, "", pattern> { 409 bits<4> Rt; 410 bits<4> Rn; 411 let Inst{27-23} = 0b00011; 412 let Inst{22-21} = opcod; 413 let Inst{20} = 1; 414 let Inst{19-16} = Rn; 415 let Inst{15-12} = Rt; 416 let Inst{11-0} = 0b111110011111; 417} 418class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 419 string opc, string asm, list<dag> pattern> 420 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 421 opc, asm, "", pattern> { 422 bits<4> Rd; 423 bits<4> Rt; 424 bits<4> Rn; 425 let Inst{27-23} = 0b00011; 426 let Inst{22-21} = opcod; 427 let Inst{20} = 0; 428 let Inst{19-16} = Rn; 429 let Inst{15-12} = Rd; 430 let Inst{11-4} = 0b11111001; 431 let Inst{3-0} = Rt; 432} 433class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern> 434 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> { 435 bits<4> Rt; 436 bits<4> Rt2; 437 bits<4> Rn; 438 let Inst{27-23} = 0b00010; 439 let Inst{22} = b; 440 let Inst{21-20} = 0b00; 441 let Inst{19-16} = Rn; 442 let Inst{15-12} = Rt; 443 let Inst{11-4} = 0b00001001; 444 let Inst{3-0} = Rt2; 445} 446 447// addrmode1 instructions 448class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 449 string opc, string asm, list<dag> pattern> 450 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 451 opc, asm, "", pattern> { 452 let Inst{24-21} = opcod; 453 let Inst{27-26} = 0b00; 454} 455class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 456 string opc, string asm, list<dag> pattern> 457 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 458 opc, asm, "", pattern> { 459 let Inst{24-21} = opcod; 460 let Inst{27-26} = 0b00; 461} 462class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 463 string asm, list<dag> pattern> 464 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 465 asm, "", pattern> { 466 let Inst{24-21} = opcod; 467 let Inst{27-26} = 0b00; 468} 469 470// loads 471 472// LDR/LDRB/STR/STRB/... 473class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am, 474 Format f, InstrItinClass itin, string opc, string asm, 475 list<dag> pattern> 476 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm, 477 "", pattern> { 478 let Inst{27-25} = op; 479 let Inst{24} = 1; // 24 == P 480 // 23 == U 481 let Inst{22} = isByte; 482 let Inst{21} = 0; // 21 == W 483 let Inst{20} = isLd; 484} 485// Indexed load/stores 486class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops, 487 IndexMode im, Format f, InstrItinClass itin, string opc, 488 string asm, string cstr, list<dag> pattern> 489 : I<oops, iops, AddrMode2, Size4Bytes, im, f, itin, 490 opc, asm, cstr, pattern> { 491 bits<4> Rt; 492 let Inst{27-26} = 0b01; 493 let Inst{24} = isPre; // P bit 494 let Inst{22} = isByte; // B bit 495 let Inst{21} = isPre; // W bit 496 let Inst{20} = isLd; // L bit 497 let Inst{15-12} = Rt; 498} 499class AI2stridx<bit isByte, bit isPre, dag oops, dag iops, 500 IndexMode im, Format f, InstrItinClass itin, string opc, 501 string asm, string cstr, list<dag> pattern> 502 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 503 pattern> { 504 // AM2 store w/ two operands: (GPR, am2offset) 505 // {13} 1 == Rm, 0 == imm12 506 // {12} isAdd 507 // {11-0} imm12/Rm 508 bits<14> offset; 509 bits<4> Rn; 510 let Inst{25} = offset{13}; 511 let Inst{23} = offset{12}; 512 let Inst{19-16} = Rn; 513 let Inst{11-0} = offset{11-0}; 514} 515 516// addrmode3 instructions 517class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f, 518 InstrItinClass itin, string opc, string asm, list<dag> pattern> 519 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 520 opc, asm, "", pattern> { 521 bits<14> addr; 522 bits<4> Rt; 523 let Inst{27-25} = 0b000; 524 let Inst{24} = 1; // P bit 525 let Inst{23} = addr{8}; // U bit 526 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 527 let Inst{21} = 0; // W bit 528 let Inst{20} = op20; // L bit 529 let Inst{19-16} = addr{12-9}; // Rn 530 let Inst{15-12} = Rt; // Rt 531 let Inst{11-8} = addr{7-4}; // imm7_4/zero 532 let Inst{7-4} = op; 533 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 534} 535 536class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops, 537 IndexMode im, Format f, InstrItinClass itin, string opc, 538 string asm, string cstr, list<dag> pattern> 539 : I<oops, iops, AddrMode3, Size4Bytes, im, f, itin, 540 opc, asm, cstr, pattern> { 541 bits<4> Rt; 542 let Inst{27-25} = 0b000; 543 let Inst{24} = isPre; // P bit 544 let Inst{21} = isPre; // W bit 545 let Inst{20} = op20; // L bit 546 let Inst{15-12} = Rt; // Rt 547 let Inst{7-4} = op; 548} 549class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops, 550 IndexMode im, Format f, InstrItinClass itin, string opc, 551 string asm, string cstr, list<dag> pattern> 552 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 553 pattern> { 554 // AM3 store w/ two operands: (GPR, am3offset) 555 bits<14> offset; 556 bits<4> Rt; 557 bits<4> Rn; 558 let Inst{27-25} = 0b000; 559 let Inst{23} = offset{8}; 560 let Inst{22} = offset{9}; 561 let Inst{19-16} = Rn; 562 let Inst{15-12} = Rt; // Rt 563 let Inst{11-8} = offset{7-4}; // imm7_4/zero 564 let Inst{7-4} = op; 565 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 566} 567 568// stores 569class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin, 570 string opc, string asm, list<dag> pattern> 571 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 572 opc, asm, "", pattern> { 573 bits<14> addr; 574 bits<4> Rt; 575 let Inst{27-25} = 0b000; 576 let Inst{24} = 1; // P bit 577 let Inst{23} = addr{8}; // U bit 578 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 579 let Inst{21} = 0; // W bit 580 let Inst{20} = 0; // L bit 581 let Inst{19-16} = addr{12-9}; // Rn 582 let Inst{15-12} = Rt; // Rt 583 let Inst{11-8} = addr{7-4}; // imm7_4/zero 584 let Inst{7-4} = op; 585 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 586} 587 588// Pre-indexed stores 589class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin, 590 string opc, string asm, string cstr, list<dag> pattern> 591 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 592 opc, asm, cstr, pattern> { 593 let Inst{4} = 1; 594 let Inst{5} = 1; // H bit 595 let Inst{6} = 0; // S bit 596 let Inst{7} = 1; 597 let Inst{20} = 0; // L bit 598 let Inst{21} = 1; // W bit 599 let Inst{24} = 1; // P bit 600 let Inst{27-25} = 0b000; 601} 602class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin, 603 string opc, string asm, string cstr, list<dag> pattern> 604 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 605 opc, asm, cstr, pattern> { 606 let Inst{4} = 1; 607 let Inst{5} = 1; // H bit 608 let Inst{6} = 1; // S bit 609 let Inst{7} = 1; 610 let Inst{20} = 0; // L bit 611 let Inst{21} = 1; // W bit 612 let Inst{24} = 1; // P bit 613 let Inst{27-25} = 0b000; 614} 615 616// Post-indexed stores 617class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin, 618 string opc, string asm, string cstr, list<dag> pattern> 619 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 620 opc, asm, cstr,pattern> { 621 let Inst{4} = 1; 622 let Inst{5} = 1; // H bit 623 let Inst{6} = 0; // S bit 624 let Inst{7} = 1; 625 let Inst{20} = 0; // L bit 626 let Inst{21} = 0; // W bit 627 let Inst{24} = 0; // P bit 628 let Inst{27-25} = 0b000; 629} 630class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin, 631 string opc, string asm, string cstr, list<dag> pattern> 632 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 633 opc, asm, cstr, pattern> { 634 let Inst{4} = 1; 635 let Inst{5} = 1; // H bit 636 let Inst{6} = 1; // S bit 637 let Inst{7} = 1; 638 let Inst{20} = 0; // L bit 639 let Inst{21} = 0; // W bit 640 let Inst{24} = 0; // P bit 641 let Inst{27-25} = 0b000; 642} 643 644// addrmode4 instructions 645class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, 646 string asm, string cstr, list<dag> pattern> 647 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, asm, cstr, pattern> { 648 bits<4> p; 649 bits<16> regs; 650 bits<4> Rn; 651 let Inst{31-28} = p; 652 let Inst{27-25} = 0b100; 653 let Inst{22} = 0; // S bit 654 let Inst{19-16} = Rn; 655 let Inst{15-0} = regs; 656} 657 658// Unsigned multiply, multiply-accumulate instructions. 659class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 660 string opc, string asm, list<dag> pattern> 661 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 662 opc, asm, "", pattern> { 663 let Inst{7-4} = 0b1001; 664 let Inst{20} = 0; // S bit 665 let Inst{27-21} = opcod; 666} 667class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 668 string opc, string asm, list<dag> pattern> 669 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 670 opc, asm, "", pattern> { 671 let Inst{7-4} = 0b1001; 672 let Inst{27-21} = opcod; 673} 674 675// Most significant word multiply 676class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 677 InstrItinClass itin, string opc, string asm, list<dag> pattern> 678 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 679 opc, asm, "", pattern> { 680 bits<4> Rd; 681 bits<4> Rn; 682 bits<4> Rm; 683 let Inst{7-4} = opc7_4; 684 let Inst{20} = 1; 685 let Inst{27-21} = opcod; 686 let Inst{19-16} = Rd; 687 let Inst{11-8} = Rm; 688 let Inst{3-0} = Rn; 689} 690// MSW multiple w/ Ra operand 691class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 692 InstrItinClass itin, string opc, string asm, list<dag> pattern> 693 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> { 694 bits<4> Ra; 695 let Inst{15-12} = Ra; 696} 697 698// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 699class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 700 InstrItinClass itin, string opc, string asm, list<dag> pattern> 701 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 702 opc, asm, "", pattern> { 703 bits<4> Rn; 704 bits<4> Rm; 705 let Inst{4} = 0; 706 let Inst{7} = 1; 707 let Inst{20} = 0; 708 let Inst{27-21} = opcod; 709 let Inst{6-5} = bit6_5; 710 let Inst{11-8} = Rm; 711 let Inst{3-0} = Rn; 712} 713class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 714 InstrItinClass itin, string opc, string asm, list<dag> pattern> 715 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 716 bits<4> Rd; 717 let Inst{19-16} = Rd; 718} 719 720// AMulxyI with Ra operand 721class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 722 InstrItinClass itin, string opc, string asm, list<dag> pattern> 723 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 724 bits<4> Ra; 725 let Inst{15-12} = Ra; 726} 727// SMLAL* 728class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 729 InstrItinClass itin, string opc, string asm, list<dag> pattern> 730 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 731 bits<4> RdLo; 732 bits<4> RdHi; 733 let Inst{19-16} = RdHi; 734 let Inst{15-12} = RdLo; 735} 736 737// Extend instructions. 738class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 739 string opc, string asm, list<dag> pattern> 740 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin, 741 opc, asm, "", pattern> { 742 // All AExtI instructions have Rd and Rm register operands. 743 bits<4> Rd; 744 bits<4> Rm; 745 let Inst{15-12} = Rd; 746 let Inst{3-0} = Rm; 747 let Inst{7-4} = 0b0111; 748 let Inst{9-8} = 0b00; 749 let Inst{27-20} = opcod; 750} 751 752// Misc Arithmetic instructions. 753class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops, 754 InstrItinClass itin, string opc, string asm, list<dag> pattern> 755 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin, 756 opc, asm, "", pattern> { 757 bits<4> Rd; 758 bits<4> Rm; 759 let Inst{27-20} = opcod; 760 let Inst{19-16} = 0b1111; 761 let Inst{15-12} = Rd; 762 let Inst{11-8} = 0b1111; 763 let Inst{7-4} = opc7_4; 764 let Inst{3-0} = Rm; 765} 766 767// PKH instructions 768class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin, 769 string opc, string asm, list<dag> pattern> 770 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin, 771 opc, asm, "", pattern> { 772 bits<4> Rd; 773 bits<4> Rn; 774 bits<4> Rm; 775 bits<8> sh; 776 let Inst{27-20} = opcod; 777 let Inst{19-16} = Rn; 778 let Inst{15-12} = Rd; 779 let Inst{11-7} = sh{7-3}; 780 let Inst{6} = tb; 781 let Inst{5-4} = 0b01; 782 let Inst{3-0} = Rm; 783} 784 785//===----------------------------------------------------------------------===// 786 787// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 788class ARMPat<dag pattern, dag result> : Pat<pattern, result> { 789 list<Predicate> Predicates = [IsARM]; 790} 791class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 792 list<Predicate> Predicates = [IsARM, HasV5TE]; 793} 794class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 795 list<Predicate> Predicates = [IsARM, HasV6]; 796} 797 798//===----------------------------------------------------------------------===// 799// Thumb Instruction Format Definitions. 800// 801 802class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 803 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 804 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 805 let OutOperandList = oops; 806 let InOperandList = iops; 807 let AsmString = asm; 808 let Pattern = pattern; 809 list<Predicate> Predicates = [IsThumb]; 810} 811 812// TI - Thumb instruction. 813class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 814 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 815 816// Two-address instructions 817class TIt<dag oops, dag iops, InstrItinClass itin, string asm, 818 list<dag> pattern> 819 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", 820 pattern>; 821 822// tBL, tBX 32-bit instructions 823class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, 824 dag oops, dag iops, InstrItinClass itin, string asm, 825 list<dag> pattern> 826 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, 827 Encoding { 828 let Inst{31-27} = opcod1; 829 let Inst{15-14} = opcod2; 830 let Inst{12} = opcod3; 831} 832 833// Move to/from coprocessor instructions 834class T1Cop<dag oops, dag iops, string asm, list<dag> pattern> 835 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, NoItinerary, asm, "", pattern>, 836 Encoding, Requires<[IsThumb, HasV6]> { 837 let Inst{31-28} = 0b1110; 838} 839 840// BR_JT instructions 841class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, 842 list<dag> pattern> 843 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 844 845// Thumb1 only 846class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 847 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 848 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 849 let OutOperandList = oops; 850 let InOperandList = iops; 851 let AsmString = asm; 852 let Pattern = pattern; 853 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 854} 855 856class T1I<dag oops, dag iops, InstrItinClass itin, 857 string asm, list<dag> pattern> 858 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 859class T1Ix2<dag oops, dag iops, InstrItinClass itin, 860 string asm, list<dag> pattern> 861 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 862 863// Two-address instructions 864class T1It<dag oops, dag iops, InstrItinClass itin, 865 string asm, string cstr, list<dag> pattern> 866 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, 867 asm, cstr, pattern>; 868 869// Thumb1 instruction that can either be predicated or set CPSR. 870class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 871 InstrItinClass itin, 872 string opc, string asm, string cstr, list<dag> pattern> 873 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 874 let OutOperandList = !con(oops, (outs s_cc_out:$s)); 875 let InOperandList = !con(iops, (ins pred:$p)); 876 let AsmString = !strconcat(opc, "${s}${p}", asm); 877 let Pattern = pattern; 878 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 879} 880 881class T1sI<dag oops, dag iops, InstrItinClass itin, 882 string opc, string asm, list<dag> pattern> 883 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 884 885// Two-address instructions 886class T1sIt<dag oops, dag iops, InstrItinClass itin, 887 string opc, string asm, list<dag> pattern> 888 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 889 "$Rn = $Rdn", pattern>; 890 891// Thumb1 instruction that can be predicated. 892class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 893 InstrItinClass itin, 894 string opc, string asm, string cstr, list<dag> pattern> 895 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 896 let OutOperandList = oops; 897 let InOperandList = !con(iops, (ins pred:$p)); 898 let AsmString = !strconcat(opc, "${p}", asm); 899 let Pattern = pattern; 900 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 901} 902 903class T1pI<dag oops, dag iops, InstrItinClass itin, 904 string opc, string asm, list<dag> pattern> 905 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 906 907// Two-address instructions 908class T1pIt<dag oops, dag iops, InstrItinClass itin, 909 string opc, string asm, list<dag> pattern> 910 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 911 "$Rn = $Rdn", pattern>; 912 913class T1pIs<dag oops, dag iops, 914 InstrItinClass itin, string opc, string asm, list<dag> pattern> 915 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>; 916 917class Encoding16 : Encoding { 918 let Inst{31-16} = 0x0000; 919} 920 921// A6.2 16-bit Thumb instruction encoding 922class T1Encoding<bits<6> opcode> : Encoding16 { 923 let Inst{15-10} = opcode; 924} 925 926// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. 927class T1General<bits<5> opcode> : Encoding16 { 928 let Inst{15-14} = 0b00; 929 let Inst{13-9} = opcode; 930} 931 932// A6.2.2 Data-processing encoding. 933class T1DataProcessing<bits<4> opcode> : Encoding16 { 934 let Inst{15-10} = 0b010000; 935 let Inst{9-6} = opcode; 936} 937 938// A6.2.3 Special data instructions and branch and exchange encoding. 939class T1Special<bits<4> opcode> : Encoding16 { 940 let Inst{15-10} = 0b010001; 941 let Inst{9-6} = opcode; 942} 943 944// A6.2.4 Load/store single data item encoding. 945class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { 946 let Inst{15-12} = opA; 947 let Inst{11-9} = opB; 948} 949class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative 950 951// Helper classes to encode Thumb1 loads and stores. For immediates, the 952// following bits are used for "opA" (see A6.2.4): 953// 954// 0b0110 => Immediate, 4 bytes 955// 0b1000 => Immediate, 2 bytes 956// 0b0111 => Immediate, 1 byte 957class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am, 958 InstrItinClass itin, string opc, string asm, 959 list<dag> pattern> 960 : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>, 961 T1LoadStore<0b0101, opcode> { 962 bits<3> Rt; 963 bits<8> addr; 964 let Inst{8-6} = addr{5-3}; // Rm 965 let Inst{5-3} = addr{2-0}; // Rn 966 let Inst{2-0} = Rt; 967} 968class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am, 969 InstrItinClass itin, string opc, string asm, 970 list<dag> pattern> 971 : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>, 972 T1LoadStore<opA, {opB,?,?}> { 973 bits<3> Rt; 974 bits<8> addr; 975 let Inst{10-6} = addr{7-3}; // imm5 976 let Inst{5-3} = addr{2-0}; // Rn 977 let Inst{2-0} = Rt; 978} 979 980// A6.2.5 Miscellaneous 16-bit instructions encoding. 981class T1Misc<bits<7> opcode> : Encoding16 { 982 let Inst{15-12} = 0b1011; 983 let Inst{11-5} = opcode; 984} 985 986// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 987class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 988 InstrItinClass itin, 989 string opc, string asm, string cstr, list<dag> pattern> 990 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 991 let OutOperandList = oops; 992 let InOperandList = !con(iops, (ins pred:$p)); 993 let AsmString = !strconcat(opc, "${p}", asm); 994 let Pattern = pattern; 995 list<Predicate> Predicates = [IsThumb2]; 996} 997 998// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an 999// input operand since by default it's a zero register. It will become an 1000// implicit def once it's "flipped". 1001// 1002// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 1003// more consistent. 1004class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1005 InstrItinClass itin, 1006 string opc, string asm, string cstr, list<dag> pattern> 1007 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1008 bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 1009 let Inst{20} = s; 1010 1011 let OutOperandList = oops; 1012 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 1013 let AsmString = !strconcat(opc, "${s}${p}", asm); 1014 let Pattern = pattern; 1015 list<Predicate> Predicates = [IsThumb2]; 1016} 1017 1018// Special cases 1019class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1020 InstrItinClass itin, 1021 string asm, string cstr, list<dag> pattern> 1022 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1023 let OutOperandList = oops; 1024 let InOperandList = iops; 1025 let AsmString = asm; 1026 let Pattern = pattern; 1027 list<Predicate> Predicates = [IsThumb2]; 1028} 1029 1030class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1031 InstrItinClass itin, 1032 string asm, string cstr, list<dag> pattern> 1033 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1034 let OutOperandList = oops; 1035 let InOperandList = iops; 1036 let AsmString = asm; 1037 let Pattern = pattern; 1038 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1039} 1040 1041class T2I<dag oops, dag iops, InstrItinClass itin, 1042 string opc, string asm, list<dag> pattern> 1043 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1044class T2Ii12<dag oops, dag iops, InstrItinClass itin, 1045 string opc, string asm, list<dag> pattern> 1046 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>; 1047class T2Ii8<dag oops, dag iops, InstrItinClass itin, 1048 string opc, string asm, list<dag> pattern> 1049 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>; 1050class T2Iso<dag oops, dag iops, InstrItinClass itin, 1051 string opc, string asm, list<dag> pattern> 1052 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>; 1053class T2Ipc<dag oops, dag iops, InstrItinClass itin, 1054 string opc, string asm, list<dag> pattern> 1055 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>; 1056class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin, 1057 string opc, string asm, list<dag> pattern> 1058 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "", 1059 pattern> { 1060 bits<4> Rt; 1061 bits<4> Rt2; 1062 bits<13> addr; 1063 let Inst{31-25} = 0b1110100; 1064 let Inst{24} = P; 1065 let Inst{23} = addr{8}; 1066 let Inst{22} = 1; 1067 let Inst{21} = W; 1068 let Inst{20} = isLoad; 1069 let Inst{19-16} = addr{12-9}; 1070 let Inst{15-12} = Rt{3-0}; 1071 let Inst{11-8} = Rt2{3-0}; 1072 let Inst{7-0} = addr{7-0}; 1073} 1074 1075class T2sI<dag oops, dag iops, InstrItinClass itin, 1076 string opc, string asm, list<dag> pattern> 1077 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1078 1079class T2XI<dag oops, dag iops, InstrItinClass itin, 1080 string asm, list<dag> pattern> 1081 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 1082class T2JTI<dag oops, dag iops, InstrItinClass itin, 1083 string asm, list<dag> pattern> 1084 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 1085 1086// Move to/from coprocessor instructions 1087class T2Cop<dag oops, dag iops, string asm, list<dag> pattern> 1088 : T2XI<oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2, HasV6]> { 1089 let Inst{31-28} = 0b1111; 1090} 1091 1092// Two-address instructions 1093class T2XIt<dag oops, dag iops, InstrItinClass itin, 1094 string asm, string cstr, list<dag> pattern> 1095 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>; 1096 1097// T2Iidxldst - Thumb2 indexed load / store instructions. 1098class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre, 1099 dag oops, dag iops, 1100 AddrMode am, IndexMode im, InstrItinClass itin, 1101 string opc, string asm, string cstr, list<dag> pattern> 1102 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> { 1103 let OutOperandList = oops; 1104 let InOperandList = !con(iops, (ins pred:$p)); 1105 let AsmString = !strconcat(opc, "${p}", asm); 1106 let Pattern = pattern; 1107 list<Predicate> Predicates = [IsThumb2]; 1108 let Inst{31-27} = 0b11111; 1109 let Inst{26-25} = 0b00; 1110 let Inst{24} = signed; 1111 let Inst{23} = 0; 1112 let Inst{22-21} = opcod; 1113 let Inst{20} = load; 1114 let Inst{11} = 1; 1115 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1116 let Inst{10} = pre; // The P bit. 1117 let Inst{8} = 1; // The W bit. 1118 1119 bits<9> addr; 1120 let Inst{7-0} = addr{7-0}; 1121 let Inst{9} = addr{8}; // Sign bit 1122 1123 bits<4> Rt; 1124 bits<4> Rn; 1125 let Inst{15-12} = Rt{3-0}; 1126 let Inst{19-16} = Rn{3-0}; 1127} 1128 1129// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 1130class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 1131 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T]; 1132} 1133 1134// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 1135class T1Pat<dag pattern, dag result> : Pat<pattern, result> { 1136 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1137} 1138 1139// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 1140class T2Pat<dag pattern, dag result> : Pat<pattern, result> { 1141 list<Predicate> Predicates = [IsThumb2]; 1142} 1143 1144//===----------------------------------------------------------------------===// 1145 1146//===----------------------------------------------------------------------===// 1147// ARM VFP Instruction templates. 1148// 1149 1150// Almost all VFP instructions are predicable. 1151class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1152 IndexMode im, Format f, InstrItinClass itin, 1153 string opc, string asm, string cstr, list<dag> pattern> 1154 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1155 bits<4> p; 1156 let Inst{31-28} = p; 1157 let OutOperandList = oops; 1158 let InOperandList = !con(iops, (ins pred:$p)); 1159 let AsmString = !strconcat(opc, "${p}", asm); 1160 let Pattern = pattern; 1161 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1162 list<Predicate> Predicates = [HasVFP2]; 1163} 1164 1165// Special cases 1166class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1167 IndexMode im, Format f, InstrItinClass itin, 1168 string asm, string cstr, list<dag> pattern> 1169 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1170 bits<4> p; 1171 let Inst{31-28} = p; 1172 let OutOperandList = oops; 1173 let InOperandList = iops; 1174 let AsmString = asm; 1175 let Pattern = pattern; 1176 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1177 list<Predicate> Predicates = [HasVFP2]; 1178} 1179 1180class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, 1181 string opc, string asm, list<dag> pattern> 1182 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 1183 opc, asm, "", pattern> { 1184 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1185} 1186 1187// ARM VFP addrmode5 loads and stores 1188class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1189 InstrItinClass itin, 1190 string opc, string asm, list<dag> pattern> 1191 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1192 VFPLdStFrm, itin, opc, asm, "", pattern> { 1193 // Instruction operands. 1194 bits<5> Dd; 1195 bits<13> addr; 1196 1197 // Encode instruction operands. 1198 let Inst{23} = addr{8}; // U (add = (U == '1')) 1199 let Inst{22} = Dd{4}; 1200 let Inst{19-16} = addr{12-9}; // Rn 1201 let Inst{15-12} = Dd{3-0}; 1202 let Inst{7-0} = addr{7-0}; // imm8 1203 1204 // TODO: Mark the instructions with the appropriate subtarget info. 1205 let Inst{27-24} = opcod1; 1206 let Inst{21-20} = opcod2; 1207 let Inst{11-9} = 0b101; 1208 let Inst{8} = 1; // Double precision 1209 1210 // Loads & stores operate on both NEON and VFP pipelines. 1211 let D = VFPNeonDomain; 1212} 1213 1214class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1215 InstrItinClass itin, 1216 string opc, string asm, list<dag> pattern> 1217 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1218 VFPLdStFrm, itin, opc, asm, "", pattern> { 1219 // Instruction operands. 1220 bits<5> Sd; 1221 bits<13> addr; 1222 1223 // Encode instruction operands. 1224 let Inst{23} = addr{8}; // U (add = (U == '1')) 1225 let Inst{22} = Sd{0}; 1226 let Inst{19-16} = addr{12-9}; // Rn 1227 let Inst{15-12} = Sd{4-1}; 1228 let Inst{7-0} = addr{7-0}; // imm8 1229 1230 // TODO: Mark the instructions with the appropriate subtarget info. 1231 let Inst{27-24} = opcod1; 1232 let Inst{21-20} = opcod2; 1233 let Inst{11-9} = 0b101; 1234 let Inst{8} = 0; // Single precision 1235 1236 // Loads & stores operate on both NEON and VFP pipelines. 1237 let D = VFPNeonDomain; 1238} 1239 1240// VFP Load / store multiple pseudo instructions. 1241class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr, 1242 list<dag> pattern> 1243 : InstARM<AddrMode4, Size4Bytes, IndexModeNone, Pseudo, VFPNeonDomain, 1244 cstr, itin> { 1245 let OutOperandList = oops; 1246 let InOperandList = !con(iops, (ins pred:$p)); 1247 let Pattern = pattern; 1248 list<Predicate> Predicates = [HasVFP2]; 1249} 1250 1251// Load / store multiple 1252class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1253 string asm, string cstr, list<dag> pattern> 1254 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im, 1255 VFPLdStMulFrm, itin, asm, cstr, pattern> { 1256 // Instruction operands. 1257 bits<4> Rn; 1258 bits<13> regs; 1259 1260 // Encode instruction operands. 1261 let Inst{19-16} = Rn; 1262 let Inst{22} = regs{12}; 1263 let Inst{15-12} = regs{11-8}; 1264 let Inst{7-0} = regs{7-0}; 1265 1266 // TODO: Mark the instructions with the appropriate subtarget info. 1267 let Inst{27-25} = 0b110; 1268 let Inst{11-9} = 0b101; 1269 let Inst{8} = 1; // Double precision 1270} 1271 1272class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1273 string asm, string cstr, list<dag> pattern> 1274 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im, 1275 VFPLdStMulFrm, itin, asm, cstr, pattern> { 1276 // Instruction operands. 1277 bits<4> Rn; 1278 bits<13> regs; 1279 1280 // Encode instruction operands. 1281 let Inst{19-16} = Rn; 1282 let Inst{22} = regs{8}; 1283 let Inst{15-12} = regs{12-9}; 1284 let Inst{7-0} = regs{7-0}; 1285 1286 // TODO: Mark the instructions with the appropriate subtarget info. 1287 let Inst{27-25} = 0b110; 1288 let Inst{11-9} = 0b101; 1289 let Inst{8} = 0; // Single precision 1290} 1291 1292// Double precision, unary 1293class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1294 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1295 string asm, list<dag> pattern> 1296 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1297 // Instruction operands. 1298 bits<5> Dd; 1299 bits<5> Dm; 1300 1301 // Encode instruction operands. 1302 let Inst{3-0} = Dm{3-0}; 1303 let Inst{5} = Dm{4}; 1304 let Inst{15-12} = Dd{3-0}; 1305 let Inst{22} = Dd{4}; 1306 1307 let Inst{27-23} = opcod1; 1308 let Inst{21-20} = opcod2; 1309 let Inst{19-16} = opcod3; 1310 let Inst{11-9} = 0b101; 1311 let Inst{8} = 1; // Double precision 1312 let Inst{7-6} = opcod4; 1313 let Inst{4} = opcod5; 1314} 1315 1316// Double precision, binary 1317class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1318 dag iops, InstrItinClass itin, string opc, string asm, 1319 list<dag> pattern> 1320 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1321 // Instruction operands. 1322 bits<5> Dd; 1323 bits<5> Dn; 1324 bits<5> Dm; 1325 1326 // Encode instruction operands. 1327 let Inst{3-0} = Dm{3-0}; 1328 let Inst{5} = Dm{4}; 1329 let Inst{19-16} = Dn{3-0}; 1330 let Inst{7} = Dn{4}; 1331 let Inst{15-12} = Dd{3-0}; 1332 let Inst{22} = Dd{4}; 1333 1334 let Inst{27-23} = opcod1; 1335 let Inst{21-20} = opcod2; 1336 let Inst{11-9} = 0b101; 1337 let Inst{8} = 1; // Double precision 1338 let Inst{6} = op6; 1339 let Inst{4} = op4; 1340} 1341 1342// Single precision, unary 1343class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1344 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1345 string asm, list<dag> pattern> 1346 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1347 // Instruction operands. 1348 bits<5> Sd; 1349 bits<5> Sm; 1350 1351 // Encode instruction operands. 1352 let Inst{3-0} = Sm{4-1}; 1353 let Inst{5} = Sm{0}; 1354 let Inst{15-12} = Sd{4-1}; 1355 let Inst{22} = Sd{0}; 1356 1357 let Inst{27-23} = opcod1; 1358 let Inst{21-20} = opcod2; 1359 let Inst{19-16} = opcod3; 1360 let Inst{11-9} = 0b101; 1361 let Inst{8} = 0; // Single precision 1362 let Inst{7-6} = opcod4; 1363 let Inst{4} = opcod5; 1364} 1365 1366// Single precision unary, if no NEON. Same as ASuI except not available if 1367// NEON is enabled. 1368class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1369 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1370 string asm, list<dag> pattern> 1371 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm, 1372 pattern> { 1373 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1374} 1375 1376// Single precision, binary 1377class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1378 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1379 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1380 // Instruction operands. 1381 bits<5> Sd; 1382 bits<5> Sn; 1383 bits<5> Sm; 1384 1385 // Encode instruction operands. 1386 let Inst{3-0} = Sm{4-1}; 1387 let Inst{5} = Sm{0}; 1388 let Inst{19-16} = Sn{4-1}; 1389 let Inst{7} = Sn{0}; 1390 let Inst{15-12} = Sd{4-1}; 1391 let Inst{22} = Sd{0}; 1392 1393 let Inst{27-23} = opcod1; 1394 let Inst{21-20} = opcod2; 1395 let Inst{11-9} = 0b101; 1396 let Inst{8} = 0; // Single precision 1397 let Inst{6} = op6; 1398 let Inst{4} = op4; 1399} 1400 1401// Single precision binary, if no NEON. Same as ASbI except not available if 1402// NEON is enabled. 1403class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1404 dag iops, InstrItinClass itin, string opc, string asm, 1405 list<dag> pattern> 1406 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1407 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1408 1409 // Instruction operands. 1410 bits<5> Sd; 1411 bits<5> Sn; 1412 bits<5> Sm; 1413 1414 // Encode instruction operands. 1415 let Inst{3-0} = Sm{4-1}; 1416 let Inst{5} = Sm{0}; 1417 let Inst{19-16} = Sn{4-1}; 1418 let Inst{7} = Sn{0}; 1419 let Inst{15-12} = Sd{4-1}; 1420 let Inst{22} = Sd{0}; 1421} 1422 1423// VFP conversion instructions 1424class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1425 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1426 list<dag> pattern> 1427 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { 1428 let Inst{27-23} = opcod1; 1429 let Inst{21-20} = opcod2; 1430 let Inst{19-16} = opcod3; 1431 let Inst{11-8} = opcod4; 1432 let Inst{6} = 1; 1433 let Inst{4} = 0; 1434} 1435 1436// VFP conversion between floating-point and fixed-point 1437class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 1438 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1439 list<dag> pattern> 1440 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { 1441 // size (fixed-point number): sx == 0 ? 16 : 32 1442 let Inst{7} = op5; // sx 1443} 1444 1445// VFP conversion instructions, if no NEON 1446class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1447 dag oops, dag iops, InstrItinClass itin, 1448 string opc, string asm, list<dag> pattern> 1449 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1450 pattern> { 1451 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1452} 1453 1454class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1455 InstrItinClass itin, 1456 string opc, string asm, list<dag> pattern> 1457 : VFPAI<oops, iops, f, itin, opc, asm, pattern> { 1458 let Inst{27-20} = opcod1; 1459 let Inst{11-8} = opcod2; 1460 let Inst{4} = 1; 1461} 1462 1463class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1464 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1465 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; 1466 1467class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1468 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1469 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; 1470 1471class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1472 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1473 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; 1474 1475class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1476 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1477 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; 1478 1479//===----------------------------------------------------------------------===// 1480 1481//===----------------------------------------------------------------------===// 1482// ARM NEON Instruction templates. 1483// 1484 1485class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1486 InstrItinClass itin, string opc, string dt, string asm, string cstr, 1487 list<dag> pattern> 1488 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> { 1489 let OutOperandList = oops; 1490 let InOperandList = !con(iops, (ins pred:$p)); 1491 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1492 let Pattern = pattern; 1493 list<Predicate> Predicates = [HasNEON]; 1494} 1495 1496// Same as NeonI except it does not have a "data type" specifier. 1497class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1498 InstrItinClass itin, string opc, string asm, string cstr, 1499 list<dag> pattern> 1500 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> { 1501 let OutOperandList = oops; 1502 let InOperandList = !con(iops, (ins pred:$p)); 1503 let AsmString = !strconcat(opc, "${p}", "\t", asm); 1504 let Pattern = pattern; 1505 list<Predicate> Predicates = [HasNEON]; 1506} 1507 1508class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1509 dag oops, dag iops, InstrItinClass itin, 1510 string opc, string dt, string asm, string cstr, list<dag> pattern> 1511 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm, 1512 cstr, pattern> { 1513 let Inst{31-24} = 0b11110100; 1514 let Inst{23} = op23; 1515 let Inst{21-20} = op21_20; 1516 let Inst{11-8} = op11_8; 1517 let Inst{7-4} = op7_4; 1518 1519 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder"; 1520 1521 bits<5> Vd; 1522 bits<6> Rn; 1523 bits<4> Rm; 1524 1525 let Inst{22} = Vd{4}; 1526 let Inst{15-12} = Vd{3-0}; 1527 let Inst{19-16} = Rn{3-0}; 1528 let Inst{3-0} = Rm{3-0}; 1529} 1530 1531class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1532 dag oops, dag iops, InstrItinClass itin, 1533 string opc, string dt, string asm, string cstr, list<dag> pattern> 1534 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc, 1535 dt, asm, cstr, pattern> { 1536 bits<3> lane; 1537} 1538 1539class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr> 1540 : InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr, 1541 itin> { 1542 let OutOperandList = oops; 1543 let InOperandList = !con(iops, (ins pred:$p)); 1544 list<Predicate> Predicates = [HasNEON]; 1545} 1546 1547class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr, 1548 list<dag> pattern> 1549 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr, 1550 itin> { 1551 let OutOperandList = oops; 1552 let InOperandList = !con(iops, (ins pred:$p)); 1553 let Pattern = pattern; 1554 list<Predicate> Predicates = [HasNEON]; 1555} 1556 1557class NDataI<dag oops, dag iops, Format f, InstrItinClass itin, 1558 string opc, string dt, string asm, string cstr, list<dag> pattern> 1559 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr, 1560 pattern> { 1561 let Inst{31-25} = 0b1111001; 1562 let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1563} 1564 1565class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin, 1566 string opc, string asm, string cstr, list<dag> pattern> 1567 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm, 1568 cstr, pattern> { 1569 let Inst{31-25} = 0b1111001; 1570 let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1571} 1572 1573// NEON "one register and a modified immediate" format. 1574class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1575 bit op5, bit op4, 1576 dag oops, dag iops, InstrItinClass itin, 1577 string opc, string dt, string asm, string cstr, 1578 list<dag> pattern> 1579 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> { 1580 let Inst{23} = op23; 1581 let Inst{21-19} = op21_19; 1582 let Inst{11-8} = op11_8; 1583 let Inst{7} = op7; 1584 let Inst{6} = op6; 1585 let Inst{5} = op5; 1586 let Inst{4} = op4; 1587 1588 // Instruction operands. 1589 bits<5> Vd; 1590 bits<13> SIMM; 1591 1592 let Inst{15-12} = Vd{3-0}; 1593 let Inst{22} = Vd{4}; 1594 let Inst{24} = SIMM{7}; 1595 let Inst{18-16} = SIMM{6-4}; 1596 let Inst{3-0} = SIMM{3-0}; 1597} 1598 1599// NEON 2 vector register format. 1600class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1601 bits<5> op11_7, bit op6, bit op4, 1602 dag oops, dag iops, InstrItinClass itin, 1603 string opc, string dt, string asm, string cstr, list<dag> pattern> 1604 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> { 1605 let Inst{24-23} = op24_23; 1606 let Inst{21-20} = op21_20; 1607 let Inst{19-18} = op19_18; 1608 let Inst{17-16} = op17_16; 1609 let Inst{11-7} = op11_7; 1610 let Inst{6} = op6; 1611 let Inst{4} = op4; 1612 1613 // Instruction operands. 1614 bits<5> Vd; 1615 bits<5> Vm; 1616 1617 let Inst{15-12} = Vd{3-0}; 1618 let Inst{22} = Vd{4}; 1619 let Inst{3-0} = Vm{3-0}; 1620 let Inst{5} = Vm{4}; 1621} 1622 1623// Same as N2V except it doesn't have a datatype suffix. 1624class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1625 bits<5> op11_7, bit op6, bit op4, 1626 dag oops, dag iops, InstrItinClass itin, 1627 string opc, string asm, string cstr, list<dag> pattern> 1628 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> { 1629 let Inst{24-23} = op24_23; 1630 let Inst{21-20} = op21_20; 1631 let Inst{19-18} = op19_18; 1632 let Inst{17-16} = op17_16; 1633 let Inst{11-7} = op11_7; 1634 let Inst{6} = op6; 1635 let Inst{4} = op4; 1636 1637 // Instruction operands. 1638 bits<5> Vd; 1639 bits<5> Vm; 1640 1641 let Inst{15-12} = Vd{3-0}; 1642 let Inst{22} = Vd{4}; 1643 let Inst{3-0} = Vm{3-0}; 1644 let Inst{5} = Vm{4}; 1645} 1646 1647// NEON 2 vector register with immediate. 1648class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 1649 dag oops, dag iops, Format f, InstrItinClass itin, 1650 string opc, string dt, string asm, string cstr, list<dag> pattern> 1651 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1652 let Inst{24} = op24; 1653 let Inst{23} = op23; 1654 let Inst{11-8} = op11_8; 1655 let Inst{7} = op7; 1656 let Inst{6} = op6; 1657 let Inst{4} = op4; 1658 1659 // Instruction operands. 1660 bits<5> Vd; 1661 bits<5> Vm; 1662 bits<6> SIMM; 1663 1664 let Inst{15-12} = Vd{3-0}; 1665 let Inst{22} = Vd{4}; 1666 let Inst{3-0} = Vm{3-0}; 1667 let Inst{5} = Vm{4}; 1668 let Inst{21-16} = SIMM{5-0}; 1669} 1670 1671// NEON 3 vector register format. 1672class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1673 dag oops, dag iops, Format f, InstrItinClass itin, 1674 string opc, string dt, string asm, string cstr, list<dag> pattern> 1675 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1676 let Inst{24} = op24; 1677 let Inst{23} = op23; 1678 let Inst{21-20} = op21_20; 1679 let Inst{11-8} = op11_8; 1680 let Inst{6} = op6; 1681 let Inst{4} = op4; 1682 1683 // Instruction operands. 1684 bits<5> Vd; 1685 bits<5> Vn; 1686 bits<5> Vm; 1687 1688 let Inst{15-12} = Vd{3-0}; 1689 let Inst{22} = Vd{4}; 1690 let Inst{19-16} = Vn{3-0}; 1691 let Inst{7} = Vn{4}; 1692 let Inst{3-0} = Vm{3-0}; 1693 let Inst{5} = Vm{4}; 1694} 1695 1696// Same as N3V except it doesn't have a data type suffix. 1697class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1698 bit op4, 1699 dag oops, dag iops, Format f, InstrItinClass itin, 1700 string opc, string asm, string cstr, list<dag> pattern> 1701 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> { 1702 let Inst{24} = op24; 1703 let Inst{23} = op23; 1704 let Inst{21-20} = op21_20; 1705 let Inst{11-8} = op11_8; 1706 let Inst{6} = op6; 1707 let Inst{4} = op4; 1708 1709 // Instruction operands. 1710 bits<5> Vd; 1711 bits<5> Vn; 1712 bits<5> Vm; 1713 1714 let Inst{15-12} = Vd{3-0}; 1715 let Inst{22} = Vd{4}; 1716 let Inst{19-16} = Vn{3-0}; 1717 let Inst{7} = Vn{4}; 1718 let Inst{3-0} = Vm{3-0}; 1719 let Inst{5} = Vm{4}; 1720} 1721 1722// NEON VMOVs between scalar and core registers. 1723class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1724 dag oops, dag iops, Format f, InstrItinClass itin, 1725 string opc, string dt, string asm, list<dag> pattern> 1726 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, NeonDomain, 1727 "", itin> { 1728 let Inst{27-20} = opcod1; 1729 let Inst{11-8} = opcod2; 1730 let Inst{6-5} = opcod3; 1731 let Inst{4} = 1; 1732 1733 let OutOperandList = oops; 1734 let InOperandList = !con(iops, (ins pred:$p)); 1735 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1736 let Pattern = pattern; 1737 list<Predicate> Predicates = [HasNEON]; 1738 1739 let PostEncoderMethod = "NEONThumb2DupPostEncoder"; 1740 1741 bits<5> V; 1742 bits<4> R; 1743 bits<4> p; 1744 bits<4> lane; 1745 1746 let Inst{31-28} = p{3-0}; 1747 let Inst{7} = V{4}; 1748 let Inst{19-16} = V{3-0}; 1749 let Inst{15-12} = R{3-0}; 1750} 1751class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1752 dag oops, dag iops, InstrItinClass itin, 1753 string opc, string dt, string asm, list<dag> pattern> 1754 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin, 1755 opc, dt, asm, pattern>; 1756class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1757 dag oops, dag iops, InstrItinClass itin, 1758 string opc, string dt, string asm, list<dag> pattern> 1759 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin, 1760 opc, dt, asm, pattern>; 1761class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1762 dag oops, dag iops, InstrItinClass itin, 1763 string opc, string dt, string asm, list<dag> pattern> 1764 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin, 1765 opc, dt, asm, pattern>; 1766 1767// Vector Duplicate Lane (from scalar to all elements) 1768class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops, 1769 InstrItinClass itin, string opc, string dt, string asm, 1770 list<dag> pattern> 1771 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> { 1772 let Inst{24-23} = 0b11; 1773 let Inst{21-20} = 0b11; 1774 let Inst{19-16} = op19_16; 1775 let Inst{11-7} = 0b11000; 1776 let Inst{6} = op6; 1777 let Inst{4} = 0; 1778 1779 bits<5> Vd; 1780 bits<5> Vm; 1781 bits<4> lane; 1782 1783 let Inst{22} = Vd{4}; 1784 let Inst{15-12} = Vd{3-0}; 1785 let Inst{5} = Vm{4}; 1786 let Inst{3-0} = Vm{3-0}; 1787} 1788 1789// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON 1790// for single-precision FP. 1791class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { 1792 list<Predicate> Predicates = [HasNEON,UseNEONForFP]; 1793} 1794